STM 8 S 003 F 3
STM 8 S 003 F 3
STM 8 S 003 F 3
Core
• 16 MHz advanced STM8 core with Harvard
architecture and 3-stage pipeline 7x7 mm 6.5x6.4 mm 3x3 mm
• Extended instruction set
Timers
Memories
• Advanced control timer: 16-bit, 4 CAPCOM
• Program memory: 8 Kbyte Flash memory; data
channels, 3 complementary outputs, dead-
retention 20 years at 55 °C after 100 cycles time insertion and flexible synchronization
• RAM: 1 Kbyte • 16-bit general purpose timer, with 3 CAPCOM
• Data memory: 128 bytes true data EEPROM; channels (IC, OC or PWM)
endurance up to 100 k write/erase cycles • 8-bit basic timer with 8-bit prescaler
Clock, reset and supply management • Auto wakeup timer
• Window and independent watchdog timers
• 2.95 V to 5.5 V operating voltage
• Flexible clock control, 4 master clock sources Communications interfaces
– Low-power crystal resonator oscillator
• UART with clock output for synchronous
– External clock input operation, SmartCard, IrDA, LIN master mode
– Internal, user-trimmable 16 MHz RC
• SPI interface up to 8 Mbit/s
– Internal low-power 128 kHz RC 2
• I C interface up to 400 Kbit/s
• Clock security system with clock monitor
• Power management Analog to digital converter (ADC)
– Low-power modes (wait, active-halt, halt) • 10-bit ADC, ± 1 LSB ADC with up to 5
– Switch-off peripheral clocks individually multiplexed channels, scan mode and analog
– Permanently active, low-consumption watchdog
power-on and power-down reset
I/Os
Interrupt management
• Up to 28 I/Os on a 32-pin package including
• Nested interrupt controller with 32 interrupts 21 high-sink outputs
• Up to 27 external interrupts on 6 vectors • Highly robust I/O design, immune against
current injection
Development support
• Embedded single-wire interface module
(SWIM) for fast on-chip programming and non-
intrusive debugging
Contents
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4 Product overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.14.1 UART1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.14.2 SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2
4.14.3 I C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
10 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
10.1 LQFP32 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
10.2 TSSOP20 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
10.3 UFQFPN20 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
10.4 Thermal
characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
10.4.1 Reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
10.4.2 Selecting the product temperature range . . . . . . . . . . . . . . . . . . . . . . . 97
11 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
List of tables
List of figures
Figure 48. TSSOP20 – 20-lead thin shrink small outline, 6.5 x 4.4 mm, 0.65 mm pitch,
package footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Figure 49. TSSOP20 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Figure 50. UFQFPN20 - 20-lead, 3 x 3 mm, 0.5 mm pitch, ultra thin fine pitch quad flat
package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Figure 51. UFQFPN20 - 20-lead, 3 x 3 mm, 0.5 mm pitch, ultra thin fine pitch quad flat
package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Figure 52. UFQFPN20 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
(1)
Figure 53. STM8S003F3/K3 value line ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . 98
1 Introduction
This datasheet contains the description of the STM8S003F3/K3 value line features, pinout,
electrical characteristics, mechanical data and ordering information.
• For complete information on the STM8S microcontroller memory, registers and
peripherals, please refer to the STM8S and STM8A microcontroller families reference
manual (RM0016).
• For information on programming, erasing and protection of the internal Flash memory
please refer to the PM0051 (How to program STM8S and STM8A Flash program
memory and data EEPROM).
• For information on the debug and SWIM (single wire interface module) refer to the
STM8 SWIM communication protocol and debug module user manual (UM0470).
• For information on the STM8 core, please refer to the STM8 CPU programming
manual (PM0044).
2 Description
The STM8S003F3/K3 value line 8 -bit microcontrollers offer 8 Kbytes of Flash program
memory, plus integrated true data EEPROM. They are referred to as low-density devices
in the STM8S microcontroller family reference manual (RM0016).
The STM8S003F3/K3 value line devices provide the following benefits:
performance, robustness and reduced system cost.
Device performance and robustness are ensured by true data EEPROM supporting up to
100000 write/erase cycles, advanced core and peripherals made in a state-of-the-art
technology at 16 MHz clock frequency, robust I/Os, independent watchdogs with separate
clock source, and a clock security system.
The system cost is reduced thanks to a high system integration level with internal clock
oscillators, watchdog, and brown-out reset.
Full documentation is offered as well as a wide choice of development tools.
Pin count 32 20
Max. number of GPIOs (I/O) 28 16
External interrupt pins 27 16
Timer CAPCOM channels 7 7
Timer complementary outputs 3 2
A/D converter channels 4 5
High-sink I/Os 21 12
Low-density Flash program 8K 8K
memory (byte)
RAM (byte) 1K 1K
True data EEPROM (byte) (1) (1)
128 128
Peripheral set Multi purpose timer (TIM1), SPI, I2C, UART, Window WDG,
independent WDG, ADC, PWM timer (TIM2), 8-bit timer (TIM4)
1. Without read-while-write capability.
3 Block diagram
Detector
POR BOR
RC int. 128 kHz
Window WDG
STM8 core
Independent WDG
Single wire
Debug/SWIM 8 Kbyte
debug interface
program Flash
128 byte
data EEPROM
Address and data bus
I2C
400 Kbit/s 1 Kbyte RAM
Up to
8 Mbit/s 4CAPCOM
SPI 16-bit advanced control
channels
timer (TIM1) + 3 complementary
outputs
LIN master
UART1
SPI emul. Up to
16-bit general purpose
3CAPCOM
timer (TIM2)
channels
up to 5 ADC1
channels 8-bit basic timer
(TIM4)
Beeper
1/2/4 kHz beep
AWU timer
4 Product overview
The following section intends to give an overview of the basic features of the
STM8S003F3/K3 value line functional modules and peripherals.
For more detailed information please refer to the corresponding family reference
manual (RM0016).
Addressing
• 20 addressing modes
• Indexed indirect addressing mode for look-up tables located anywhere in the address
space
• Stack pointer relative addressing mode for local variables and parameter passing
Instruction set
• 80 instructions with 2-byte average instruction size
• Standard data movement and logic/arithmetic functions
• 8-bit by 8-bit multiplication
• 16-bit by 8-bit and 16-bit by 16-bit division
• Bit manipulation
• Data transfer between stack and accumulator (push/pop) with direct stack access
• Data transfer using the X and Y registers or direct memory-to-memory transfers
4.2 Single wire interface module (SWIM) and debug module (DM)
The single wire interface module and debug module permits non-intrusive, real-time
in-circuit debugging and fast memory programming.
SWIM
Single wire interface module for direct access to the debug module and memory
programming. The interface can be activated in all device operation modes. The maximum
data transmission speed is 145 byte/ms.
Debug module
The non-intrusive debugging module features a performance close to a full-featured
emulator. Beside memory and peripherals, also CPU operation can be monitored in
real-time by means of shadow registers.
• R/W to RAM and peripheral registers in real-time
• R/W access to all resources by stalling the CPU
• Breakpoints on all program-memory instructions (software breakpoints)
• Two advanced breakpoints, 23 predefined configurations
The size of the UBC is programmable through the UBC option byte (Table 13), in
increments of 1 page (64-byte block) by programming the UBC option byte in ICP mode.
This divides the program memory into two areas:
• Main program memory: 8 Kbyte minus UBC
• User-specific boot code (UBC): Configurable up to 8 Kbyte
The UBC area remains write-protected during in-application programming. This means
that the MASS keys do not unlock the UBC area. It protects the memory used to store the
boot program, specific code libraries, reset and interrupt vectors, the reset routine and
usually the IAP and communication routines.
Option bytes
Programmable
area from 64 bytes
UBC area (1 page) up to 8
Remains write protected during IAP Kbytes
(in 1 page steps)
Low density
Flash program
memory
(8 Kbytes)
Program memory area
Write access possible for IAP
MS36408V1
Features
• Clock prescaler: To get the best compromise between speed and current
consumption the clock frequency to the CPU and peripherals can be adjusted by a
programmable prescaler.
• Safe clock switching: Clock sources can be changed safely on the fly in run mode
through a configuration register. The clock signal is not switched until the new clock
source is ready. The design guarantees glitch-free switching.
• Clock management: To reduce power consumption, the clock controller can stop
the clock to the core, individual peripherals or memory.
• Master clock sources: Four different clock sources can be used to drive the master
clock:
– 1-16 MHz high-speed external crystal (HSE)
– Up to 16 MHz high-speed user-external clock (HSE user-ext)
– 16 MHz high-speed internal RC oscillator (HSI)
– 128 kHz low-speed internal RC (LSI)
• Startup clock: After reset, the microcontroller restarts by default with an internal
2 MHz clock (HSI/8). The prescaler ratio and clock source can be changed by
the application program as soon as the code execution starts.
• Clock security system (CSS): This feature can be enabled by software. If an HSE
clock failure occurs, the internal RC (16 MHz/8) is automatically selected by the CSS
and an interrupt can optionally be generated.
• Configurable main clock output (CCO): This outputs an external clock for use by
the application.
4.9 Beeper
The beeper function outputs a signal on the BEEP pin for sound generation. The signal is
in the range of 1, 2 or 4 kHz.
The beeper output port is only available through the alternate function remap option bit
AFR7.
4.14.1 UART1
Main features
• 1 Mbit/s full duplex SCI
• SPI emulation
• High precision baud rate generator
• Smartcard emulation
• IrDA SIR encoder decoder
• LIN master mode
• Single wire half duplex mode
Synchronous communication
• Full duplex synchronous transfers
• SPI master operation
• 8-bit data communication
• Maximum speed: 1 Mbit/s at 16 MHz (fCPU/16)
4.14.2 SPI
• Maximum speed: 8 Mbit/s (fMASTER/2) both for master and slave
• Full duplex synchronous transfers
• Simplex synchronous transfers on two lines with a possible bidirectional data line
• Master or slave operation - selectable by hardware or software
• CRC calculation
• 1 byte Tx and Rx buffer
• Slave/master selection input pin
2
4.14.3 I C
• I2C master features
– Clock generation
– Start and stop generation
• I2C slave features
– Programmable I2C address detection
– Stop bit detection
• Generation and detection of 7-bit/10-bit addressing and general call
• Supports different communication speeds
– Standard speed (up to 100 kHz)
– Fast speed (up to 400 kHz)
PB2
PB3
PB7
PB1
PB0
PB6
TIM1 CH3N/AIN2/(HS)_
I2C SDA/(T)_
TIM1 ETR/AIN3/(HS)_
TIM1 CH1N/AIN0/(HS)_
MS37740V1
Input Output
Type
Alternate
PP
Ext.interrupt
floating
OD
wpu
LQFP32
Highsink
dSpee
Default
(1)
function
Pin name alternate
after remap
function
1 [option bit]
I/O - X - - - - - Reset -
2
NRST
I/O X X X - O1 X X Port A1 Resonator/ -
(2)
PA1/OSCIN crystal in
Mainfunction(afterreset
Input Output
)
LQFP32
Type
Alternate
PP
wp
OD
Ext.interrupt
Highsink
floating
Speed
Default
(1)
function
Pin name alternate
after remap
function
[option bit]
Mainfunction(afterreset
Input Output
)
LQFP32
Type
Alternate
PP
Ext.interrupt
wp
OD
Highsink
floating
Speed
Default
(1)
function
Pin name alternate
after remap
function
[option bit]
Timer 1 -
21 PC4/TIM1_CH4/C I/O X X X HS O3 X X Port C4 channel -
LK_CCO 4/configurable
clock output
22 PC5/SPI_SCK I/O X X X HS O3 X X Port C5 SPI clock -
23 PC6/SPI_MOSI I/O X X X HS O3 X X Port C6 SPI master -
out/slave in
24 PC7/SPI_MISO I/O X X X HS O3 X X Port C7 SPI master in/ -
slave out
25 PD0/[TIM1_BKIN X X X HS O3 X X Port D0 Timer 1 - break Configurable
[CLK_CCO] I/O input clock output
[AFR5]
26 (4) I/O X X X HS O4 X X Port D1 SWIM data -
PD1/SWIM
interface
PD2 X Port D2 Timer 2 -
27 I/O X X HS O3 X X - channel 3
[TIM2_CH3]
[AFR1]
28 PD3/TIM2_CH2 I/O X Port D3 Timer 2 -
X X HS O3 X X channel 2/ADC -
[ADC_ETR]
external trigger
29 PD4/BEEP/ I/O X Port D4 Timer 2 -
X X HS O3 X X channel -
TIM2_CH1
1/BEEP output
30 PD5/ UART1_TX I/O X X X HS O3 X X Port D5 UART1 data -
transmit
31 PD6/ UART1_RX I/O X X X HS O3 X X Port D6 UART1 data -
receive
32 PD7/TLI X X X HS O3 X X Port D7 Top level Timer 1 -
[TIM1_CH4] I/O interrupt channel 4
[AFR6]
1. I/O pins used simultaneously for high-current source/sink must be uniformly spaced around the package.
In addition, the total driven current must respect the absolute maximum ratings given in Section 9:
Electrical characteristics.
2. When the MCU is in Halt/Active-halt mode, PA1 is automatically configured in input weak pull-up and
cannot be used for waking up the device. In this mode, the output state of PA1 is not driven. It is
recommended to use PA1 only in input mode if Halt/Active-halt is used in the application.
3. In the open-drain output column, "T" defines a true open-drain I/O (P-buffer, weak pull-up, and
protection diode to VDD are not implemented).
4. The PD1 pin is in input pull-up during the reset phase and after the internal reset release.
PD5(HS)/AIN5/UART1 TX
PD6(HS)/AIN6/UART1 RX
PD2(HS)/AIN3/{TIM2 CH3]
PD4 (HS)/BEEP / TIM2 CH1/UART1 CK
NRST 1 15 PD1(HS)/SWIM
OSCIN/PA1 2 14 PC7(HS)/SPI_MISO[TIM1_CH2]
VCAP 5 11 PC4(HS)/TIM1_CH4/CLK_CCO/AIN2/[TIM1_CH2N]
6 7 8 9 10
V
[SPINSS]TIM2CH3/(HS)PA3
[ADCETR]I2CSCL/(T)PB4
CH1N][TLI]TIM1CH3/(HS)PC3
[TIM1BKIN]I2CSDA/(T)PB5
DD
[TIM1_
MS36409V1
Ext.interr.
function function
floating
Speed
wpu
Pin name Type alternate
High (after function after remap
OD PP
(1) reset) [option bit]
sink
Timer 2 -
PD4/ BEEP/ X channel
1 18 TIM2_ CH1/ I/O X X HS O3 X X Port D4 1/BEEP -
UART1 _CK output/
UART1 clock
2 19 PD5/ AIN5/ X Analog input
UART1 _TX I/O X X HS O3 X X Port D5 5/ UART1 -
data transmit
3 20 PD6/ AIN6/ X Analog input
UART1 _RX I/O X X HS O3 X X Port D6 6/ UART1 -
data receive
4 1 NRST I/O - X - - - - - Reset -
5 2 (2) I/O X X X - O1 X X Port A1 Resonator/ -
PA1/ OSCIN
crystal in
6 3 PA2/ OSCOUT I/O X X X - O1 X X Port A2 Resonator/ -
crystal out
7 4 VSS S - - - - - - - Digital ground -
8 5 VCAP S - - - - - - - 1.8 V regulator -
capacitor
9 6 VDD S - - - - - - - Digital power supply -
PA3/ TIM2_ CH3 X Timer 2 SPI master/
10 7 [SPI_ NSS] I/O X X HS O3 X X Port A3 channel 3 slave select
[AFR1]
PB5/ I2C_ SDA X Timer 1 -
8 I/O - X - O1 T(3) - Port B5 I2C data break input
11 [TIM1_ BKIN]
[AFR4]
ADC
9 PB4/ I2C_ SCL I/O X - X - O1 - Port B4 I2C clock external
12 T(3) trigger
[AFR4]
Top level
interrupt
PC3/ TIM1_CH3 X Timer 1 - [AFR3]
13 10 [TLI] I/O X X HS O3 X X Port C3 channel 3 Timer 1 -
[TIM1_ CH1N] inverted
channel 1
[AFR7]
Ext.interr.
TSSOP20
floating
Speed
wpu
alternate
High (after function after remap
PC4/ CLK_CCO/ OD PP
(1) reset) [option bit]
sink
Configurable
clock Timer 1 -
14 11 TIM1_ I/O X X X HS O3 X X Port C4 output/Timer inverted
CH4/AIN2/ 1 - channel channel 2
[TIM1_ CH2N] 4/Analog [AFR7]
input 2
12 PC5/ SPI_SCK X Timer 2 -
15[TIM2_ CH1] I/O X X HS O3 X X Port C5 SPI clock channel 1
13 PC6/ SPI_MOSI [AFR0]
16[TIM1_ CH1] X X X HS O3 X X Port C6 SPI master Timer 1 -
1. I/O pins used simultaneously for high current source/sink must be uniformly spaced around the package. In addition,
the total driven current must respect the absolute maximum ratings.
2. When the MCU is in halt/active-halt mode, PA1 is automatically configured in input weak pull-up and cannot be used for
waking up the device. In this mode, the output state of PA1 is not driven. It is recommended d to use PA1 only in input
mode if halt/active-halt is used in the application.
3. In the open-drain output column, "T" defines a true open-drain I/O (P-buffer, weak pull-up, and protection diode to VDD are
not implemented).
4. The PD1 pin is in input pull-up during the reset phase and after internal reset release.
Reserved
0x00 4000
Data EEPROM
0x00 407F
0x00 47FF Reserved
0x00 4800
Option bytes
0x00 480A
0x00 480B
Reserved
0x00 4FFF
0x00 5000
GPIO and periph. reg.
0x00 57FF
0x00 5800
Reserved
0x00 7EFF
0x00 7F00 CPU/SWIM/debug/ITC
registers
0x00 7FFF
0x00 8000
0x00 807F 32 interrupt vectors
0x00 8080
Flash program memory
(8 Kbyte)
0x00 9FFF
0x00 A000
Reserved
8 Option bytes
Option bytes contain configurations for device hardware features as well as the memory
protection of the device. They are stored in a dedicated block of the memory. Except for
the ROP (read-out protection) byte, each option byte has to be stored twice, in a regular
form (OPTx) and a complemented one (NOPTx) for redundancy.
Option bytes can be modified in ICP mode (via SWIM) by accessing the EEPROM address
shown in Table 12: Option bytes below. Option bytes can also be modified ‘on the fly’ by
the application in IAP mode, except the ROP option that can only be modified in ICP mode
(via SWIM).
Refer to the STM8S Flash programming manual (PM0051) and STM8 SWIM
communication protocol and debug module user manual (UM0470) for information on
SWIM programming procedures.
0x4803 Alternate OPT2 AFR7 AFR6 AFR5 AFR4 AFR3 AFR2 AFR1 AFR0 0x00
function
0x4804 remapping NOPT2 NAFR7 NAFR6 NAFR5 NAFR4 NAFR3 NAFR2 NAFR1 NAFR0 0xFF
(AFR)
0x4805 OPT3 Reserved HSITRIM LSI IWDG WWDG WWDG 0x00
_EN _HW _HW _HALT
Misc. option
0x4806 NOPT3 Reserved NHSI NLSI NIWDG NWWDG NWWDG 0xFF
TRIM _EN _HW _HW _HALT
0x4807 OPT4 Reserved EXT CKAWU PRS PRS 0x00
CLK SEL C1 C0
Clock option
0x4808 NOPT4 Reserved NEXT NCKAW NPR NPR 0xFF
CLK USEL SC1 SC0
0x4809 HSE clock OPT5 HSECNT[7:0] 0x00
1. Do not use more than one remapping option in the same port. It is forbidden to enable both AFR1 and
AFR0
2. Refer to the pinout description.
9 Electrical characteristics
STM8 pin
50 pF
STM8 pin
V
IN
1. All power (VDD) and ground (VSS) pins must always be connected to the external power supply
2. IINJ(PIN) must never be exceeded. This is implicitly insured if V IN maximum is respected. If VIN maximum cannot be
respected, the injection current must be limited externally to the I INJ(PIN) value. A positive injection is induced by
VIN>VDD while a negative injection is induced by V IN<VSS. For true open-drain pads, there is no positive injection
current, and the corresponding VIN maximum must always be respected
fCPU (MHz)
Functionality
not guaranteed 16
in this area
12 Functionality guaranteed
8 @TA -40 to 85 °C
0
2.95 4.0 5.0 5.5
Supply voltage
MS36411V1
ESR
RLeak
MSv36488V1
1. Legend: ESR is the equivalent series resistance and ESL is the equivalent inductance.
Table 21. Total current consumption with code execution in run mode at VDD = 5 V
Table 22. Total current consumption with code execution in run mode at VDD = 3.3 V
fCPU = fMASTER = 16 MHz HSE user ext. clock (16 MHz) 1.1 1.3
Supply HSI RC osc. (16 MHz) 0.89 1.1 mA
I current in HSI RC osc. (16 MHz) 0.7 0.88
DD(WFI) fCPU = fMASTER/128 = 125 kHz
wait mode f =f /128 =
CPU MASTER
HSI RC osc. (16 MHz/8)(2) 0.45 0.57
15.625 kHz
fCPU = fMASTER = 128 kHz LSI RC osc. (128 kHz) 0.4 0.54
Table 30. Total current consumption and timing in forced reset state
Symbol Parameter Conditions Typ Unit
Max(1)
I (2) 400 - µA
DD(R)
Supply current in reset state VDD = 5 V
VDD = 3.3 V 300 -
t Reset pin release to vector fetch - - 150 µs
RESETBL
Figure 12. Typ. IDD(RUN) vs fCPU, HSE user external clock, VDD = 5 V
Figure 14. Typ. IDD(WFI) vs. VDD HSE user external clock, fCPU = 16MHz
Figure 15. Typ. IDD(WFI) vs. fCPU, HSE user external clock, VDD = 5 V
V
HSEH
V
HSEL
f
HSE
External clock
source
OSCIN
STM8
MS36489V2
R
m
fHSE to core
CO RF
Lm
C CL1 OSCIN
m gm
Resonator
Consumption
Resonator control
OSCOUT
CL2
STM8
MS36490V3
1. Guaranteed by design.
General characteristics
Subject to general operating conditions for VDD and T A unless otherwise specified. All
unused pins must be kept at a fixed voltage: using the output mode of the I/O for example
or an external pull-up or pull-down resistor.
Output low level with 8 pins sunk IIO = 10 mA, VDD = 5 V - 0.8
V Output low level with 4 pins sunk -
OL IIO = 10 mA, VDD = 3.3 V 1.0(1)
Output low level with 4 pins sunk - (1) V
IIO = 20 mA, VDD = 5 V 1.5
Output high level with 8 pins sourced IIO = 10 mA, VDD = 5 V 4.0 -
(1)
V OH Output high level with 4 pins sourced I = 10 mA, V DD = 3.3 V 2.1 -
IO
(1)
Output high level with 4 pins sourced I = 20 mA, V DD = 5 V 3.3 -
IO
1. Data based on characterization results.
Figure 27. Typ. VOL @ VDD = 3.3 V (true open drain ports)
Figure 33. Typ. VDD - VOH @ VDD = 3.3 V (high sink ports)
The reset network shown in Figure 37 protects the device against parasitic resets. The user
must ensure that the level on the NRST pin can go below the V IL max. level specified in Table
38. Otherwise the reset is not taken into account internally. For power consumption sensitive
applications, the capacity of the external reset capacitor can be reduced to limit
charge/discharge current. If the NRST signal is used to reset the external circuitry, care must
be taken of the charge/discharge time of the external capacitor to fulfill the external device’s
reset timing conditions. The minimum recommended capacity is 10 nF.
VDD STM8
RPU
External
reset NRST Filter
circuit 0.1 μF
(Optional)
MSv36491V1
Unless otherwise specified, the parameters given in Table 43 are derived from
tests performed under ambient temperature, f MASTER frequency and VDD supply
voltage conditions. tMASTER = 1/fMASTER.
Refer to I/O port characteristics for more details on the input/output alternate function
characteristics (NSS, SCK, MOSI, MISO).
3. Min time is for the minimum time to invalidate the output and the max time is for the maximum time to put the data in Hi-Z.
(1)
Figure 39. SPI timing diagram - slave mode and CPHA = 1
NSS input
CPHA=1
SCK input
CPOL=0
tw(SCKH)
CPHA=1 tw(SCKL)
CPOL=1
ai14135b
1. Measurement points are done at CMOS levels: 0.3 VDD and 0.7 VDD.
(1)
Figure 40. SPI timing diagram - master mode
High
NSS input
t
c(SCK)
SCK Output
CPHA= 0
CPOL=0
CPHA= 0
CPOL=1
SCK Output
CPHA=1
CPOL=0
CPHA=1
CPOL=1
t t t
su(MI) w(SCKH) r(SCK)
t t
w(SCKL) f(SCK)
MISO
INP UT MSB IN BIT6 IN LSB IN
t
h(MI)
MOSI MSB OUT BIT1 OUT LSB OUT
OUTPUT
t t
v(MO) h(MO)
ai14136c
1. Measurement points are done at CMOS levels: 0.3 VDD and 0.7 VDD.
9.3.9 2
I C interface characteristics
2
Table 44. I C characteristics
Symbol Parameter 2 2 (1) Unit
Standard mode I C Fast mode I C
(2) (2) (2)
Min(2) Max Min Max
t SCL clock low time 4.7 - 1.3 - µs
w(SCLL)
t SCL clock high time 4.0 - 0.6 -
w(SCLH)
t SDA setup time 250 - 100 -
su(SDA)
t SDA data hold time -
h(SDA) 0(3) 0(4) 900(3)
t SDA and SCL rise time - 1000 - 300 ns
r(SDA)
t
r(SCL)
t SDA and SCL fall time - 300 - 300
f(SDA)
t
f(SCL)
t START condition hold time 4.0 - 0.6 - µs
h(STA)
t Repeated START condition setup time 4.7 - 0.6 -
su(STA)
t STOP condition setup time 4.0 - 0.6 - µs
su(STO)
V V
DD DD
4.7 kΩ 4.7 kΩ STM8
100 Ω
SDA
I²C bus SCL
100 Ω
START REPEATED
S TART
t START
su(STA)
SDA t
t r(SDA) t
f(SDA) su(SDA) t
STOP su(STA:STO)
t t
h(STA) w(SCLL) t
h(SDA)
SCL t
su(STO)
t t t
w(SCLH) r(SCL) f(SCL)
ai17490V2
1. Measurement points are made at CMOS levels: 0.3 x VDD and 0.7 x VDD
Table 47. ADC accuracy with RAIN < 10 kΩ RAIN, VDD = 3.3 V
Symbol Parameter Conditions Typ (1) Unit
Max
|E | (2) 1.6 3.5
Total unadjusted error fADC = 2 MHz
T
fADC = 4 MHz 1.9 4
(2) 1 2.5
|EO| Offset error fADC = 2 MHz
fADC = 4 MHz 1.5 2.5
(2) 1.3 3 LSB
|EG| Gain error fADC = 2 MHz
fADC = 4 MHz 2 3
(2) 0.7 1.0
|ED| Differential linearity error fADC = 2 MHz
fADC = 4 MHz 0.7 1.5
|E | (2) 0.6 1.5
Integral linearity error fADC = 2 MHz
L 0.8 2
fADC = 4 MHz
1. Data based on characterization results.
2. ADC accuracy vs. negative injection current: Injecting negative current on any of the analog input pins
should be avoided as this significantly reduces the accuracy of the conversion being performed on
another analog input. It is recommended to add a Schottky diode (pin to ground) to standard analog pins
which may potentially inject negative current. Any positive injection current within the limits specified for
IINJ(PIN) and ΣIINJ(PIN) in Section 9.3.6 does not affect the ADC accuracy.
1023 V –V EG
DDA SSA
1022 1LSB
= ----------------------------------------
IDEAL
1021 1024
(2)
7 ET (3)
6 (1)
5
EO
EL
4
3
ED
2
1 1 LSB
IDEAL
0
1 2 3 4 5 6 7 1021102210231024 V
V DDA
SSA
V STM8
DD
VT
R AINx 0.6V
AIN 10-bit A/D
V
AIN
C V conversion
IL C
AIN T ADC
0.6V
±1µA
Static latch-up
Two complementary static tests are required on 10 parts to assess the latch-up
performance:
• A supply overvoltage (applied to each power supply pin)
• A current injection (applied to each input, output and configurable I/O pin) is
performed on each sample.
This test conforms to the EIA/JESD 78 IC latch-up standard. For more details, refer to the
application note AN1181.
TA = 85 °C A
1. Class description: A Class is an STMicroelectronics internal specification. All its limits are higher than
the JEDEC specifications, that means when a device belongs to class A it exceeds the JEDEC
standard. B class strictly covers all the JEDEC criteria (international standard).
10 Package information
SEATING
PLANE
C
A2
A
A1
0.25 mm
GAUGE PLANE
ccc C
D K
A1
L
D1
L1
D3
24 17
25 16
b
E
E3
E1
32 9
PIN 1
8
IDENTIFICATION 1
e
5V_ME_V2
A - - 1.600 - - 0.0630
A1 0.050 - 0.150 0.0020 - 0.0059
A2 1.350 1.400 1.450 0.0531 0.0551 0.0571
b 0.300 0.370 0.450 0.0118 0.0146 0.0177
c 0.090 - 0.200 0.0035 - 0.0079
D 8.800 9.000 9.200 0.3465 0.3543 0.3622
D1 6.800 7.000 7.200 0.2677 0.2756 0.2835
D3 - 5.600 - - 0.2205 -
E 8.800 9.000 9.200 0.3465 0.3543 0.3622
E1 6.800 7.000 7.200 0.2677 0.2756 0.2835
E3 - 5.600 - - 0.2205 -
e - 0.800 - - 0.0315 -
L 0.450 0.600 0.750 0.0177 0.0236 0.0295
L1 - 1.000 - - 0.0394 -
k 0° 3.5° 7° 0° 3.5° 7°
ccc - - 0.100 - - 0.0039
1.20
24 17
25 16 0.50
0.30
7. 30
6.10
9.70 7.30
32 9
8
1
1.20
6.10
9.70
5V_FP_V2
Product (1)
identification STM8S003
K6T6C
Date code
Standard ST logo
Y WW
Revision code
Pin 1 identifier
MS37767V1
1. Parts marked as "ES", "E" or accompanied by an Engineering Sample notification letter, are not yet
qualified and therefore not yet ready to be used in production and any consequences deriving from such
usage will not be at ST charge. In no event, ST will be liable for any customer usage of these engineering
samples in production. ST Quality has to be contacted prior to any decision to use these Engineering
Samples to run qualification activity.
c
E1 E
SEATING 0.25 mm
PLANE GAUGE PLANE
C
1 10
PIN 1
IDENTIFICATION k
aaa C
A1 L
A A2 L1
b e
YA_ME_V3
Table 53. TSSOP20 – 20-lead thin shrink small outline, 6.5 x 4.4 mm, 0.65 mm
pitch, package mechanical data
Symbol millimeters (1)
inches
Min. Typ. Max. Min. Typ. Max.
A - - 1.200 - - 0.0472
A1 0.050 - 0.150 0.0020 - 0.0059
A2 0.800 1.000 1.050 0.0315 0.0394 0.0413
b 0.190 - 0.300 0.0075 - 0.0118
c 0.090 - 0.200 0.0035 - 0.0079
6.400 6.500 6.600 0.2520 0.2559 0.2598
D(2)
E 6.200 6.400 6.600 0.2441 0.2520 0.2598
4.300 4.400 4.500 0.1693 0.1732 0.1772
E1(3)
e - 0.650 - - 0.0256 -
L 0.450 0.600 0.750 0.0177 0.0236 0.0295
L1 - 1.000 - - 0.0394 -
k 0° - 8° 0° - 8°
aaa - - 0.100 - - 0.0039
1. Values in inches are converted from mm and rounded to four decimal digits.
2. Dimension "D" does not include mold flash, protrusions or gate burrs. Mold flash, protrusions or gate
burrs shall not exceed 0.15mm per side.
3. Dimension "E1" does not include interlead Flash or protrusions. Interlead Flash or protrusions shall
not exceed 0.25mm per side.
Figure 48. TSSOP20 – 20-lead thin shrink small outline, 6.5 x 4.4 mm,
0.65 mm pitch, package footprint
0.25
6.25
20 11
1.35
0.25
7.10 4.40
1.35
1 10
0.40
0.65 YA_FP_V1
Standard ST logo
Product
(1)
identification
8S003F3P6
Pin 1 identifier Date code Revision code
Y WW R
MS37768V1
1. Parts marked as "ES", "E" or accompanied by an Engineering Sample notification letter, are not yet
qualified and therefore not yet ready to be used in production and any consequences deriving from such
usage will not be at ST charge. In no event, ST will be liable for any customer usage of these engineering
samples in production. ST Quality has to be contacted prior to any decision to use these Engineering
Samples to run qualification activity.
TOP VIEW
D L1 ddd
L3 D1
e 10 L2 A3
5 e
b
E1 E
1 15
20 16 A1
L5
A
BOTTOM VIEW SIDE VIEW
A0A5_ME_V4
Table 54. UFQFPN20 - 20-lead, 3 x3 mm, 0.5 mm pitch, ultra thin fine pitch quad
flat package mechanical data
Symbol millimeters (1)
inches
Min Typ Max Min Typ Max
Figure 51. UFQFPN20 - 20-lead, 3 x 3 mm, 0.5 mm pitch, ultra thin fine
pitch quad flat package recommended footprint
A0A5_FP_V2
Product (1)
S033
identification
Date code
Revision code
Y WW R
Dot (pin 1)
MS37769V1
1. Parts marked as "ES", "E" or accompanied by an Engineering Sample notification letter, are not yet
qualified and therefore not yet ready to be used in production and any consequences deriving from such
usage will not be at ST charge. In no event, ST will be liable for any customer usage of these engineering
samples in production. ST Quality has to be contacted prior to any decision to use these Engineering
Samples to run qualification activity.
Using the values obtained in Section Table 55.: Thermal characteristics TJmax is
calculated as follows for LQFP32 7 x 7 mm = 60 °C/W:
TJmax = 75 °C + (60 °C/W x 464 mW) = 75 °C + 27.8 °C = 102.8 °C This
is within the range of the suffix 6 version parts (-40 < TJ < 105 °C).
In this case, parts must be ordered at least with the temperature range suffix 6.
11 Ordering information
(1)
Figure 53. STM8S003F3/K3 value line ordering information scheme
Product class
STM8 microcontroller
Family type
S = standard
(2)
Sub-family type
00x = Value line sub-family
003 = low density
Pin count
F = 20 pins
K = 32 pins
Package type
T = LQFP
P = TSSOP
U = UFQFPN
Temperature range
6 = -40 °C to 85 °C
Package pitch
(3)
No character = 0.5 mm or 0.65 mm
(4)
C = 0.8 mm
Packing
No character = Tray or tube
TR = Tape and reel
1. For a list of available options (e.g. memory size, package) and orderable part numbers or for further
information on any aspect of this device, please go to www.st.com or contact the ST Sales Office nearest
to you.
2. Refer to Table 1: STM8S003F3/K3 value line features for detailed description.
3. TSSOP and UFQFPN packages.
4. LQFP package.
Development tools for the STM8 microcontrollers include the full -featured STice emulation
system supported by a complete software tool package including C compiler, assembler
and integrated development environment with high -level language debugger. In addition,
the STM8 is to be supported by a complete range of tools including starter kits, evaluation
boards and a low-cost in-circuit debugger/programmer.
13 Revision history
Updated:
– All table footnotes from “Guaranteed by design, not
tested in production” to “Guaranteed by design” and
“Data based on characterization results, not tested in
production” to “Data based on characterization
results”
– Section 9.2: Absolute maximum ratings
– Section : Device marking for LQFP32 on page 90
03-May-2017 9 – Section : Device marking for TSSOP20 on page 92
– Section : Device marking for UFQFPN20 on page 95
– Table 54: UFQFPN20 - 20-lead, 3 x3 mm, 0.5 mm
pitch, ultra thin fine pitch quad flat package
mechanical data
– Figure 50: UFQFPN20 - 20-lead, 3 x 3 mm, 0.5 mm
pitch, ultra thin fine pitch quad flat package outline
– Figure 17: HSE external clock source was centered
into the frame.
30-Aug-2018 10 Updated:
– Table 34: HSI oscillator characteristics
STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and
improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information
on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order
acknowledgement.
Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance
or the design of Purchasers’ products.
Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product.
ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners.
Information in this document supersedes and replaces information previously supplied in any prior versions of this document.