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Describe The Memory Mapped

The memory mapped I/O scheme uses a single address space for both memory and I/O devices. Addresses are assigned to both memory locations and I/O devices, and I/O devices are treated as memory locations accessible via unique addresses. Data transfer instructions like MOV can access either memory locations or I/O devices depending on the address specified. In contrast, the I/O mapped I/O scheme uses separate address spaces for memory and I/O. The CPU has control lines to indicate whether an operation involves memory or I/O, and the same address can map to either depending on the control line status.

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154 views2 pages

Describe The Memory Mapped

The memory mapped I/O scheme uses a single address space for both memory and I/O devices. Addresses are assigned to both memory locations and I/O devices, and I/O devices are treated as memory locations accessible via unique addresses. Data transfer instructions like MOV can access either memory locations or I/O devices depending on the address specified. In contrast, the I/O mapped I/O scheme uses separate address spaces for memory and I/O. The CPU has control lines to indicate whether an operation involves memory or I/O, and the same address can map to either depending on the control line status.

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Sultan Ahmad
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AMIE NBCAFE STUDY NOTES

Describe the memory mapped I/O scheme.

In memory mapped I/O scheme we can use only one address space. This particular one address
space is allocated to both memory and I/O devices. In total memory address some addresses are
assigned to memories and some to I/O devices. But we have to assign the address for I/O
devices are different from the addresses which have been assigned to memories. In this scheme
remember that I/O device is also treated as a memory location. And one address is assigned to
each memory location (unique address) and one address is assigned to each I/O device.

Now if we explain it with some example then it will be very easy to understand so remember all
data transfer instructions of the microprocessor can be used for transferring data from and to
either memory or I/O devices. Now take a very good example, MOV C, M instruction would
transfer one byte of data from a memory location or it can also transfer an input device to the
register C, depending on whether the address in the H-L register pair is assigned to a memory
location or to an input device. If H-L contains address of a memory location, data will be
transferred from that memory location to register C, while if H-L pair contains the address of an
input device, data will be transferred from that input device to register C.

Explain the I/O mapped I/O scheme.

We know that Some CPUs provide one or more control lines like IO/ M line for 8085, which indicates
the status of operation, is memory or I/O operation. If we get the status of IO/ M line is high, it indicates
I/O operation and when we get low, it points to memory operation. But we have to remember main thing
that in this case the same address may be assigned to both memory and an I/O device depending on the
status of IO/M line.
The above mansion scheme is referred or we can call as I/O mapped I/O scheme. Look in this scheme two
separate address spaces exist. One space is meant exclusively for memory operations and the other for I/O
operations.

Now see block represent of memory allocation for above mansion scheme.

The following figure shows, pictorially, both the schemes. Here it is assumed that the system has a 64 KB
of memory and 256 I/O space.

Memory Mapped I/O I/O Mapped I/O


In Memory Mapped I/O Address width is 16-bit. A0 In I/O Mapped I/O Address width is 8-bit. A0 to A15
to A15 are used to generate address of the device. lines are used to generate address of the device.

MEMR and MEMW control signals are used to control IOR and IOW control signals are used to control read
read and write I/O operations respectively. and write I/O operations respectively.

Instructions available are STA addr, LDA addr, LDAX rp, IN and OUT are the only available instructions.
STAX rp, ADD M, CMP M, MOV r, M, etc.
Data transfer takes place between accumulator and I/O
Data transfer takes place between any register and I/O device.

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AMIE NBCAFE STUDY NOTES
device.

Maximum number of I/O devices that can be addressed Maximum number of I/O devices that can be addressed
is 65536 (theoretically). is 256.

Execution speed using STA addr, LDA addr is 13 T-state Execution speed is 10 T-states.
and for MOV M, r, etc.,it is 7-T states.

It requires more hardware circuitry because it decodes


16-bit address. It requires less hardware circuitry because it decodes 8-
bit address.

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