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Lab # 06 - 07

This document provides instructions for implementing a finite impulse response (FIR) filter using fixed point arithmetic in Verilog. Students are asked to 1) set the formats for coefficients, inputs, and outputs, 2) perform calculations to convert values from floating point to fixed point, 3) write Verilog code for the FIR filter and a testbench, and 4) verify simulations match calculations. The testbench should exhaustively test the filter by looping through input values and using a clock for timing instead of manual delays. Students must submit the source code, testbench, and RTL along with a properly formatted report.

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Hamza Ali
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54 views

Lab # 06 - 07

This document provides instructions for implementing a finite impulse response (FIR) filter using fixed point arithmetic in Verilog. Students are asked to 1) set the formats for coefficients, inputs, and outputs, 2) perform calculations to convert values from floating point to fixed point, 3) write Verilog code for the FIR filter and a testbench, and 4) verify simulations match calculations. The testbench should exhaustively test the filter by looping through input values and using a clock for timing instead of manual delays. Students must submit the source code, testbench, and RTL along with a properly formatted report.

Uploaded by

Hamza Ali
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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Center for Advanced Studies in Engineering, Islamabad

DIGITAL SYSTEMS DESIGN

EXPERIMENT # 6 and 7: Implementation of Finite


Impulse Response (FIR) filter using fixed point
arithmetic (Qn.m) and stimulus writing for exhaustive
testing

Name of students: …………………………………………………………………..

Roll No.: …………………………………………………………………………..

Date of Experiment: ………………………………………………………………

Report submitted on :………………………………………………….…………..

Marks obtained: …………………………


Remarks: ………………………………….

Instructor’s signature: ……………………..

Semester VI- Spring 2019

CE3201: Digital System Design Lab


C.A.S.E.
Center for Advanced Studies in Engineering

Introduction:

Digital signal processing can be separated into two categories - fixed point
and floating point. These designations refer to the format used to store and
manipulate numeric representations of data.

Fixed Point:
The term ‘fixed point’ refers to the corresponding manner in which numbers are
represented, with a fixed number of digits after, and sometimes before, the decimal point.
For example, a fixed-point representation with a uniform decimal point placement
convention can represent the numbers 123.45, 1234.56, 12345.67 etc.
• Place of decimal is fixed
• Simpler HW, low power, less silicon
• Converting FP simulation to Fixed-point simulation is time consuming

Floating Points:
With floating-point representation, the placement of the decimal point can ‘float’ relative
to the significant digits of the number.
A floating-point representation could in addition represent 1.234567, 123456.7,
0.00001234567, 1234567000000000 etc.
• Used where precision and dynamic range are important

• More Cost (Area, Speed, Power)

Filters:
Filtering is a class of signal processing, the defining feature of filters being the complete
or partial suppression of some aspect of the signal. Most often, this means removing
some frequencies and not others in order to suppress interfering signals and reduce
background noise.

FIR Filter:
In signal processing, a finite impulse response (FIR) filter is a filter whose impulse
response (or response to any finite length input) is of finite duration, because it settles to
zero in finite time. This is in contrast to infinite impulse response (IIR) filters, which may
have internal feedback and may continue to respond indefinitely (usually decaying).

CE3201: Digital System Design Lab 2


Lab Engineers: Sohaib Tallat / Irfan Ikhlaq
C.A.S.E.
Center for Advanced Studies in Engineering

For a FIR filter of order N, each value of the output sequence is a weighted sum of the
most recent input values:

Lab Task:
You need to implement the given fir filter in Verilog and write a testbench for exhaustive
testing. Follow the given guidelines properly to implement task successfully.

CE3201: Digital System Design Lab 3


Lab Engineers: Sohaib Tallat / Irfan Ikhlaq
C.A.S.E.
Center for Advanced Studies in Engineering

The required parameters for the coefficients and input are given in table:

SIGNED

Procedure:
1) First of all, set the formats for each coefficient, input and output.
2) Perform the required arithmetic operations after conversions (floating to fixed point)
on page and fill the table 4.2 with your calculated values.
3) Write a Verilog code and a appropriate test bench for the above filter accordingly.
4) Verify your simulations with the help of calculations performed.

Calculated Results:
Filter Parameters Floating Point Fixed Point
a 0.0625
b -0.375
c 2.5
x -8.0
a_r
CE3201: Digital System Design Lab 4
Lab Engineers: Sohaib Tallat / Irfan Ikhlaq
C.A.S.E.
Center for Advanced Studies in Engineering

b_r
c_r
ab
y[n]
x -4.0
a_r
b_r
c_r
ab
y[n]

For Exhaustive testing:


 Use a for loop to simulate values of input (x) from 0  -8.
 Generate a 100 MHz clock and set the sensitivity of the always block in UUT at
positive edge of the clock.
 In the for loop of testbench, instead of using a manual delay command, give delay
until the positive edge of clock is detected.
Syntax: instead of #10 use @(posedge clk);

Expected Results:

CE3201: Digital System Design Lab 5


Lab Engineers: Sohaib Tallat / Irfan Ikhlaq
C.A.S.E.
Center for Advanced Studies in Engineering

NOTE:
For submission of lab report, ensure that:
1. You have attached the Source code, Test bench, and the RTL of the
task. Report should be properly formatted.
2. Convert word file to PDF.
3. Name the file according to lab number and your section.
e.g. (E15/082)-(E15/120)-Lab#5-(Section-A)
4. Email the lab report to [email protected] with the subject
as follows:
(E15/082)-(E15/120)-Lab#5-(Section-A)
Replace your roll numbers, section and lab number appropriately.

CE3201: Digital System Design Lab 6


Lab Engineers: Sohaib Tallat / Irfan Ikhlaq
C.A.S.E.

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