APPROVED BY AICTE NEW DELHI, AFFILIATED TO VTU, BELGAUM

DEPARTMENT OF ELECTRONICS & COMMUNICATION

ENGINEERING

ANALOG ELECTRONICS LABORATORY

LAB MANUAL – 15ECL37
III-SEMESTER
2016-2017

Prepared by: Reviewed by: Approved by:

Pavan V S Kavitha M V Dr. A.A. Powly Thomas

Assistant Professor Head of the Department Principal
Dept. of ECE Dept. of CSE GCEM
GCEM GCEM

81/1, 182/1, Hoodi Village, Sonnenahalli, K.R. Puram, Bengaluru,

Karnataka-560048.
CONTENTS

S.No Title Page No

1. Syllabus ii

2. Course objective iii

3. Course outcome iii

4. Do‟s & Don‟ts iv

5. List of experiments v

6. Viva questions 47-48

7. Appendix-1 49-52
 Analog Electronics Laboratory Manual - 10ESL37

SYLLABUS

1. Design and set up the following rectifiers with and without filters
and to determine ripple factor and rectifier efficiency:
Full Wave Rectifier (b) Bridge Rectifier

2. Conduct experiment to test diode clipping (single/double ended) and

clamping circuits (positive/negative).

3. Conduct an experiment on Series Voltage Regulator using Zener diode and

power transistor to determine line and load regulation characteristics.

4. Realize BJT Darlington Emitter follower with and without bootstrapping and
determine the gain, input and output impedances.

5. Design and set up the BJT common emitter amplifier using voltage divider bias
with and without feedback and determine the gain bandwidth product from its
frequency response.

6. Plot the transfer and drain characteristics of a JFET and calculate its drain
resistance, mutual conductance and amplification factor.

7. Design, setup and plot the frequency response of Common Source

JFET/MOSFET amplifier and obtain the bandwidth.

8. Plot the transfer and drain characteristics of n-channel MOSFET and calculate
its parameters, namely; drain resistance, mutual conductance and
amplification factor.

9. Set-up and study the working of complementary symmetry class B push pull
power amplifier and calculate the efficiency.

10.Design and set-up the RC-Phase shift Oscillator using FET, and calculate the
frequency of output waveform.

11.Design and set-up the following tuned oscillator circuits using BJT, and
determine the frequency of oscillation.
a) Hartley Oscillator (b) Colpitts Oscillator
12.Design and set-up the crystal oscillator and determine the frequency of
oscillation.

Dept of ECE- GCEM Page ii

 Analog Electronics Laboratory Manual - 10ESL37

Course objectives:
This laboratory course enables students to get practical experience in design,
assembly, testing and evaluation of

 Rectifiers and Voltage Regulators.

 BJT characteristics and Amplifiers.

 JFET Characteristics and Amplifiers.

 MOSFET Characteristics and Amplifiers.

 Power Amplifiers.

 RC-Phase shift, Hartley, Colpitts and Crystal Oscillators

Course outcomes:
Through this course, the students:

 Acquire a basic knowledge in solid state electronics including diodes, MOSFET,

BJT, and operational amplifier.

 Develop the ability to analyze and design analog electronic circuits using
discrete components.

 Observe the amplitude and frequency responses of common amplification

circuits.

 Design, construct, and take measurement of various analog circuits to compare

experimental results in the laboratory with theoretical analysis.

Dept of ECE- GCEM Page iii

 Analog Electronics Laboratory Manual - 10ESL37

LAB INSTRUCTIONS

Do’s
 Ensure your presence five minutes before the commencement of the lab.

 Attend all the lab sessions without fail.

 Come well prepared for every lab session.

 Complete and Bring the Lab records regularly.

 Ensure the proper polarity of cables before connecting the kits.

 Ensure the checking of the circuit of circuit connections before turning ON

the circuit.

 Tuck in your shirts and not to play with instruments laid on the bench.

 Wearing loose garments inside the lab is strictly prohibited.

 You have to wear shoes compulsorily.

 Keep the space around you clear for others.

Don’ts
 Don‟t bring the Cell phone and food items to Lab.

 Don‟t switch ON voltage supplies after making circuit connections in the

absence of the teacher.

 Don‟t rotate the Knobs unnecessarily.

Dept of ECE- GCEM Page iv

 Analog Electronics Laboratory Manual - 10ESL37

LIST OF EXPERIMENTS

Sl No Title Page No
1 Rectifiers 1
2 Clippers and Clampers 7
3 Zener Diode 20
4 BJT Amplifiers 23
5 BJT Darlington Emitter Follower 27
6 Hartley and Colpitts oscillator 31
7 Crystal Oscillator 38
8 Class B push –Pull amplifier 41
9 JFET Characteristics 43
10 JFET Common Source Characteristics 47

Dept of ECE- GCEM Page v

 Analog Electronics Laboratory Manual - 10ESL37

Experiment No : 1 DATE :
FULL WAVE RECTIFIER
AIM:
To study the full wave rectifier and to calculate ripple factor and efficiency
and Regulation with filter and without filter.

COMPONENTS REQUIRED:

Sl. No. Components Details Specification Qty

1. Diodes BY127 2 Nos.
2. Capacitor 0.1µf, 470µf Each 1 No.
3. Power Resistance Board 1 No.
4. Step down Transformer 12 V 1 No.
5. CRO, Multimeter, Milliammeter, Connecting Board

THEORY:
The center tapped full wave rectifier circuit is similar to a half wave rectifier
circuit, using two diodes and a center tapped transformer. Both the input half
cycles are converted into unidirectional pulsating DC.
CIRCUIT DIAGRAM:
FULL WAVE RECTIFIER WITHOUT FILTER CAPACITOR
Step down
Transformer
Ammeter(0-250mA)
12V C2
A K
A
BY127
+ - 0.1UF

AC
(230V/50HZ) 0
VO(DC) VO (AC)
RL

A K

12V BY127

Dept of ECE- GCEM Page 1

 Analog Electronics Laboratory Manual - 10ESL37

FULL WAVE RECTIFIER WITH FILTER CAPACITOR

Step down
Transformer
Ammeter(0-250mA)
12V C2
A K
A
BY127
+ - 0.1UF

AC
(230V/50HZ) 0
+ VO(DC) VO(AC)
RL
C1
A K
470UF -
12V BY127

DESIGN:

Vin rms = 12V

Vin m =  2Vin rms = 16.97V
VO DC = 2Vm/ = 10.8V
Given VO DC = 10V
IO DC = 100mA
RL = VO DC / IO DC = 100

Ripple = r = Vo rms / VO DC = 0.48

Design for the filter capacitor
Ripple = 1/(43 f C RL)

Given r = .06
C = 1/(43 f r RL)
RL = 100
f = 50Hz

= 470UF

Efficiency  = PDC /PAC  (I2DC * RL) / [(Irms)2 * (RL + RF)]

Regulation % Regulation =
VNL  VFL
100
VFL

PROCEDURE:
1. Connections are made as shown in the circuit diagram
2. Switch on the AC power supply

Dept of ECE- GCEM Page 2

 Analog Electronics Laboratory Manual - 10ESL37

3. Observe the wave form on CRO across the load resistor and measure the o/p
amplitude and frequency.
4. Note down RL, IDC, VODC , Vinac, Voac in the tabular column for different load
resistances.
5. Calculate the ripple and efficiency and regulation for each load resistance.
6. Repeat the above procedure with filter capacitor.

TABULAR COLUMN:
Sl. VO VIN VO
RL IDC Ripple Efficiency Regulation
No. (DC) (AC) (AC)

WAVEFORMS:

t
VIN 0

0 Vo (Without Filter)
VO

VC

Vo (with filter)

Dept of ECE- GCEM Page 3

 Analog Electronics Laboratory Manual - 10ESL37

Experiment No : 1b DATE :
BRIDGE RECTIFIER
AIM:
To study the bridge rectifier and to calculate ripple factor and efficiency and
regulation with filter and without filter.
COMPONENTS REQUIRED:

Sl. No. Components Details Specification Qty

1. Diodes BY127 4 Nos.
2. Capacitor 0.1µf, 470µf Each 1 No.
3. Power Resistance Board 1 No.
4. Step down Transformer 12 V 1 No.
5. CRO, Multimeter, Milliammeter, Connecting Board

THEORY:
The bridge rectifier circuit is essentially a full wave rectifier circuit, using
four diodes, forming the four arms of an electrical bridge. To one diagonal of the
bridge, the ac voltage is applied through a transformer and the rectified dc voltage
is taken from the other diagonal of the bridge. The main advantage of this circuit
is that it does not require a center tap on the secondary winding of the
transformer; ac voltage can be directly applied to the bridge.
The bridge rectifier circuit is mainly used as a power rectifier circuit for
converting ac power to dc power, and a rectifying system in rectifier type ac
meters, such as ac voltmeter in which the ac voltage under measurement is first
converted into dc and measured with conventional meter.
CIRCUIT DIAGRAM:
BRIDGE RECTIFIER WITHOUT FILTER CAPACITOR
Step down
Transformer
Ammeter(0-250mA)
12V BRIDGE C2
1 A
+ - 0.1UF

AC
(230V/50HZ) 0 2 - + 4

RL Vo
3
12V

Dept of ECE- GCEM Page 4

 Analog Electronics Laboratory Manual - 10ESL37

BRIDGE RECTIFIER WITH FILTER CAPACITOR

Step down
Transformer
Ammeter(0-250mA)
12V B RIDGE C2

A
+ - 0.1UF

1
AC
(230 V/50 HZ) 0 2 - + 4

+
C1
RL Vo

3
47 0UF

-
12V

DESIGN:

Vin rms = 12V

Vin m =  2Vin rms = 16.97V
VO DC = 2Vm/ = 10.8V
Given VO DC = 10V
IO DC = 100mA
RL = VO DC / IO DC = 100

Ripple = r = Vo rms / VO DC = 0.48

Design for the filter capacitor
Ripple = 1/(43 f C RL)

Given r = .06
C = 1/(43 f r RL)
RL = 100
f = 50Hz

= 470UF

Efficiency
 = PDC /PAC
= (I2DC * RL) / [(Irms)2 * (RL + RF)]

Regulation % Regulation =
VNL  VFL
100
VFL

Dept of ECE- GCEM Page 5

 Analog Electronics Laboratory Manual - 10ESL37

PROCEDURE:

1. Connections are made as shown in the circuit diagram

2. Switch on the AC power supply
3. Observe the wave form on CRO across the load resistor and measure the
o/p amplitude and frequency.
4. Note down RL, IDC, VODC , Vinac, Voac in the tabular column for different load
resistances.
5. Calculate the ripple factor, efficiency and regulation for each load
resistance.
6. Repeat the above procedure with filter capacitor.
TABULAR COLUMN:
Sl. RL VO VIN VO
IDC Ripple Efficiency Regulation
No. (DC) (AC) (AC)

WAVEFORMS:
Vin
20

t
0

- 20

Vo
0 Vo (Without Filter)

Vo (with filter)
VC

Dept of ECE- GCEM Page 6

 Analog Electronics Laboratory Manual - 10ESL37

Experiment No : 2a DATE :
CLAMPING CIRCUITS
AIM:
Design a clamping circuit for the given output.
COMPONENTS REQUIRED:

Sl. No. Components Details Specification Qty

1. Diodes BY127 1 No
2. Capacitors 0.1 F 1 No
Signal generator, Cathode Ray Oscilloscope (CRO) with
Probes, Dual Power Supply, Connecting Board

THEORY:
A clamper is one, which provides a D.C shift to the input signal. The D.C
shift can be positive or negative. The clamper with positive D.C shift is called
positive clamper and clamper with negative shift is called negative clamper.
Consider a clamper circuit shown below.
0.1u

+ -
C D1
Vin Vo
BY 127

In the positive half cycle as the diode is forward biased the capacitor charges to
the value VIN  VD  with the polarity as shown in the figure. In the negative half

cycle the diode is reverse biased. Hence the output is VO  VIN  VC .

Initially let us assume that the capacitor has charged to VIN  VD  i.e.

(5 – 0.5) = 4.5V
Then in the positive half cycle diode is forward biased and applying KVL to
the loop,
Vin –VC –V0 = 0 V0 =Vin –VC
When Vin = 0 V0 = 0 - 4.5 = - 4.5V
Vin = 5V V0 = 5 – 4.5 = 0.5V
In the negative half cycle
When Vin = -5V V0 = -5 – 4.5 = -9.5V
The output shifts between 0.5V and – 9.5V.Here the output has shifted
down by 4.5V

Dept of ECE- GCEM Page 7

 Analog Electronics Laboratory Manual - 10ESL37

The peak to peak voltage at the output of a clamper is the same as that of
the input.
CIRCUIT DIAGRAM AND DESIGN:
Given Vin = 10V (p-p)
A] In the positive half cycle:
Diode is forward biased.
Applying KVL to loop 1
Vin – VC – VD = 0
0.1u
VC = Vin – VD
+ -
= 5 - 0.5  4.5V C D1
Vin Vo
In the negative half cycle: BY 127

Vin – VC – V0 = 0
V0 = Vin – VC
When Vin = 0 V0 = - 4.5V
When Vin = 5V V0 = 0.5V
When Vin = -5V V0 = -9.5V
B]In the negative half cycle:
Diode is forward biased
0.1u
Applying KVL to loop 1 - +
C
Vin + VC + VD = 0 BY127
D1
Vin Vo
VC = - ( Vin + VD)
VC = - (-5 + 0.5)
= 4.5V
In the positive half cycle:
Diode is reverse biased.
Apply KVL to the loop
Vin + VC – V0 = 0
V0 = Vin + VC
When Vin = 0 V0 = 4.5V
When Vin = 5V V0 = 5 + 4.5 = 9.5V
When Vin = - 5V V0 = - 0.5V

Dept of ECE- GCEM Page 8

 Analog Electronics Laboratory Manual - 10ESL37

C] Assume VR = 2V
In the positive half cycle:
Diode is forward biased.
Apply KVL to loop 1
Vin – VC – VD – VR = 0
VC = Vin – VD – VR 0.1u
= 5 - 0.5 – 2 + -
C
D1 BY127
= 2.5V Vin Vo
In the negative half cycle:
VR
Diode is reverse biased
Vin – VC – V0 = 0
V0 = Vin – VC
When Vin = 0V V0 = - 2.5V
When Vin = 5V V0 = 2.5V
When Vin = -5V V0 = -7.5V
D] Assume VR = 2V
In the positive half cycle: 0.1u
Diode is forward biased and the capacitor charges. + -
C
D1 BY127
Apply KVL to loop 1 Vin Vo
Vin – VC – VD + VR = 0 VR
VC = Vin – VD + VR
= 5 –0.5 +2
= 6.5V
In the negative half cycle:
Vin – VC – V0 = 0
V0 = Vin – VC
When Vin = 0V V0 = - 6.5V
When Vin = 5V V0 = - 1.5V
When Vin = -5V V0 = - 11.5V

Dept of ECE- GCEM Page 9

 Analog Electronics Laboratory Manual - 10ESL37

E]In the negative half cycle:

Assume VR = 2V
Diode is forward biased and capacitor charges.
Apply KVL to the loop1
Vin + VC + VD + VR = 0
0.1u
VC = - ( Vin + VR + VD)
- +
= - (- 5 + 0.5 + 2) C
BY127 D1
= 2.5V Vin Vo
From the fig. we see that VR

Vin + VC – V0 = 0
V0 = Vin + VC
When Vin = 0 V0 = 2.5V
When Vin = 5V V0 = 7.5V
When Vin = -5V V0 = -2.5V
F] VR = 2V
0.1u
In the negative half cycle: - +
C
Diode is forward biased and capacitor charges. BY127 D1
Vin Vo
Apply KVL to loop 1
VR
Vin + VC + VD - VR =0
VC = - ( Vin + VD - VR)
= - (- 5 + 0.5 – 2)
= 6.5V
From the circuit we see that,
Vin + VC - V0 =0
V0 = Vin – VC
When Vin =0V V0=6.5V
When Vin = 5V V0= 11.5V
When Vin = - 5V V0= 1.5V
PROCEDURE:
1. Rig up the circuit as shown in the circuit diagram.
2. Give a sinusoidal input of 10V peak to peak
3. Check and verify the output.

Dept of ECE- GCEM Page 10

 Analog Electronics Laboratory Manual - 10ESL37

WAVEFORMS:
Vin
5V

0 t

- 5V

V0

0.5
0 t
[A]
- 4.5

- 9.5

V0

9.5

4.5

[B] 0 t
- 0.5

V0

2.5
0
[C] t
- 2.5

- 7.5

Dept of ECE- GCEM Page 11

 Analog Electronics Laboratory Manual - 10ESL37

V0

0 t
[D] - 1.5

- 6.5

- 11.5

V0
7.5

2.5

[E] 0 t

- 2.5

V0
11.5

6.5
[F]
1.5
0 t

RESULT :

Dept of ECE- GCEM Page 12

 Analog Electronics Laboratory Manual - 10ESL37

Experiment No : 2b DATE :
CLIPPING CIRCUITS
AIM:
Design a clipping circuit for the given values.
COMPONENTS REQUIRED:

Sl. No. Components Details Specification Qty

1. Diodes BY127 1 No
2. Resistors 10 K 1 No

THEORY:
The process by which the shape of a signal is changed by passing the signal
through a network consisting of linear elements is called linear wave shaping.
Most commonly used wave shaping circuit is clipper. Clipping circuits are those,
which cut off the unwanted portion of the waveform or signal without distorting
the remaining part of the signal. There are two types of clippers namely parallel
and series. A series clipper is one in which the diode is connected in series with
the load and a parallel clipper is one in which the diode is connected in parallel
with the load.

CIRCUIT DIAGRAM AND DESIGN:

Assume Vin = 10V (Peak to Peak) (a) D1

(a) Consider the circuit in fig. 1 BY127

Vin Vo
10k
In the positive half cycle D is forward biased
 V0 = Vin – 0.5 = 5 – 0.5 = 4.5 (0.5V is the diode drop)
In the negative half cycle D is reverse biased
 V0 = 0V
(b) Consider the circuit in fig. 2 D1
In the positive half cycle D is reverse biased
BY127
 V0 = 0V Vin 10k Vo

In the negative half cycle D is forward biased

Applying KVL to the loop
 Vin + VD – V0 = 0
 V0 = Vin + VD = -5 + 0.5 = - 4.5V

Dept of ECE- GCEM Page 13

 Analog Electronics Laboratory Manual - 10ESL37

(c) Consider the circuit in fig. 3

Given VR = 2.5V
In the positive half cycle
(i) When |Vin| > |VD + VR|, D is forward biased
Applying KVL, we get D1 VR
Vin = VD + VR + V0 BY127
Vin 10k Vo
V0 = Vin – VD – VR
V0 = 5 – 0.5 – 2.5
V0 = 2V
(ii) When |Vin| < |VD + VR|, D is reverse biased
V0 = 0V
In the negative half cycle, D is reverse biased
V0 = 0V
(d) Consider the circuit in fig. 4
Assume VR = 3V
In the positive half cycle, D is reverse biased
V0 = 0V
In the negative half cycle
(i) When |Vin| > |VD + VR|, D is forward biased
Applying KVL, we get D1 VR
Vin = - VD - VR + V0
BY127
V0 = Vin + VD + VR Vin 10k Vo

V0 = -5 + 0.5 + 3
V0 = -1.5V
(ii) When |Vin < |VD + VR|, D is reverse biased
V0 = 0V

Dept of ECE- GCEM Page 14

 Analog Electronics Laboratory Manual - 10ESL37

(e) Consider the circuit in fig. 5

Assume VR1 = 2.5V and VR2 = 3V
In the positive half cycle, D2 is reverse biased
(i) When |Vin| > |VD1 + VR1|, D1 is forward biased
Applying KVL, we get
BY127
Vin = VD1 + VR1 + V0 D2
VR2

V0 = Vin - VD1 - VR1

V0 = 5 - 0.5 – 2.5 Vin BY127 D1 VR1 10k Vo
2

V0 = 2V 1

(ii) When |Vin < |VD1 + VR1|, D1 is reverse biased

V0 = 0V
In the negative half cycle
(i) When |Vin| > |VD2 + VR2|, D2 is forward biased
Applying KVL, we get
Vin = - VD - VR + V0
V0 = Vin + VD2 + VR2
V0 = -5 + 0.5 + 3
V0 = -1.5V
(ii) When |Vin < |VD2 + VR2|, D2 is reverse biased

V0 = 0V
(f) Consider the circuit in fig. 6
During the positive half cycle, D is forward biased 10k
V0 = VD = 0.5V
BY127
During negative half cycle, D is reverse biased Vin Vo
D1
V0 = Vin

Dept of ECE- GCEM Page 15

 Analog Electronics Laboratory Manual - 10ESL37

(g) Consider the circuit in fig. 7

During positive half cycle,
10k
D is reverse biased
D1
V0 = Vin Vin BY127 Vo
During negative half cycle,
D is forward biased
V0 = -VD = -0.5V
(h) Consider the circuit in fig. 8
During positive half cycle 10k
(i) When |Vin| > |VD + VR|, D1
D is forward biased BY127
Vin
V0 = VD + VR = 0.5 + 2.5 Vo
V0 = 3V VR
(ii) When |Vin| < |VD + VR|, D is reverse biased
V0 = Vin
During negative half cycle, D is reverse biased
V0 = Vin
(i)Consider the circuit in fig. 9
Assume VR = 2.5V
During positive half cycle, 10k
D is reverse biased +
D1
V0 = Vin BY127
During negative half cycle Vin Vo
(i) When |Vin| > |VD + VR|, VR
D is forward biased -

Applying KVL to the loop, we get

V0 = -VD - VR = - 0.5 - 2.5
V0 = -3V
(ii) When |Vin| < |VD + VR|,
D is reverse biased
V0 = Vin
During negative half cycle, D is reverse biased
V0 = Vin

Dept of ECE- GCEM Page 16

 Analog Electronics Laboratory Manual - 10ESL37

(j) Consider the circuit in fig. 10

Assume VR1 = VR2 = 2.5V
During positive half cycle, D2 is reverse biased.
(i) When |Vin| > |VD1 + VR1|, D1 is forward biased
V0 = VD1 + VR1 = 0.5 + 2.5
V0 = 3V
10k
(ii) When |Vin| < |VD1 + VR1|,
D1 is reverse biased D1 D2
BY127 BY127
V0 = Vin Vin Vo Vo
During negative half cycle,
VR1 VR2
D1 is reverse biased 1
(i)When |Vin| > |VD2 + VR2|, D2 is forward biased
Applying KVL to the loop, we get
V0 = -VD2 - VR2 = -0.5 - 2.5
V0 = -3V
(ii) When |Vin| < |VD2 + VR2|, D2 is reverse biased
V0 = Vin
(k) Consider the circuit in fig. 11 10k
Assume VR1 = 3.5V and VR2 = 2V
D1 D2
During positive half cycle
(i) When |Vin| > |VD1 + VR1| Vin BY127 BY127 Vo

D1 is forward biased and VR1 VR2

D2 is reverse biased
V0 = VD1 + VR1 = 0.5 + 3.5 = 4 V
(ii) When |Vin| < |VR2 – VD2|
D1 is reverse biased and
D2 is forward biased
V0 = -VD2 + VR2 = - 0.5 + 2  1.5V
During negative half cycle,
D1 is reverse biased and D2 is forward biased
V0 = -VD2 + VR2 = - 0.5 + 2  V0 = 1.5V
PROCEDURE:
1. Rig up the circuit as shown in the fig.
2. Give a sinusoidal input of 10V peak to peak.
3. Check the output at the output terminal.
4. To plot the transfer characteristics, connect channel 1 of the CRO to the
output and channel 2 to the input and press the XY knob
5. Adjust the grounds of both the channels to the centre.
6. Measure the designed values.

Dept of ECE- GCEM Page 17

 Analog Electronics Laboratory Manual - 10ESL37

WAVEFORMS:
Series Clipper
Vin
5
3
0 t
- 3.5
-5
Vo Vo

4.5
Vin

(a) 0 t

Vo
Vo
(b)
0 t Vin

- 4.5

Vo

2.0
Vin
(c)
0 t 3

Vo

-3.5
(d) 0 t Vin

-1.5

Vo

2 -3.5
Vin
(e) 0 t 3

-1.5

RESULT :

Dept of ECE- GCEM Page 18

 Analog Electronics Laboratory Manual - 10ESL37

Shunt Clipper
Vin
+5
0 t

+5

Vo

(f) 0.5 t Vin

0.5
-5

Vo
4.5

Vin
(g) 0 t 0.5

Vo
VO
3 3.0

(h) t Vin

-5

Vo
+5
(i) 0 t -3.0
Vin
-3

Vo

+3
Vin
(j) 0 t 3.0

-3
Vo
+4
1.5
(k) 0 t Vin

Dept of ECE- GCEM Page 19

 Analog Electronics Laboratory Manual - 10ESL37

Experiment : 03 DATE :
ZENER DIODE
AIM:
To study zener diode as voltage regulator, To calculate % line regulation, To
calculate % load regulation.

APPARATUS: Zener diode, Resistors, Power supply, Multi meter.

CIRCUIT DIAGRAM:

THEORY:
Zener diode is a P-N junction diode specially designed to operate in the reverse
biased mode. It is acting as normal diode while forward biasing. It has a particular
voltage known as break down voltage, at which the diode break downs while
reverse biased. In the case of normal diodes the diode damages at the break
down voltage. But Zener diode is specially designed to operate in the reverse
breakdown region.

Dept of ECE- GCEM Page 20

 Analog Electronics Laboratory Manual - 10ESL37

The basic principle of Zener diode is the Zener breakdown. When a diode is
heavily doped, it‟s depletion region will be narrow. When a high reverse voltage is
applied across the junction, there will be very strong electric field at the junction.
And the electron hole pair generation takes place. Thus heavy current flows. This
is known as Zener break down.
So a Zener diode, in a forward biased condition acts as a normal diode. In reverse
biased mode, after the break down of junction current through diode increases
sharply. But the voltage across it remains constant. This principle is used in
voltage regulator using Zener diodes The figure shows the zener voltage
regulator, it consists of a current limiting resistor RS connected in series with the
input voltage Vs and zener diode is connected in parallel with the load RL in
reverse biased condition. The output voltage is always selected with a breakdown
voltage Vz of the diode.

The input source current, IS = IZ + IL………….. (1)

The drop across the series resistance, Rs = Vin – Vz …….. (2)
And current flowing through it, Is = (Vin – VZ) / RS ………….. (3)
From equation (1) and (2), we get, (Vin - Vz )/Rs = Iz +IL ………… (4)

Regulation with a varying input voltage (line regulation): It is defined as

the change in regulated voltage with respect to variation in line voltage. It is
denoted by „LR‟. In this, input voltage varies but load resistance remains constant
hence, the load current remains constant. As the input voltage increases, form
equation (3) Is also varies accordingly. Therefore, zener current Iz will increase.
The extra voltage is dropped across the Rs. Since, increased Iz will still have a
constant Vz and Vz is equal to Vout.
The output voltage will remain constant. If there is decrease in Vin, Iz decreases
as load current remains constant and voltage drop across Rs is reduced. But even
though Iz may change, Vz remains constant hence, output voltage remains
constant.

Regulation with the varying load (load regulation): It is defined as change in

load voltage with respect to variations in load current. To calculate this regulation,
input voltage is constant and output voltage varies due to change in the load
resistance value. Consider output voltage is increased due to increasing in the
load current. The left side of the equation (4) is constant as input voltage Vin, IS
and Rs is constant. Then as load current changes, the zener current Iz will also
change but in opposite way such that the sum of Iz and IL will remain constant.
Thus, the load current increases, the zener current decreases and sum remain
constant. Form reverse bias characteristics even Iz changes, Vz remains same
hence, and output voltage remains fairly constant.

PROCEDURE:-
A) Line Regulation:
1. Make the connections as shown in figure below.
2. Keep load resistance fixed value; vary DC input voltage from 5V to 15V.
3. Note down output voltage as a load voltage with high line voltage „VHL‟ and as
a load
Voltage with low line voltage „VLL‟.
4. Using formula, % Line Regulation = (VHL-VLL)/ VNOM x100, where VNOM =
the nominal
load voltage under the typical operating conditions. For ex. VNOM = 9.5 ± 4.5 V
Dept of ECE- GCEM Page 21
 Analog Electronics Laboratory Manual - 10ESL37

B) Load Regulation:
1. For finding load regulation, make connections as shown in figure below.
2. Keep input voltage constant say 10V, vary load resistance value.
3. Note down no load voltage „VNL‟ for maximum load resistance value and full
load
voltage „VFL‟ for minimum load resistance value.
4. Calculate load regulation using, % load regulation = (VNL-VFL)/ VFL x100.

Calculations:
% Line Regulation = (VHL-VLL) / VNOM x100 = ------------ %
% voltage regulation = (VNL-VFL)/VFLx100 =----------%

RESULT:

Dept of ECE- GCEM Page 22

 Analog Electronics Laboratory Manual - 10ESL37

Experiment No : 4 DATE :
BJT AMPLIFIER
AIM:
Design and set up the BJT common emitter amplifier using voltage divider bias
with and without feedback and determine the gain bandwidth product from its
frequency response.

APPARATUS REQUIRED:

Sl.No APPARATUS RANGE QUANTITY

1 AFO (0-1)MHz 1
2 CRO (0-20)MHz 1
3 Resistors 1.5KΩ,6KΏ,2KΩ, Each one
14kΩ,2.3KΩ,10KΩ
4 Power supply (0-30V) 1
5 Transistors BC 107 1
6 Capacitors 28pF, 10pF,720pF 1

THEORY:
Negative feedback in general increases the bandwidth of the transfer function
stabilized by the specific type of feedback used in a circuit. In Voltage shunt
feedback amplifier, consider a common emitter stage with a resistance R‟
connected from collector to base. This is a case of voltage shunt feedback and we
expect the bandwidth of the Trans resistance to be improved due to the feedback
through R‟. The voltage source is represented by its Norton‟s equivalent current
source Is=Vs/Rs.

Design :
Given specifications:
VCC= 10V, IC=1.2mA, AV= 30, fI = 1 kHz, S=2, hFE= 150, β=0.4
The feedback factor, β= - 1/RF= +1/0.4=2.5KΏ
(i) To calculate RC:
The voltage gain is given by,
AV= -hfe (RC|| RF) / hie
h ie = β re
re = 26mV / IE = 26mV / 1.2mA = 21.6
hie = 150 x 21.6 =3.2K
Apply KVL to output loop,
VCC= IC RC + VCE+ IE RE ----- (1)
Where VE = IE RE (IC= IE)
VE= VCC / 10= 1V
Therefore RE= 1/1.2x10-3=0.8K= 1KΏ
VCE= VCC/2= 5V
From equation (1), RC= 3 KΏ
(ii) To calculate R1&R2:
S=1+ (RB/RE)
RB= (S-1) RE= R1 || R2 =1KΏ
RB= R 1R2 / R1+ R2------- (2)
VB= VBE + VE = 0.7+ 1= 1.7V
VB= VCC R2 / R1+ R2 ------- (3)
Solving equation (2) & (3),
R1= 5 KΏ & R2= 1.1KΏ
Dept of ECE- GCEM Page 23
 Analog Electronics Laboratory Manual - 10ESL37

CIRCUIT DIAGRAM

WITHOUT FEEDBACK:

WITH FEEDBACK:

Dept of ECE- GCEM Page 24

 Analog Electronics Laboratory Manual - 10ESL37

PROCEDURE:
1. Connect the circuit as per the circuit diagram.
2. Set VCC = 10V; set input voltage using audio frequency oscillator.
3. By varying audio frequency oscillator take down output frequency oscillator
voltage for difference in frequency.
4. Calculate the gain in dB
5. Plot gain Vs frequency curve in semi-log sheet.
6. Connect the circuit as per the circuit diagram.
7. Set VCC = 10V; set input voltage using audio frequency oscillator.
8. By varying audio frequency oscillator take down output frequency oscillator
voltage for difference in frequency.
9. Calculate the gain in dB
10. Plot gain Vs frequency curve in semi-log sheet.
11. Compare this response with respect to the amplifier without feedback.

TABULATION:
(With or without feedback)

FREQUENCY OUTPUT Vin(V) Gain = 20log(Vo/Vin) dB

VO(V)

(iii) To calculate Resistance:

Output resistance is given by,
RO= RC || RF
RO= 1.3KΏ
input impedance is given by,
Ri = (RB|| RF) || hie = 0.6KΏ
Trans-resistance is given by,
Rm= -hfe (RB|| RF)( RC || RF) / (RB|| RF)+ hie
Rm= 0.06KΏ.

AC parameter with feedback network:

(i) Input Impedance:
Rif = Ri /D (where D= 1+β Rm)
Therefore D = 25
Rif= 24
Input coupling capacitor is given by,
Xci= Rif / 10= 2.4 (since XCi << Rif)
Ci = 1/ 2пfXCi =66μf
(ii) Output impedance:
ROf= RO/ D = 52
Output coupling capacitor:
XCO= Rof /10= 5.2
CO = 1/ 2пfXCO= 30μf

Dept of ECE- GCEM Page 25

 Analog Electronics Laboratory Manual - 10ESL37

(iii) Emitter capacitor:

XCE << R‟E = R‟/10
R‟E= RE|| {( hie +RB) / (1+hfe)}
XCE= 2.7
Therefore CE= 58μf.

Model Graph:

RESULT:

Dept of ECE- GCEM Page 26

 Analog Electronics Laboratory Manual - 10ESL37

Experiment No : 5 DATE :
BJT DARLINGTON EMITTER FOLLOWER
AIM:
To design and test a Darlington emitter follower circuit with and without
boot strapping and determine the gain, input and output impedance.
COMPONENTS REQUIRED:

Sl. No. Components Specification Qty

Details
1. Transistor SL100 2 Nos.
10 f 1 No
2. Capacitors
0.47µf 2 Nos.
3. Resistors 1 M, 2.2 M, 1.5 K, 10 K, 47K Each 1 No
DC Supply, CRO with Probe, Signal generator,
AC millivoltmeter

THEORY:
Normally transistors are used as amplifiers. But there are some applications
in which, matching of impedance is required between two circuits without any gain
or attenuation. In such applications emitter followers are used. Emitter followers
have large input impedance and small output impedance. Darlington emitter
follower has two transistors connected in cascade such that the emitter of first
transistor is connected to the base of second transistor. The voltage gain of the
darlington emitter follower is close to unity. The major drawback of this circuit is
that the second transistor amplifies leakage current of the first transistor and
overall leakage current becomes high. The output is observed at the emitter
terminal of the second transistor. Hence it is called an emitter follower.

Dept of ECE- GCEM Page 27

 Analog Electronics Laboratory Manual - 10ESL37

CIRCUIT DIAGRAM:
Darlington emitter follower without bootstrapping
Vcc = 12V

R1 1M

Cb = 0.47µf
Q1
QSL100

SL100
R2 2.2 M
Vin

CE = 0.47µf
RE
Vo
1.5 K

Darlington emitter follower with bootstrapping

DESIGN:
Given IC = 4mA, VCC = 12V, VBE = 0.6V, 1 = 2 = 100
To find RE:
Applying KVL to the output loop of the second transistor, we get
VCC = VCE + VRE
Therefore VRE = VCC – VCE = 12 – 6
Therefore VRE = 6V
W.K.T RE = VRE / IE2
Here IE2 = IC2
Therefore RE = 6 / 4 x 10-3
RE = 1.5k

Dept of ECE- GCEM Page 28

 Analog Electronics Laboratory Manual - 10ESL37

To find R1 & R2:

From the circuit we have
VA = VBE1 + VBE2 + VRE
= 0.6 + 0.6 + 6 = 7.2V
W.K.T. IC = IB
Therefore IB = (4 x 10-3)/ 100 = 40 A
Let 10IB be the current through R1 and 9IB be the current through R2.
From the fig. we see that
R1 = (VCC – VA) / 10IB
Therefore R1 = 12K
From the fig. R2 = VA / 9IB
Therefore R2 = 20 K  22K
W.K.T. CC = 10 / XRE = 10 / ( 2..f.RE)
Assume f = 50Hz
Therefore CC = 21.2F  47 F
W.K.T. Cb = 10 / XRB = 10 / ( 2..f.RB ) where RB = R1 || R2 = 7.5k
Therefore Cb = 4.2F  4.7F
Chose R3 = 10 K, CB = 10µf for bootstrapping
PROCEDURE:

1. Rig up the circuit as shown in the fig.

2. Check the circuit for biasing, i.e. check VCE, VCC and VRE.
3. Give a sinusoidal input signal of 1KHz from a signal generator.
4. Set the input signal to a value such that the output doesn‟t get clipped.
5. For different frequencies of the input signal, read the output on the
voltmeter and verify that the gain is 1.
6. To measure input impedance, connect a resistor of 47k in series with
the signal generator.
7. Measure the voltage at the input point (VS) and at the point after the
resistor (VIN).
8. Current through the resistor is given by the expression I
= (VS - VIN) / 47K.
9. Input impedance is given by ZIN = VIN / 47 K
10.To measure output impedance, connect a DRB in parallel with the
output.
11.Adjust all the knobs of the DRB to maximum.
12.Start reducing the resistance in the DRB from a large value until the
output reduces to half.
13.The resistance in the DRB is the output impedance.

Dept of ECE- GCEM Page 29

 Analog Electronics Laboratory Manual - 10ESL37

TABULAR COLUMN:
VIN = __________ constant

Frequency
V0 (V) AV AV (dB)
(Hz)

WAVEFORM:
Vin

Vin 0 t

V0

0 t
Vin

RESULT :

Dept of ECE- GCEM Page 30

 Analog Electronics Laboratory Manual - 10ESL37

Experiment No : 6 DATE :
HARTLEY OSCILLATOR / COLPITT’S OSCILLATOR
AIM:
Design and set-up the following tuned oscillator circuits using BJT, and determine
the frequency of oscillation.

COMPONENTS REQUIRED:

Sl. No. Components Specification Qty

Details
1. Transistor SL100 1 No
0.1 f, 1000 pf 2 No
2. Capacitors
47µf, 0.0023 µf Each 1 No
3. Resistors 22K, 4.7K, 1.2K, 330
Each 1 No
1 K Pot
4. Inductors 100 µH, 1mH, 5mH Each 1 No
DC Supply, CRO with Probe

THEORY:
Oscillators are devices, which generate oscillations. The frequency of
oscillations depends on the feedback network. Feedback may be of two types
namely positive and negative. In positive feedback, the feedback signal is applied
in phase with the input signal thus increasing it. In negative feedback, the
feedback signal is applied out of phase with the input thus reducing it. The
feedback used in oscillators is positive feedback. The oscillators work on the
principle of Barkhausen criteria. This states that for sustained oscillations
i) Loop gain Av must be equal to 1.
ii) The phase shift around the loop must be 0 deg of 360 deg.
Here Av is the gain of the amplifier and  is the attenuation of the feedback
network. Consider the feedback network shown in the fig (1) below. Assume an
amplifier with input signal Vin. The output signal VO will be 180 deg out of phase
with Vin. So to get an in phase output, the feedback network provides 180-deg
phase shift. Therefore the output Vf from the feedback network can be made in
phase and equal in amplitude to Vin and Vin can be removed. Even then the
oscillations continue. Practical oscillations do not need any input signal to start
oscillations. They are self-starting due to thermally produced noise in resistors and
other components. Only one frequency (fo) of noise satisfies, Barkhausen

Dept of ECE- GCEM Page 31

 Analog Electronics Laboratory Manual - 10ESL37

criteria and the circuit oscillates with that frequency. The magnitude of fo keeps
on increasing each time it goes around the loop. The amplification of fo is limited
by circuit‟s own non-linearities. Therefore to start oscillations Av > 1 and to
sustain it, the loop gain Av = 1.

Fig 1.
Amplifier

Vin Vo
Av

B
Vf

The feedback network used here consists of L and C. Consider the circuit
shown below fig 2. This circuit consists of L and C in parallel. The capacitor stores
energy in its electric field whenever there is voltage across it and the inductor
stores energy in its magnetic field whenever there is current through it. Initially
let us assume that the capacitor has charged to V volts. When S is closed c= 0.
When S is closed at t = t0 , capacitor starts charging through the inductor. Thus a
voltage gets built up across the inductor due to the change in current through it. If
the capacitor was changed with the polarity as shown in the fig 2 the current
starts flowing from the positive plate of the capacitor to the negativ4 plate of the
capacitor. As shown the voltage across the capacitor reduces during the discharge
time v reduces and I increases. At time t1 v will be 0 and I will be maximum as c
is fully discharged, the capacitor charges like sinusoidal oscillations. Thus the
circuit oscillates with the frequency
fo = 1/ 2LC
S t = to

Fig.2 +
v L C
-
i

The Hartley oscillator consists of two inductors and a capacitor and Colpitts
oscillator consists of two capacitors and an inductor.

Dept of ECE- GCEM Page 32

 Analog Electronics Laboratory Manual - 10ESL37

The resonant frequency fo for Hartley oscillator is

fo =1/ 2 LeqC ------where Leq = L1 + L2.

The resonant frequency fo for Colpitts oscillator is

fo = 1/ 2LCeq ------where Ceq = C1C2/(C1 + C2)

CIRCUIT DIAGRAM:

HARTLEY OSCILLATOR:

Vcc = 9 v

R1 Rc
1.8 K Cc VO
18K

CB 0.1 f
BC109

0.1 f

Variable
1 K Pot

3.9K
470 
R2 CE
RE

47 f

L1 = 100 µH L2 = 1mH
GND

C = 0.0023 µf

Dept of ECE- GCEM Page 33

 Analog Electronics Laboratory Manual - 10ESL37

COLPITTS OSCILLATOR:

Vcc = 9 v

R1 Rc
1.8 K Cc VO
18K
CB 0.1 f
BC109
0.1 f

Variable
1 K Pot

3.9K
470 
R2 CE
RE

47 f

C1 = 1000pf C2 = 1000pf
GND

L = 5mH

DESIGN:
Given VCC = 9V, IC = 2mA,  = 50

RE: W.K.T. VRE = VCC / 10 = 9 / 10 = 0.9V ------for biasing

IE  IC = 2 mA
From the fig. We see that,
IERE = VRE
RE = 0.9 / (2 x 10-3 ) = 450
Therefore RE  470

RC: VCE = VCC / 2 = 4.5V ----- for Q point to be in active region.

Applying KVL to output loop
VCC –ICRC-VCE -VRE = 0
9 – 2 x 10-3 RC – 4.5 -0.9 = 0
Dept of ECE- GCEM Page 34
 Analog Electronics Laboratory Manual - 10ESL37

Therefore RC = 1.8k
R1 & R2: From biasing circuit
VB = VBE+ VRE
= 0.7 + 0.9
VB = 1.6V
Assume 10 IB flows through R1 and 9 IB flows through R2.
W.K.T. IC = IB
2 x 10-3 = 50 IB
Therefore IB = 40 A
From the fig. we see that,
R1 = VCC – VB / 10 IB = 9 – 1.6 / (10 x 40 x 10-6 ) = 18.5k
Therefore R1  18k
R2 = VB / 9IB = 1.6 / ( 9 x 40 x 10-6 ) = 4.44k
Therefore R2  3.9k
CE, CC, CB : Let CB = CC = 0.1F
XCE = RE/10
Therefore f = 10 / (2 CE RE)
Let f = 100Hz and W.K.T RE = 470
Therefore CE = 10 / 2 f.RE = 34F
Therefore CE  47F.

HARTLEY OSCILLATOR:

Attenuation  = Vf/Vo = IXL1/IX L2 = XL1 / X L2 = 2 foL1/2foL2 = L1/L2

For sustained oscillations Av = 1 -------- Av = 1/ = L2/L1

For oscillations to start Av > 1 -----------Av > L2/L1

COLPITTS OSCILLATOR:

Attenuation  = Vf / Vo = IXC1/IXC2 = XC1/ XC2 = (1/ 2foC1)/(1/2foC2) =

C1/C2

For sustained oscillations Av = 1 ---------- Av = C1/C2

For oscillations to start Av > 1----------Av > C1/C2

Dept of ECE- GCEM Page 35

 Analog Electronics Laboratory Manual - 10ESL37

DESIGN OF TANK CIRCUIT

Assume = fo = 100 KHz

HARTLEY OSCILLATOR

fo = 1/ (2 LeqC) ------where Leq = L1 + L2.

Assume L1 = 100 µH, L2 =1mH

 LEQ =
 fO =1/ (2 2*10-3 C)
 C = 0.0023 µf (Decade capacitance box)

COLPITTS OSCILLATOR

fO = 1/ (2LCeq ) ------where Ceq = (C1C2)/(C1 + C2)

Assume C1 = C2 = 1000 pF

 Ceq =

 fO = 1/ 2L * .05*10 - 6

 L = 5 mH (Use decade inductance box)

PROCEDURE:

1. Rig up the circuit as shown in the circuit diagram.

2. Before connecting the feedback network, check the circuit for biasing
conditions i.e. check VCE, and VRE.
3. After connecting the feedback network. Check the output.
4. Check for the sinusoidal waveform at output. Note down the frequency of
the output waveform and check for any deviation from the designed value
of the frequency.
5. To get a sinusoidal waveform adjust 1K potentiometer.
6. DCB/DIB can be varied to vary the frequency of the output waveform.

TABULAR COLUMN

HARTLEY OSCILLATOR COLPITTS OSCILLATOR

SL NO C fo SL NO L fo

WAVEFORM:

Dept of ECE- GCEM Page 36

 Analog Electronics Laboratory Manual - 10ESL37

Vo

 frequency fo = 1/T

RESULT:

Dept of ECE- GCEM Page 37

 Analog Electronics Laboratory Manual - 10ESL37

Experiment No : 7 DATE :
CRYSTAL OSCILLATOR
AIM:
To design a crystal oscillator to oscillate at the specified crystal frequency.
COMPONENTS REQUIRED:

Sl. No. Components Details Specification Qty

1. Transistor SL100 1 No
0.1 f 2 No
2. Capacitors
47µf 1 No
3. Resistors 22K, 4.7K, 1.2K, 330
Each 1 No
1 K Pot
4. Crystal 2 MHz or 1.8 MHz 1 No
DC Supply, CRO with Probe

CIRCUIT DIAGRAM:

Vcc = 9 v

R1 Rc
1.8 K Cc VO
18K
CB 0.1 f
BC109

0.1 f

Variable
1 K Pot

3.9K
470 
R2 CE
RE

47 f

2 MHz

1.8 MHz

Dept of ECE- GCEM Page 38

 Analog Electronics Laboratory Manual - 10ESL37

DESIGN:
Given VCC = 9V, IC = 2mA,  = 50

RE: W.K.T. VRE = VCC / 10 = 9 / 10 = 0.9V ------for biasing

IE  IC = 2 mA
From the fig. We see that,
IERE = VRE
RE = 0.9 / (2 x 10-3 ) = 450
Therefore RE  470

RC: VCE = VCC / 2 = 4.5V ----- for Q point to be in active region.

Applying KVL to output loop
VCC –ICRC-VCE -VRE = 0
9 – 2 x 10-3 RC – 4.5 -0.9 = 0
Therefore RC = 1.8k
R1 & R2: From biasing circuit
VB = VBE+ VRE
= 0.7 + 0.9
VB = 1.6V
Assume 10 IB flows through R1 and 9 IB flows through R2.
W.K.T. IC = IB
2 x 10-3 = 50 IB
Therefore IB = 40 A
From the fig. we see that,
R1 = VCC – VB / 10 IB = 9 – 1.6 / (10 x 40 x 10-6 ) = 18.5k
Therefore R1  18k
R2 = VB / 9IB = 1.6 / ( 9 x 40 x 10-6 ) = 4.44k
Therefore R2  3.9k
CE, CC, CB : Let CB = CC = 0.1F
XCE = RE/10
Therefore f = 10 / (2 CE RE)
Let f = 100Hz and W.K.T RE = 470
Therefore CE = 10 / 2 f.RE = 34F
Therefore CE  47F.

Dept of ECE- GCEM Page 39

 Analog Electronics Laboratory Manual - 10ESL37

PROCEDURE:
1. Rig up the circuit as shown in the circuit diagram.
2. Before connecting the feedback network, check the circuit for biasing
conditions i.e. check VCE, and VRE.
3. After connecting the feedback network. Check the output.
4. Check for the sinusoidal waveform at output. Note down the frequency of
the output waveform and check for any deviation from the designed value
of the frequency.
5. To get a sinusoidal waveform adjust 1K potentiometer.

WAVEFORM:

Vo

 frequency fo = 1/T

RESULT:

Dept of ECE- GCEM Page 40

 Analog Electronics Laboratory Manual - 10ESL37

Experiment No : 8 DATE :
COMPLEMENTRY SYMMETRY CLASS-B PUSH PULL POWER
AMPLIFIER
Aim:
Set-up and study the working of complementary symmetry class B push pull
power amplifier and calculate the efficiency.

COMPONENTS REQUIRED:

Sl. No. Components Specification Qty

Details
SL100 1 No.
1. Transistor
SK100 1 No.
2. Diode BY127 2 Nos.
47 f 2 Nos.
3. Capacitors
470 µf 1 No.
220 2 No
4. Resistors
DRB 1 No
DC Supply, CRO with Probe, Signal generator,
AC millivoltmeter

Theory: In class B operation, to obtain output for the full cycle of signal, it is
necessary to use two transistors and have each conduct on opposite half cycle,
the combined operation providing a full cycle of output signal. Since one part of
the circuit pushes the signal high during one half cycle and the other part pulls the
signal low during the other half cycle, the circuit is referred to as a push pull
circuit.

Circuit diagram:

Dept of ECE- GCEM Page 41

 Analog Electronics Laboratory Manual - 10ESL37

DESIGN: Po (watts)

Given Vcc =2.5V; RL= 10 Ω; IDC = 3mA

To Find R1 & R2:

Applying KVL at the input circuit;
We get ; Vcc = 2VR1 + 1.4
Therefore; VR1 = 0.55V;
VR1 =IDCR1 = 0.55V; R1 = 183Ω.
Choose; R1 = R2 = 220Ω.

To Find Ci : Resistance RL(Ω)

Input coupling capacitor is given by, Xci >Zieff/10 >1.1K/10
Xci > 1/2πfCi ;Ci >28μF; Choose Ci = 47μF

To Find CO:
Output coupling capacitor is given by, Xco = 10
Xco > 1/2πfCo
Co > 318μF; Choose; Co = 470μF
Poac=Vo2/8RL Pidc=VccIdc
Calculate circuit efficiency, η = Po (ac)/Pi(dc) = (π/4)Vo/Vcc = ?

Procedure:
1. Connect the circuit as per the circuit diagram.
2. Set VI = 3V, using the signal generator.
3. Keeping the input voltage constant, vary the load resistor and note down
the readings of the ammeter and peak to peak output voltage.
4. Calculate PDC, PAC and % efficiency η.
5. Draw the plot of resistance versus output power.

Tabulation
Vi = ----------------
RL () VO (v) IDC(mA) PAC PDC %

RESULT:

Dept of ECE- GCEM Page 42

 Analog Electronics Laboratory Manual - 10ESL37

Experiment No : 9 DATE :
JFET CHARACTERISTICS

AIM : Plot the transfer and drain characteristics of a JFET and calculate its drain
resistance, mutual conductance and amplification factor.

EQUIPMENT REQUIRED :
1 Regulated Power Supply 0-30V
2 Voltmeter 0-20V
3 Ammeter 0-50mA
4 Bread Board
5 JFET.

SPECIFICATIONS:

For JFET BFW11: -

Gate Source Voltage VGS = - 30V
Forward Gain Current IGF = 10 mA
Maximum Power Dissipation PD = 300 mW.

THEORY:
A FET is a three terminal device, having the characteristics of high input
impedance and less noise, the gate to source junction of the FET always reverse
biased. In response to small applied voltage from drain to source, the n-type bar
acts as sample resistor, and the drain current increases linearly with vds.with
increase in Id the ohmic voltage drop between the and the channel region reverse
biases the junction and the conducting position of the channel begins to remain
Dept of ECE- GCEM Page 43
 Analog Electronics Laboratory Manual - 10ESL37

constant. The Vds at this instant is called “pinch of voltage”. If the gate to source
voltage (Vgs)is applied in the direction to provide additional reverse bias, the
pinch off voltage is decreased.
In amplifier applications, the FET is always used in the region beyond the pinch
off.
Fds = Idss (1-Vgs/ Vp)^2.
PROCEDURE:
DRAIN CHARACTERISTICS
1. Make the connections as per circuit diagram.
2. Keep VGS = 0V by varying VGG.
3. Varying VDD gradually, note down both drain current ID and drain to source
voltage (VDS).
4. Step Size is not fixed because of non linear curve and vary the X-axis variable
(i.e. if
5. Output variation is more, decrease input step size and vice versa).
6. Repeat above procedure (step 3) for VGS = -1V.

TRANSFER CHARACTERISTICS:
1. Keep VDS = 2V by varying VDD.
2. Varying VGG gradually from 0 – 5V, note down both drain current (ID) and
gate to source
3. Voltage (VGS).
4. Step Size is not fixed because of non linear curve and vary the X-axis variable
(i.e. if
5. Output variation is more, decrease input step size and vice versa).
6. Repeat above procedure (step 2) for VDS = 4V.

OBSERVATIONS:
DRAIN CHARACTERISTICS:
VGS(V)=0 VGS(V)= -1
VDS(V) ID (mA) VDS(V) ID(mA)

Dept of ECE- GCEM Page 44

 Analog Electronics Laboratory Manual - 10ESL37

TRANSFER CHARACTERISTICS:
VDS(V)= 1 VDS(V)= 3
VGS(V) ID (mA) VGS(V) ID(mA)

MODEL GRAPH:

Transfer Characteristics Drain Characteristics

Dept of ECE- GCEM Page 45

 Analog Electronics Laboratory Manual - 10ESL37

CALCULATIONS:
1. Drain resistance rd =ΔVDS/ΔID=
2. Trans conductance gm = ΔID/ ΔVGS=
3. Amplification factor μ= rd ×gm=

RESULT:
1. Drain Resistance (rd) =
2. Trans conductance (gm) =
3. Amplification factor (μ) =

Dept of ECE- GCEM Page 46

 Analog Electronics Laboratory Manual - 10ESL37

Experiment No : 10 DATE :
JFET COMMON SOURCE CHARACTERISTICS
AIM:
Design, setup and plot the frequency response of Common Source JFET/MOSFET
amplifier and obtain the bandwidth.

EQUIPMENT REQUIRED:

1 Regulated Power Supply 0-30V

2 Voltmeter 0-20V
3 Ammeter 0-50mA
4 Bread Board
5 JFET.

THEORY:

The Common Source Amplifier is one of the three basic FET transistor amplifier
configurations. In comparison to the BJT common-emitter amplifier, the FET
amplifier has much higher input impedance, but a lower voltage gain. The Junction
Field Effect Transistor (JFET) offers very high input impedance along with very low
noise figures. It is very suitable for extremely low-level audio applications as in
audio preamplifiers. The JFET is more expensive than conventional bipolar
transistors but offers superior overall performance. Unlike bipolar transistors,
current can flow through the drain and source in any direction equally. Often the
drain and source can be reversed in a circuit with almost no effect on circuit
operation.
The bias levels in amplifiers based on BJTs are often stabilized using the emitter
degeneration technique; that is, a resistor is placed between the transistor‟s
emitter and ground. The resistor creates negative feedback, which forces the
quiescent collector current to remain at its design value regardless of changes in
the transistor‟s parameters (such as βF). A similar technique can be used to
stabilize the biasing of FET amplifiers.
A common-source JFET amplifier in which a resistor RS has been added between
the source and ground. In this circuit the gate has been connected to ground
through the resistor RG; thus, the gate is held at ground potential (0 V). If the
drain current ID begins to rise above its intended quiescent value, the voltage
drop across RS will increase. Since the gate-source voltage VGS is the difference
between the gate potential (fixed at 0 V) and the voltage across RS, a rise in the
voltage across RS will cause VGS to drop, lowering ID back to its original value.
The opposite chain of events occurs if ID begins to drop below its design value. It
is a common practice in the design of circuits based on JFETs to tie the gate to
ground potential via a large-valued resistor (typically around 1MΩ)

Dept of ECE- GCEM Page 47

 Analog Electronics Laboratory Manual - 10ESL37

PROCEDURE:

1. Make the connections as per circuit diagram.

2. Keep VGS = 0V by varying VGG.
3. Varying VDD gradually, note down both drain current ID and drain to source
voltage (VDS).
4. Step Size is not fixed because of non linear curve and vary the X-axis variable
(i.e. if
5. Output variation is more, decrease input step size and vice versa).
6. Repeat above procedure (step 3) for VGS = -1V.

CIRCUIT DIAGRAM:

TABULAR COLUMN:
Input Input Output Gain (db)
Sl No Voltage (Vi) Frequency Voltage (V0)
(fi)

Dept of ECE- GCEM Page 48

 Analog Electronics Laboratory Manual - 10ESL37

GAIN VS FREQUENCY CURVE:

RESULT:

FH =
FL =
Gain (db) =

VIVA – QUESTIONS

1. What are Semiconductors? Give examples?

2. What are the types of Semiconductor?
Dept of ECE- GCEM Page 49
 Analog Electronics Laboratory Manual - 10ESL37

3. What is Intrinsic Semiconductor?

4. What is Extrinsic Semiconductor?
5. What are the types of Extrinsic Semiconductor?
6. What is P-type Semiconductor?
7. What are break down diodes or zener diodes
8. What is break down? What are its types?
9. What is zener breakdown4.What is avalanche break down?
10. What are the PIVs of three different filters
11. What are the advantages of bridge rectifier over center-taped full wave rectifier?

12. Define transformer utilization factor? What is the TUF for HWR and full wave center taped
and bridge rectifier?
13. Why the CE configuration is commonly used for the amplifier circuits?
14. Why the Ib vs Vbe plots move outwards for higher values of Vce in Ce input
characteristics?
15. What are the different types of clipping circuits?
16. Explain the different types of clipping circuits.

APPENDIX

Pin Identification of Transistors

1. Bipolar Junction Transistor (BJT)Transistors

Transistors may be NPN or PNP which are available in

Plastic casing or Metal Can package. In plastic casing,

Dept of ECE- GCEM Page 50

 Analog Electronics Laboratory Manual - 10ESL37

one side of the transistor is Flat which is the front side and the pins are arranged serially.
To identify the pins, keep the front flat side facing you and count the pins as one, two etc.
In most NPN transistors it will be 1 (Collector), 2 (Base) and 3 (Emitter). Thus CBE. But in
PNP transistors, the condition will be just reversed. That is EBC.

In Metal can types, the pins are arranged circularly. Just see a Tab in the rim. In NPN
type, the pin close to the Tab is Emitter, the opposite one ,the Collector and the middle
one, base. In PNP type the pins are reversed. Pin close to the Tab is Collector.

Dept of ECE- GCEM Page 51

 Analog Electronics Laboratory Manual - 10ESL37

But this is not a standard pin configuration. The pin arrangement may vary in some
transistors. So to get an idea, the following table will help you

2. Field Effect Transistor (FET)

To identify a Field Effect Transistor, one should keep the curved portion facing him/her
and start counting in anti clockwise direction. The 1st one is the source, then the gate and
then the drain.

3. MOSFET – Metal Oxide Semiconductor Field Effect Transistor

Usually in some cases the pins of MOSFET are accordingly labeled as G, S and D
denoting Gate, Source and Drain. In some cases, it is recommended to consult the
datasheet of the MOSFET. Normally making the flat side faced towards you, the pins are
labeled as S, G, D starting from left to right.

Dept of ECE- GCEM Page 52