MPMC UNIT 4 SIETK

SYLLABUS
UNIT-IV

Programming of 8051- Assembly language Programming, Assembler directives, Instruction set -

Moving Data, Logical operations – Byte level and bit level operations, Rotate and swap operations,
Arithmetic operations, Jump and call Instructions, Interrupts and Returns.

Assembly language Programming

Programming in the sense of Microcontrollers (or any computer) means writing a sequence
of instructions that are executed by the processor in a particular order to perform a
predefined task. Programming also involves debugging and troubleshooting of instructions
and instruction sequence to make sure that the desired task is performed.
Like any language, Programming Languages have certain words, grammar and rules. There
are three types or levels of Programming Languages for 8051 Microcontroller. These levels
are based on how closely the statements in the language resemble the operations or tasks
performed by the Microcontroller.
The three levels of Programming Languages are:
Machine Language
Assembly Language
High-level Language

Machine language
In Machine language or Machine Code, the instructions are written in binary bit patterns i.e.
combination of binary digits 1 and 0, which are stored as HIGH and LOW Voltage Levels. This
is the lowest level of programming languages and is the language that a Microcontroller or
Microprocessor actually understands.

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Assembly Language
The next level of Programming Language is the Assembly Language. Since Machine Language
or Code involves all the instructions in 1’s and 0’s, it is very difficult for humans to program
using it.
Assembly Language is a pseudo-English representation of the Machine Language. The 8051
Microcontroller Assembly Language is a combination of English like words called Mnemonics
and Hexadecimal codes. It is also a low level language and requires extensive understanding
of the architecture of the Microcontroller.
High-level Language
The name High-level language means that you need not worry about the architecture or other
internal details of a microcontroller and they use words and statements that are easily
understood by humans.
Few examples of High-level Languages are BASIC, C Pascal, C++ and Java. A program called
Compiler will convert the Programs written in High-level languages to Machine Code.
Why Assembly Language?
The assembly language is a low-level programming language used to write program code in
terms of mnemonics. Even though there are many high-level languages that are currently in
demand, assembly programming language is popularly used in many applications. It can be
used for direct hardware manipulations. It is also used to write the 8051-programming
code efficiently with less number of clock cycles by consuming less memory compared to the
other high-level languages., the following reasons point out the advantage of Assembly
Language
• The Programs written in Assembly gets executed faster and they occupy less memory.
• With the help of Assembly Language, you can directly exploit all the features of a
Microcontroller.
• Using Assembly Language, you can have direct and accurate control of all the
Microcontroller’s resources like I/O Ports, RAM, SFRs, etc.
• Compared to High-level Languages, Assembly Language has less rules and restrictions

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8051 Programming in Assembly Language

The assembly language is a fully hardware related programming language. The embedded
designers must have sufficient knowledge on hardware of particular processor or controllers
before writing the program. The assembly language is developed by mnemonics; therefore,
users cannot understand it easily to modify the program.

Microcontrollers or processors can understand only binary language in the form of ‘0s or 1s’;
An assembler converts the assembly language to binary language, and then stores it in
the microcontroller memory to perform the specific task.
The assembly language is made up of elements which all are used to write the program
in sequential manner. Follow the given rules to write programming in assembly language.
Rules of Assembly Language
• The assembly code must be written in upper case letters
• The labels must be followed by a colon (label:)
• All symbols and labels must begin with a letter
• All comments are typed in lower case
• The last line of the program must be the END directive
The Structure or Syntax of the 8051 Microcontroller Assembly Language is discussed here.
Each line or statement of the assembly language program of 8051 Microcontroller consists of
three fields: Label, Instruction and Comments.

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The arrangement of these fields or the order in which they appear is shown below.

[Label:] Instructions [//Comments]

NOTE: The brackets for Label and Comments mean that these fields are optional and may not
be used in all statements in a program.

Before seeing about these three fields, let us first see an example of how a typical statement
or line in an 8051 Microcontroller Assembly Language looks like.

TESTLABEL: MOV A, 24H ; THIS IS A SAMPLE COMMENT

In the above statement, the “TESTLABEL” is the name of the Label, “MOV A, 24H” is the
Instruction and the “THIS IS A SAMPLE COMMENT” is a Comment.

Label

The Label is programmer chosen name for a Memory Location or a statement in a program.
The Label part of the statement is optional and if present, the Label must be terminated with
a Colon (:).An important point to remember while selecting a name for the Label is that they
should reduce the need for documentation.

Instruction

The Instruction is the main part of the 8051 Microcontroller Assembly Language Programming
as it is responsible for the task performed by the Microcontroller. Any Instruction in the
Assembly Language consists of two parts: Op-code and Operand(s).

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The first part of the Instruction is the Op-code, which is short for Operation Code, specifies
the operation to be performed by the Microcontroller. Op-codes in Assembly Language are
called as Mnemonics. Op-codes are in binary format (used in Machine Language) while the
Mnemonic (which are equivalent to Op-codes) are English like statements.

The second part of the instruction is called the Operand(s) and it represents the Data on which
the operation is performed. There are two types of Operands: the Source Operand and the
Destination Operand. The Source Operand is the Input of the operation and the Destination
Operand is where the result is stored.

Comments

The last part of the Structure of 8051 Assembly Language is the Comments. Comments are
statements included by the developer for easier understanding of the code and is used for
proper documentation of the Program.

Comments are optional and if used, they must begin with a semicolon (;) or double slash (//)
depending on the Assembler.

The following statements will show a few possible ways of using Label, Instruction and
Comments.

Label without instruction and comment: LABEL:

Line with Label and Instruction: LABEL: MOV A, 22H

Line with Instruction and Comment: MOV A, 22H ; THIS IS A COMMENT

Line with Label and Comment: LABEL: ; THIS IS A COMMENT

Line with only Comment: ; THIS IS A COMMENT

Assembler Directives
Assembly Language Directives are not the instructions to the 8051 Microcontroller Assembler
even though they are written in the Mnemonic field of the program. Assembly Language
Directives are actually instructions to the Assembler and directs the Assembler Program what
to do during the process of Assembling.
The Assembly Language Directives do not have any effect on the contents of the 8051
Microcontroller Memory (except DB and DW directives).These Directives are dependent on
the Assembler Program and in case of ASM51 Assembler, the following are the categories of
Directives.

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The important and frequently used Assembly Language Directives are :

ORG – Set Origin
The 8051 Microcontroller Assembly Language Program will start assembling from the
Program Memory Address 0000H. This is also the address from which the 8051
Microcontroller will start executing the code.
In order place the Program and Data anywhere in the Address Space of the 8051
Microcontroller, you can use the ORG Directive.
Examples
ORG 0000H ; Tells the Assembler to assemble the next statement at 0000H
LJMP MAIN ; Code Memory at 0000H. Jump to MAIN.
ORG 000BH ; Tells the Assembler to assemble the next statement at 000BH
MAIN: NOP ; Code Memory at 000BH. MAIN starts here.
DB – Define Byte
The DB Directive is used to define a Byte type variable. Using this directive, you can define
data in Decimal, Binary, HEX or ASCII formats. There should be a suffix of ‘B’ for binary and ‘H’
for HEX. The ASCII Characters are placed in single quotation marks (like ‘string’).
Examples
ORG 0000H
DB 10 ; Define Byte 10 (Decimal) and store at 0000H
DB 30H ; Define Byte 30 (HEX) and store at 0001H
DB ‘STRING’ ; Define String ‘STRING’ and store at 0002H to 0007H
DB 00001111B ; Define Byte 00001111 (Binary) and store at 0008H

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DB 1234H ; Define Byte 34 (HEX) and store at 0009H. Only lower byte is
accepted as DB can allocate only a Byte of Memory.
DW – Define Word
The Define Word (DW) Directive is used to include a 16-bit data in a program. The
functionality of DW is similar to that of DB except that DW generates 16-bit values.
EQU – Equate
Using the EQU Directive, you can associate a Symbol (or Label) with a Value.
Examples
TMP EQU #30 ; Assigns the value #30 to the name TMP
RED_LED EQU P1.0 ; P1.0 is defined as RED_LED
END
The END Directive is used to stop the assembling process. This should be the last statement
in the program. END Directive cannot have a Label and the statements beyond END will not
be processed by the Assembler.
Example
ORG 0000H
MOV A, 20H
MOV R0, #30
END

Instruction set
Writing a Program for any Microcontroller consists of giving commands to the Microcontroller
in a particular order in which they must be executed in order to perform a specific task. The
commands to the Microcontroller are known as a Microcontroller’s Instruction Set.
Just as our sentences are made of words, a Microcontroller’s (for that matter, any computer)
program is made of Instructions. Instructions written in a program tell the Microcontroller
which operation to carry out.
An Instruction Set is unique to a family of computers. As the 8051 family of Microcontrollers
are 8-bit processors, the 8051 Microcontroller Instruction Set is optimized for 8-bit control
applications. As a typical 8-bit processor, the 8051 Microcontroller instructions have 8-bit
Opcodes. As a result, the 8051 Microcontroller instruction set can have up to 28 = 256
Instructions.

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An 8051 Instruction consists of an Opcode (short of Operation – Code) followed by Operand(s)

of size Zero Byte, One Byte or Two Bytes.The Op-Code part of the instruction contains the
Mnemonic, which specifies the type of operation to be performed. All Mnemonics or the
Opcode part of the instruction are of One Byte size.
Coming to the Operand part of the instruction, it defines the data being processed by the
instructions. The operand can be any of the following:
• No Operand
• Data value
• I/O Port
• Memory Location
• CPU register
There can multiple operands and the format of instruction is as follows:
MNEMONIC DESTINATION OPERAND, SOURCE OPERAND

DATA PROGRAM
ARITHMETIC LOGICAL BOOLEAN
TRANSFER BRANCHING

MOV ADD ANL CLR LJMP

MOVC ADDC ORL SETB AJMP

MOVX SUBB XRL MOV SJMP

PUSH INC CLR JC JZ

POP DEC CPL JNC JNZ

XCH MUL RL JB CJNE

XCHD DIV RLC JNB DJNZ

DA A RR JBC NOP

RRC ANL LCALL

SWAP ORL ACALL

CPL RET

RETI

JMP

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A simple instruction consists of just the opcode. Other instructions may include one or more
operands. Instruction can be one-byte instruction, which contains only opcode, or two-byte
instructions, where the second byte is the operand or three-byte instructions, where the
operand makes up the second and third byte.
Based on the operation they perform, all the instructions in the 8051 Microcontroller
Instruction Set are divided into five groups. They are:
• Data Transfer Instructions
• Arithmetic Instructions
• Logical Instructions
• Boolean or Bit Manipulation Instructions
• Program Branching Instructions
We will now see about these instructions briefly.
Data Transfer Instructions
The Data Transfer Instructions are associated with transfer with data between registers or
external program memory or external data memory. The Mnemonics associated with Data
Transfer are given below.
MOV - The MOV instruction moves data bytes between the two specified operands. The byte
specified by the second operand is copied to the location specified by the first operand. The
source data byte is not affected.
Example MOV A, R6
MOVC - The MOVC instruction moves a byte from the code or program memory to the
accumulator
Example MOVC A, @A+DPTR MOVC A, @A+PC
MOVX - The MOVX instruction transfers data between the accumulator and external data
memory. External memory may be addressed via 16-bits in the DPTR register or via 8-bits in
the R0 or R1 registers. When using 8-bit addressing, Port 2 must contain the high-order byte
of the address.
Example MOVX A, @DPTR
PUSH - The PUSH instruction increments the stack pointer and stores the value of the
specified byte operand at the internal RAM address indirectly referenced by the stack pointer.
No flags are affected by this instruction.
Example PUSH A
POP - The POP instruction reads a byte from the address indirectly referenced by the SP
register. The value read is stored at the specified address and the stack pointer is
decremented. No flags are affected by this instruction.
Example POP 34h

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XCH - The XCH instruction loads the accumulator with the byte value of the specified operand
while simultaneously storing the previous contents of the accumulator in the specified
operand.
Example XCH A, 45h
XCHD - The XCHD instruction exchanges the low-order nibble of the accumulator with the
low-order nibble of the specified internal RAM location. The internal RAM is accessed
indirectly through R0 or R1. The high-order nibbles of each operand are not affected.
Example XCHD A, @R1
Arithmetic Instructions
Using Arithmetic Instructions, you can perform addition, subtraction, multiplication and
division. The arithmetic instructions also include increment by one, decrement by one and a
special instruction called Decimal Adjust Accumulator.
The Mnemonics associated with the Arithmetic Instructions of the 8051 Microcontroller
Instruction Set are:
ADD-The ADD instruction adds a byte value to the accumulator and stores the results back in
the accumulator. Several of the flag registers are affected.
Example ADD A, #03h
ADDC - The ADDC instruction adds a byte value and the value of the carry flag to the
accumulator. The results of the addition are stored back in the accumulator. Several of the
flag registers are affected.
Example ADDC A, #23h (A = A + C + immediate value 23h)
SUBB - The SUBB instruction subtracts the specified byte variable and the carry flag from the
accumulator. The result is stored in the accumulator. This instruction sets the carry flag if a
borrow is required for bit 7 of the result. If no borrow is required, the carry flag is cleared.
Example SUBB A, #01h (A = A - C – immediate value 01h)
INC - The INC instruction increments the specified operand by 1. An original value of 0FFh or 0FFFFh
overflows to 00h or 0000h. No flags are affected by this instruction.

Note - When this instruction is used to modify an output port, the value used as the port
data is read from the output data latch, not the input pins of the port.
Example INC DPTR
DEC - The DEC instruction decrements the specified operand by 1. An original value of 00h
underflows to 0FFh. No flags are affected by this instruction.
Note - When this instruction is used to modify an output port, the value used as the port data
is read from the output data latch, not the pins of the port.
Example DEC A

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MUL - The MUL instruction multiplies the unsigned 8-bit integer in the accumulator and the
unsigned 8-bit integer in the B register producing a 16-bit product. The low-order byte of the
product is returned in the accumulator. The high-order byte of the product is returned in the
B register. The OV flag is set if the product is greater than 255 (0FFh), otherwise it is cleared.
The carry flag is always cleared.
Example MUL AB
DIV - The DIV instuction divides the unsigned 8-bit integer in the accumulator by the unsigned
8-bit integer in register B. After the division, the quotient is stored in the accumulator and the
remainder is stored in the B register. The carry and OV flags are cleared.
If the B register begins with a value of 00h the division operation is undefined, the values of
the accumulator and B register are undefined after the division, and the OV flag will be set
indicating a division-by-zero error.
Example DIV AB
DA - The DA instruction adjusts the eight-bit value in the Accumulator resulting from the
earlier addition of two variables (each in packed-BCD format), producing two four-bit digits.
Any ADD or ADDC instruction may have been used to perform the addition.
If Accumulator bits 3-0 are greater than nine (xxx1010-xxx1111), or if the AC flag is one, six is
added to the Accumulator, producing the proper BCD digit in the low-order nibble. This
internal addition would set the carry flag if a carry-out of the low-order four-bit field
propagated through all high-order bits, but it would not clear the carry flag otherwise.
If the carry flag is now set, or if the four high-order bits now exceed nine (1010xxx-111xxxx),
these high-order bits are incremented by six, producing the proper BCD digit in the high-order
nibble. Again, this would set the carry flag if there was a carry-out of the high-order bits, but
would not clear the carry. The carry flag thus indicates if the sum of the original two BCD
variables is greater than 100, allowing multiple precision decimal addition. OV is not affected.
All of this occurs during the one instruction cycle. Essentially, this instruction performs the
decimal conversion by adding 00H, 06H, 60H, or 66H to the Accumulator, depending on initial
Accumulator and PSW conditions.

Note
▪ DA A cannot simply convert a hexadecimal number in the Accumulator to BCD notation, nor
does it apply to decimal subtraction.
Example DA A

DA

IF (A3-0 > 9) OR (AC = 1)

A = A + 6

IF (A7-4 > 9) OR (C = 1)

A = A + 60h

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The arithmetic instructions has no knowledge about the data format i.e. signed, unsigned,
ASCII, BCD, etc. Also, the operations performed by the arithmetic instructions affect flags like
carry, overflow, zero, etc. in the PSW Register.
Logical Instructions

ANL - The ANL instruction performs a bitwise and byte wise logical AND operation between the
specified byte or bit operands and stores the result in the destination operand.

Example ANL A, #3Fh (byte level)

ANL C, 1 (bit level)

ORL - The ORL instruction performs a bitwise and byte wise logical OR operation on the
specified operands, the result of which is stored in the destination operand.

Example ORL A, #01h (byte level)

ORL C, 0 (bit level)

XRL - The XRL instruction performs a logical exclusive OR operation between the specified
operands. The result is stored in the destination operand.

Example XRL A, #0FFh

CLR - The CLR instruction sets the specified destination operand or bit to a value of 0.
Example CLR A (byte wise)
` CLR C (bit wise)
CPL - The CPL instruction logically complements the value of the specified destination operand
and stores the result back in the destination operand. Bits that previously contained a 1 will be
changed to a 0 and bits that previously contained a 0 will be changed to a 1.

Example CPL 55h (byte wise)

CPL C (bit wise)

RL - The RL instruction rotates the eight bits in the accumulator left one bit position. Bit 7 of the
accumulator is rotated into bit 0, bit 0 into bit 1, bit 1 into bit 2, and so on. No flags are affected by
this instruction.

Example RL A
RLC - The RLC instruction rotates the eight bits in the accumulator and the one bit in the carry
flag left one bit position. Bit 7 of the accumulator is rotated into the carry flag while the original
value of the carry flag is rotated into bit 0 of the accumulator. Bit 0 of the accumulator is rotated
into bit 1, bit 1 into bit 2, and so on. No other flags are affected by this operation.

Example RLC A
RR - The RR instruction rotates the eight bits in the accumulator right one bit position. Bit 0 of the
accumulator is rotated into bit 7, bit 7 into bit 6, and so on. No flags are affected by this instruction.

Example RR A

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RRC - The RRC instruction rotates the eight bits in the accumulator and the one bit in the carry
flag right one bit position. Bit 0 of the accumulator is rotated into the carry flag while the original
value of the carry flag is rotated in to bit 7 of the accumulator. Bit 7 of the accumulator is rotated
into bit 6, bit 6 into bit 5, and so on. No other flags are affected by this instruction.

Example RRC A
SWAP - The SWAP instruction exchanges the low-order and high-order nibbles within the
accumulator. No flags are affected by this instruction.

Example SWAP A
Boolean Instructions
CLR, ANL, ORL , CPL are same operation of above logical operations but it performs operations
on bits.
SETB - The SETB instruction sets the bit operand to a value of 1. This instruction can operate on
the carry flag or any other directly addressable bit. No flags are affected by this instruction.

Example SETB C
MOV - The MOV instruction moves data bits between the two specified operands. The bit
specified by the second operand is copied to the location specified by the first operand. The source
data bit is not affected.
Example MOV C, bit

JC - The JC instruction branches to the specified address if the carry flag is set. Otherwise,
execution continues with the next instruction. No flags are affected by this instruction.
Example JC LABEL

JNC - The JNC instruction transfers program control to the specified address if the carry flag is 0.
Otherwise, execution continues with the next instruction. No flags are affected by this instruction.
Example JNC LABEL
JB - The JB instruction branches to the address specified in the second operand if the value of
the bit specified in the first operand is 1. The bit that is tested is not modified. No flags are affected
by this instruction.
Example JB P1.2 LABEL
JNB - The JNB instruction branches to the specified address if the specified bit operand has a
value of 0. Otherwise, execution continues with the next instruction. No flags are affected by this
instruction.
Example JNB P1.2 LABEL
JBC - The JBC instruction branches to the address specified in the second operand if the value
of the bit specified in the first operand is 1.Otherwise, execution continues with the next instruction.
If the bit specified in the first operand is set, it is cleared. No flags are affected by this instruction.
Example JBC 44h

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Branching Instructions
LJMP - The LJMP instruction transfers program execution to the specified 16-bit address. The
PC is loaded with the high-order and low-order bytes of the address from the second and third
bytes of this instruction respectively. No flags are affected by this instruction.
Example LJMP addr16

AJMP - The AJMP instruction transfers program execution to the specified address. The address
is formed by combining the 5 high-order bits of the address of the following instruction (for A15-
A11), the 3 high-order bits of the opcode (for A10-A8), and the second byte of the instruction (for
A7-A0). The destination address must be located in the same 2KByte block of program memory
as the opcode following the AJMP instruction. No flags are affected.

Example AJMP addr11

SJMP - The SJMP instruction transfers execution to the specified address. The address is
calculated by adding the signed relative offset in the second byte of the instruction to the address
of the following instruction. The range of destination addresses is from 128 before the next
instruction to 127 bytes after the next instruction.
Example SJMP LABEL

JZ - The JZ instruction transfers control to the specified address if the value in the accumulator is
0. Otherwise, the next instruction is executed. Neither the accumulator nor any flags are modified
by this instruction.
Example JZ LABEL

JNZ - The JNZ instruction transfers control to the specified address if the value in the accumulator
is not 0. If the accumulator has a value of 0, the next instruction is executed. Neither the
accumulator nor any flags are modified by this instruction.
Example JNZ LABEL

CJNE - The CJNE instruction compares the first two operands and branches to the specified
destination if their values are not equal. If the values are the same, execution continues with the
next instruction.
Example CJNE R6, #12H, LABEL

DJNZ - The DJNZ instruction decrements the byte indicated by the first operand and, if the
resulting value is not zero, branches to the address specified in the second operand.
Example DJNZ 40h, LABEL

NOP - The NOP instruction does nothing. Execution continues with the next instruction. No
registers or flags are affected by this instruction. NOP is typically used to generate a delay in
execution or to reserve space in code memory.
Example NOP

LCALL - The LCALL instruction calls a subroutine located at the specified address. This
instruction first adds 3 to the PC to generate the address of the next instruction. This result is
pushed onto the stack low-byte first and the stack pointer is incremented by 2. The high-order and
low-order bytes of the PC are loaded from the second and third bytes of the instruction respectively.
Program execution is transferred to the subroutine at this address. No flags are affected by this
instruction.
Example LCALL addr16

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ACALL - The ACALL instruction calls a subroutine located at the specified address. The PC is
incremented twice to obtain the address of the following instruction. The 16-bit PC is then stored
on the stack (low-order byte first) and the stack pointer is incremented twice. No flags are affected.

The address of the subroutine is calculated by combining the 5 high-order bits of the incremented
PC (for A15-A11), the 3 high-order bits of the ACALL instruction opcode (for A10-A8), and the
second byte of the instruction (for A7-A0). The subroutine that is called must be located in the
same 2KByte block of program memory as the opcode following the ACALL instruction.
Example ACALL addr11

RET - The RET instruction pops the high-order and low-order bytes of the PC from the stack (and
decrements the stack pointer by 2). Program execution resumes from the resulting address which
is typically the instruction following an ACALL or LCALL instruction. No flags are affected by this
instruction
Example RET

RETI - The RETI instruction is used to end an interrupt service routine. This instruction pops the
high-order and low-order bytes of the PC (and decrements the stack pointer by 2) and restores the
interrput logic to accept additional interrupts. No other registers are affected by this instruction.

The RETI instruction does not restore the PSW to its value before the interrupt. The interrupt
service routine must save and restore the PSW.

Execution returns to the instruction immediately after the point at which the interrupt was detected.
If another interrupt was pending when the RETI instruction is executed, one instruction at the return
address is executed before the pending interrupt is processed.
Example RETI

JMP - The JMP instruction transfers execution to the address generated by adding the 8-bit value
in the accumulator to the 16-bit value in the DPTR register. Neither the accumulator nor the DPTR
register are altered. No flags are affected by this instruction.
Example JMP @A+DPTR

INTERRUPS & RETURNS

The dictionary meaning of the word ‘interrupt is to break the sequence of operation. While the
CPU is executing a program, an ‘interrupt’ breaks the normal sequence of execution of
instructions, diverts its execution to some other program called ‘Interrupt service routine (ISR)’.
After executing ISR, the control is transferred back again to the main program which was being
executed at the time of interruption.
An interrupt is an external or internal signal to the processor architecture that temporarily
changes the flow of execution of the main program and may execute another program before
continuing with the main program. Many big microprocessor architectures and systems
support several interrupts.
In general, only a few interrupts are supported directly by a processor architecture. If a system
requires a large number of interrupts, an external interrupt controller is incorporated in the
system. Microcontrollers mainly used in small dedicated systems, so in general less number
of interrupts are required.

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In microprocessor systems, the interrupts may be used for implementing the following
applications:
1. Data communication and IO
2. Task switching, Multitasking, Multiprogramming
3. Timing & Real time clock, counting
4. Interfacing peripherals and IO devices
5. Handling of system faults and errors
6. Interlinking of external events with system operation and programming execution.
8051 architecture handles 5 interrupt sources, out of which two are internal (Timer Interrupts),
two are external and one is a serial interrupt. Each of these interrupts has their interrupt vector
address. Highest priority interrupt is the Reset, with vector address 0x0000.

Interrupt Flag Interrupt vector address

Reset - 0000H

INT0 (Ext. int. 0) IE0 0003H

Timer 0 TF0 000BH

INT1 (Ext. int. 1) IE1 0013H

Timer 1 TF1 001BH

Serial TI/RI 0023H

Vector Address: This is the address where controller jumps after the interrupt to serve the
ISR (interrupt service routine).

Reset

Reset is the highest priority interrupt, upon reset 8051 microcontroller start executing
code from 0x0000 address.

Internal interrupt (Timer Interrupt)

8051 has two internal interrupts namely timer0 and timer1. Whenever timer overflows,
timer overflow flags (TF0/TF1) are set. Then the microcontroller jumps to their vector
address to serve the interrupt. For this, global and timer interrupt should be enabled.

Serial interrupt

8051 has serial communication port and have related serial interrupt flags (TI/RI). When
the last bit (stop bit) of a byte is transmitted, TI serial interrupt flag is set and when last
bit (stop bit) of receiving data byte is received, RI flag get set.

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IE register: Interrupt Enable Register

IE register is used to enable/disable interrupt sources.

Bit 7 – EA: Enable All Bit

1 = Enable all interrupts

0 = Disable all interrupts

Bit 6,5 – Reserved bits

Bit 4 – ES: Enable Serial Interrupt Bit

1 = Enable serial interrupt

0 = Disable serial interrupt

Bit 3 – ET1: Enable Timer1 Interrupt Bit

1 = Enable Timer1 interrupt

0 = Disable Timer1 interrupt

Bit 2 – EX1: Enable External1 Interrupt Bit

1 = Enable External1 interrupt

0 = Disable External1 interrupt

Bit 1 – ET0: Enable Timer0 Interrupt Bit

1 = Enable Timer0 interrupt

0 = Disable Timer0 interrupt

Bit 0 – EX0: Enable External0 Interrupt Bit

1 = Enable External0 interrupt

0 = Disable External0 interrupt

Interrupt priority

Each interrupt of 8051 can have two levels of priority: Level 0 and Level 1. Level 1 is
considered a higher priority level compared to Level 0. If the two interrupts are working
at equal priority, the processor takes default priority among those two interrupts and
execute the highest priority interrupt first Priority to the interrupt can be assigned by
using interrupt priority register (IP)

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Interrupt priority after Reset:

Priority Interrupt source Intr. bit / flag

1 External Interrupt 0 INT0

2 Timer Interrupt 0 TF0

3 External Interrupt 1 INT1

4 Timer Interrupt 1 TF1

5 Serial interrupt (TI/RI)

In the table, interrupts priorities upon reset are shown. As per 8051 interrupt priorities,
lowest priority interrupts are not served until microcontroller is finished with higher priority
ones. In a case when two or more interrupts arrives microcontroller queues them according
to priority.
IP Register: Interrupt priority register
8051 has interrupt priority register to assign priority to interrupts.

Bit 7,6,5 – Reserved bits.

Bit 4 – PS: Serial Interrupt Priority Bit
1 = Assign high priority to serial interrupt.
0 = Assign low priority to serial interrupt.
Bit 3 – PT1: Timer1 Interrupt Priority Bit
1 = Assign high priority to Timer1 interrupt.
0 = Assign low priority to Timer1 interrupt.
Bit 2 – PX1: External Interrupt 1 Priority Bit
1 = Assign high priority to External1 interrupt.
0 = Assign low priority to External1 interrupt.
Bit 1 – PT0: Timer0 Interrupt Priority Bit
1 = Assign high priority to Timer0 interrupt.
0 = Assign low priority to Timer0 interrupt.

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Bit 0 – PX0: External0 Interrupt Priority Bit

1 = Assign high priority to External0 interrupt.
0 = Assign low priority to External0 interrupt.
External interrupts in 8051
• 8051 has two external interrupt INT0 and INT1.
• 8051 controller can be interrupted by external Interrupt, by providing level or edge on
external interrupt pins PORT3.2, PORT3.3.
• External peripherals can interrupt the microcontroller through these external
interrupts if global and external interrupts are enabled.
• Then the microcontroller will execute current instruction and jump to the Interrupt
Service Routine (ISR) to serve to interrupt.
• In polling method microcontroller has to continuously check for a pulse by monitoring
pin, whereas, in interrupt method, the microcontroller does not need to poll.
Whenever an interrupt occurs microcontroller serves the interrupt request.
External interrupt has two types of activation level
1. Edge triggered (Interrupt occur on rising/falling edge detection)
2. Level triggered (Interrupt occur on high/low-level detection)
In 8051, two types of activation level are used. These are,
Low level triggered
Whenever a low level is detected on the INT0/INT1 pin while global and external
interrupts are enabled, the controller jumps to interrupt service routine (ISR) to serve
interrupt.
Falling edge triggered
Whenever falling edge is detected on the INT0/INT1 pin while global and ext. interrupts
are enabled, the controller jumps to interrupt service routine (ISR) to serve interrupt.
There are lower four flag bits in TCON register required to select and monitor the external
interrupt type and ISR status.

TCON: Timer/ counter Register

Bit 3- IE1:
External Interrupt 1 edge flag, set by hardware when interrupt on INT1 pin occurred and
cleared by hardware when interrupt get processed.

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Bit 2- IT1:
This bit selects external interrupt event type on INT1 pin,
1= sets interrupt on falling edge
0= sets interrupt on low level
Bit 1- IE0:
Interrupt0 edge flag, set by hardware when interrupt on INT0 pin occurred and cleared
by hardware when an interrupt is processed.
Bit 0 - IT0:
This bit selects external interrupt event type on INT0 pin.
1= sets interrupt on falling edge
0= sets interrupt on low level
Steps in executing an interrupt
Upon activation of an interrupt, the microcontroller goes through the following steps.
1. It finishes the instruction it is executing and saves the address of the next
instruction (PC) on the stack.
2. It also saves the current status of all the interrupts internally (i.e., not on the
stack).
3. It jumps to a fixed location in memory called the interrupt vector table that
holds the address of the interrupt service routine.
4. The microcontroller gets the address of the ISR from the interrupt vector table
and jumps to it. It starts to execute the interrupt service subroutine until it
reaches the last instruction of the subroutine, which is RETI (return from interrupt).
5. Upon executing the RETI instruction, the microcontroller returns to the place
where it was interrupted. First, it gets the program counter (PC) address from
the stack by popping the top two bytes of the stack into the PC. Then it starts
to execute from that address.

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