1

UNIT 1
LINEAR WAVESHAPING
1.0 INTRODUCTON
Based on the electrical conductivity all the materials in nature are classified as insulators,
semiconductors, and conductors.

A linear network is a network made up of linear elements only. A linear network

can be described by linear differential equations. The principle of superposition and the principle
of homogeneity hold good for linear networks. In pulse circuitry, there are a number of
waveforms, which appear very frequently. The most important of these are sinusoidal, step,
pulse, square wave, ramp, and exponential waveforms. The response of RC, RL, and RLC
circuits to these signals is described in this chapter. Out of these signals, the sinusoidal signal has
a unique characteristic that it preserves its shape when it is transmitted through a linear network,
i.e. under steady state, the output will be a precise reproduction of the input sinusoidal signal.
There will only be a change in the amplitude of the signal and there may be a phase shift
between the input and the output waveforms. The influence of the circuit on the signal may then
be completely specified by the ratio of the output to the input amplitude and by the phase angle
between the output and the input. No other periodic waveform preserves its shape precisely when
transmitted through a linear network, and in many cases the output signal may bear very little
resemblance to the input signal. The process whereby the form of a non-sinusoidal signal is
altered by transmission through a linear network is called linear wave shaping.

THE LOW-PASS RC CIRCUIT

Figure 1.1 shows a low-pass RC circuit. A low-pass circuit is a circuit, which transmits only low-
frequency signals and attenuates or stops high-frequency signals.

At zero frequency, the reactance of the capacitor is infinity (i.e. the capacitor acts as an open
circuit) so the entire input appears at the output, i.e. the input is transmitted to the output with
zero attenuation. So the output is the same as the input, i.e. the gain is unity. As the frequency
increases the capacitive reactance (Xc = H2nfC) decreases and so the output decreases. At very
high frequencies the capacitor virtually acts as a short-circuit and the output falls to zero.
 2

Sinusoidal Input
The Laplace transformed low-pass RC circuit is shown in Figure 1.2(a). The gain versus
frequency curve of a low-pass circuit excited by a sinusoidal input is shown in Figure 1.2(b).
This curve is obtained by keeping the amplitude of the input sinusoidal signal constant and
varying its frequency and noting the output at each frequency. At low frequencies the output is
equal to the input and hence the gain is unity. As the frequency increases, the output decreases
and hence the gain decreases. The frequency at which the gain is l/√2 (= 0.707) of its maximum
value is called the cut-off frequency. For a low-pass circuit, there is no lower cut-off frequency.
It is zero itself. The upper cut-off frequency is the frequency (in the high-frequency range) at
which the gain is 1/√2 . ie. 0.7%, of its maximum value. The bandwidth of the low-pass circuit is
equal to the upper cut-off frequency f2 itself

For the network shown in Figure 1.2(a), the magnitude of the steady-state gain A is given by
 3

Step-Voltage Input

A step signal is one which maintains the value zero for all times t < 0, and maintains the value V for
all times t > 0. The transition between the two voltage levels takes place at t = 0 and is accomplished
in an arbitrarily small time interval. Thus, in Figure 1.3(a), vi = 0 immediately before t = 0 (to be
referred to as time t = 0-) and vi = V, immediately after t= 0 (to be referred to as time t = 0+). In the
low-pass RC circuit shown in Figure 1.1, if the capacitor is initially uncharged, when a step input is
applied, since the voltage across the capacitor cannot change instantaneously, the output will be zero
at t = 0, and then, as the capacitor charges, the output voltage rises exponentially towards the steady-
state value V with a time constant RC as shown in Figure 1.3(b).

Let V’ be the initial voltage across the capacitor. Writing KVL around the LOOP in FIgure 1.1.
4
 5

Expression for rise time

When a step signal is applied, the rise time tr is defined as the time taken by the output voltage
waveform to rise from 10% to 90% of its final value: It gives an indication of how fast the circuit can
respond to a discontinuity in voltage. Assuming that the capacitor in Figure 1.1 is initially uncharged,
the output voltage shown in Figure 1.3(b) at any instant of time is given by

This indicates that the rise time tr is proportional to the time constant RC of the circuit. The larger the
time constant, the slower the capacitor charges, and the smaller the time constant, the faster the
capacitor charges.

Relation between rise time and upper 3-dB frequency

We know that the upper 3-dB frequency (same as bandwidth) of a low-pass circuit is

Thus, the rise time is inversely proportional to the upper 3-dB frequency.
The time constant (Τ= RC) of a circuit is defined as the time taken by the output to rise to 63.2% of
the amplitude of the input step. It is same as the time taken by the output to rise to 100% of the
amplitude of the input step, if the initial slope of rise is maintained. See Figure 1.3(b). The Greek
letter T is also employed as the symbol for the time constant.
 6

Pulse Input

The pulse shown in Figure 1.4(a) is equivalent to a positive step followed by a delayed negative step
as shown in Figure 1 .4(b). So, the response of the low-pass RC circuit to a pulse for times less than
the pulse width tp is the same as that for a step input and is given by

v0(t) = V(l – e-t/RC).

The responses of the low-pass RC circuit for time constant RC » tp, RC smaller than tp and RC very
small compared to tp are shown in Figures 1.5(a), 1.5(b), and 1.5(c) respectively.

If the fime constant RC of the circuit is very large, at the end of the pulse, the output voltage will be
Vp(t) = V(1 – e-tp/RC), and the output will decrease to zero from this value with a time constant RC as
shown in Figure 1.5(a). Observe that the pulse waveform is distorted when it is passed through a
linear network. The output will always extend beyond the pulse width tp, because whatever charge
has accumulated across the capacitor C during the pulse cannot leak off instantaneously.

If the time constant RC of the circuit is very small, the capacitor charges and discharges very quickly
and the rise time tr will be small and so the distortion in the wave shape is small. For minimum
distortion (i.e. for preservation of wave shape), the rise time must be small compared to the pulse
width tp. If the upper 3-dB frequency /2 is chosen equal to the reciprocal of the pulse width tp, i.e. if f2
= 1/tp then tr = 0.35tp and the output is as shown in Figure 1.5(b), which for many applications is a
reasonable reproduction of the input. As a rule of thumb, we can say
 7

Square-Wave Input
A square wave is a periodic waveform which maintains itself at one constant level V’ with respect to
ground for a time T1 and then changes abruptly to another level V", and remains constant at that level
for a time T2, and repeats itself at regular intervals of T = T1 + T2.
A square
Square wave may be treated as a series JNTU of positive
World and negative steps. The shape of the output
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waveform for a square wave input dependsJNTU on theWorld
time constant of the From
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very small, the rise time will also be small and a reasonable reproduction of the input may be
obtained. Asquare
For the square wave shown in Figure 1.6(a), the output waveform will be as shown in Figure 1.6(b) if
the time constant RC of the circuit is small compared to the period of the input waveform. In this
case, the wave shape is preserved. If the time constant is comparable with the period of the input
square wave, the output will be as shown id Figure 1.6(c). The output rises and falls exponentially. If
the time constant is very large compared to the period of the input waveform, the output consists of
exponential sections, which are essentially linear as indicated in Figure 1.6(d). Since the average
voltage across R is zero, the dc voltage at the output is the same as that of the input. This average
value is indicated as V&. in all the waveforms of Figure 1.6.
8
9
10
 11

When the time constant is very small relative to the total ramp time T, the ramp will be transmitted
with minimum distortion. The output follows the input but is delayed by one time constant RC from
the input (except near the origin where there is distortion) as shown in Figure 1.7(a). If the time
constant is large compared with the sweep duration, i.e. if RCIT » 1, the output will be highly
distorted as shown in Figure 1.7(b).

This shows that a quadratic response is obtained for a linear input and hence the circuit acts as an
integrator for RC/T » 1.

The transmission error et for a ramp input is defined as the difference between the input and the
output divided by the input at the end of the ramp, i.e. at t = T.

For RC/T « 1

where f2 is the upper 3-dB frequency. For example, if we desire to pass a 2 ms pulse with less than
0.1% error, the above equation yields f2 > 80 kHz and RC < 2 μ.s.
 12

Exponential Input

For the low-pass RC circuit shown in Figure 1.1, let the input applied as shown in Figure 1.8 be
vi(t ) = V(l – e-tlτ),, where T is the time constant of the input waveform.
 13

These are the expressions for the voltage across the capacitor of a low-pass RC circuit excited by an
exponential input of rise time tr1 - 2.2r. If an exponential of rise time tr1 is passed through a low-pass
circuit with rise time tr2, the rise time of the output waveform tr will be given by an empirical relation
,tr =1.05√tr12 + tr22 .This is same as the rise time obtained when a step is applied to a cascade of two
circuits of rise times trl and tr2 assuming that the second circuit does not load the first

THE LOW-PASS RC CIRCUIT AS AN INTEGRATOR

If the time constant of an RC low-pass circuit is very large, the capacitor charges very slowly and so
almost all the input voltage appears across the resistor for small values of time. Then, the current in
the circuit is vffylR and the output signal across C is

As time increases, the voltage drop across C does not remain negligible compared with that across R
and the output will not remain the integral of the input. The output will change from a quadratic to a
linear function of time. If the time constant of an RC low-pass circuit is very large in comparison
with the time required for the input signal to make an appreciable change, the circuit acts as an
integrator. A criterion for good integration in terms of steady-state analysis is as follows: The low-
pass circuit acts as an integrator provided the time constant of the circuit RC > 15T, where T is the
period of the input sine wave. When RC > 15T, the input sinusoid will be shifted at least by 89.4°
(instead of the ideal 90° shift required for integration) when it is transmitted through the network.
 14

An RC integrator converts a square wave into a triangular wave. Integrators are almost invariably
preferred over differentiators in analog computer applications for the following reasons

1. It is easier to stabilize an integrator than a differentiator because the gain of an integrator decreases
with frequency whereas the gain of a differentiator increases with frequency.
2. An integrator is less sensitive to noise voltages than a differentiator because of its limited
bandwidth.
3. The amplifier of a differentiator may overload if the input waveform changes very rapidly.
4. It is more convenient to introduce initial conditions in an integrator.

THE HIGH-PASS RC CIRCUIT

Figure 1.30 shows a high-pass RC circuit. At zero frequency the reactance of the capacitor is infinity
and so it blocks the input and hence the output is zero. Hence, this capacitor is called the blocking
capacitor and this circuit, also called the capacitive coupling circuit, is used to provide dc isolation
between the input and the output. As the frequency increases,'the reactance of the capacitor decreases
and hence the output and gain increase. At very high frequencies, the capacitive reactance is very
small so a very small voltage appears, across C and, so the output is almost equal to the input and the
gain is equal to 1. Since this circuit attenuates low-frequency signals and allows transmission of
high-frequency signals with little or no attenuation, it is called a high-pass circuit.
 15

Sinusoidal Input

Figure 1.31 (a) shows the Laplace transformed high-pass RC circuit. The gain versus frequency curve
of a high-pass circuit excited by a sinusoidal input is shown in Figure 1.31(b). For a sinusoidal input
v,, t;he output signal v0 increases in amplitude with increasing frequency. The frequency at which the
gain is 1/V2 of its maximum value is called the lower cut-off or lower 3-dB frequency. For a high-
pass circuit, there is no upper cut-off frequency because all high frequency signals are transmitted
with zero attenuation. Therefore, f2 – f1. Hence bandwidth B.W= f2 - fi =∞

Expression for the lower cut-off frequency

For the high-pass RC circuit shown in Figure 1.31 (a), the magnitude of the steady-state gain A, and
the angle θ by which the output leads the input are given by
 16

This is the expression for the lower cut-off frequency of a high-pass circuit

Step Input

When a step signal of amplitude V volts shown in Figure 1.32(a) is applied to the high-pass RC
circuit of Figure 1.30, since the voltage across the capacitor cannot change instantaneously the output
will be just equal to the input at t = 0 (for f < 0, v,- = 0 and va = 0). Later when the capacitor charges
exponentially, the output reduces exponentially with the same time constant RC. The expression for
the output voltage for t > 0 is given by
 17

byFigure 1.32(b) shows the response of the circuit for large, small, and very small time constants.
For t > 5r, the output will reach more than 99% of its final value. Hence although the steady state is
approached asymptotically, for most applications we may assume that the final value has been
reached after 5f. If the initial slope of the exponential is maintained, the output falls to zero in a time
t = T.

The voltage across a capacitor can change instantaneously only when an infinite current passes
through it, because for any finite current i(t) through the capacitor, the instantaneous change in
voltage across the capacitor is given by

Pulse Input
A pulse of amplitude V and duration tp shown in Figure 1.4(a) is nothing but the sum of a positive
step of amplitude V starting at t = 0 and a negative step of amplitude V starting at tp as shown in
Figure 1.4(b). So, the response of the circuit for 0 < t < t,, for the pulse input is the same as that for a
step input and is given by v0(t) = Ve-t/ RC. At t = tp, vo(t) = V = Ve-t/RC . At t = tp,

since the input falls by V volts suddenly and since the voltage across the capacitor cannot change
instantaneously, the output also falls suddenly by V volts to Vp - V. Hence at t = t + , va(t) = Ve-tp /RC -
V . Since Vp< V, Vp- V is negative. So there is an undershoot at t = tp and hence for t > tp, the output
is negative. For t > tp, the output rises exponentially towards zero with a time constant RC according
to the expression (Ve-tp/RC - V)e-(t-tp)/RC-

The output waveforms for RC » tp, RC comparable to tp and RC « tp are shown in Figures 1.33(a), (b),
and (c) respectively. There is distortion in the outputs and the distortion is the least when the time
constant is very large. Observe that there is positive area and negative area in the output waveforms.
The negative area will always be equal to the positive area. So if the time constant is very large the
tilt (the almost linear decrease in the output voltage) will be small and hence the undershoot will be
very small, and for t > tp, the output rises towards the zero level very very slowly. If the time
 18

constant is very small compared to the pulse width (i.e. RC/tp « T), the output consists of a positive
spike or pip of amplitude V volts at the beginning of the pulse and a negative spike of the same
amplitude at the end of the pulse. Hence a high-pass circuit with a very small time constant is called
a peaking circuit and this process of converting pulses into pips by means of a circuit of short time
constant is called peaking.

Square-Wave Input
A square wave shown in Figure 1.34(a) is a periodic waveform, which maintains itself at one
constant level V with respect to ground for a time T{ and then changes abruptly to another level V"
and remains constant at that level for a time T2, and then repeats itself at regular intervals of T = T\ +
T2. A square wave may be treated as a series of positive and negative steps. The shape of the output
depends on the time constant of the circuit. Figures 1.34(b), 1.34(c), 1.34(d), and 1.34(e) show the
output waveforms of the high-pass RC circuit under .steady-state conditions for the cases (a) RC » T,
(b) RC > T, (c) RC - T, and (d) RC « T respectively.

When the time constant is arbitrarily large (i.e. RC/T1 and RC/T2 are very very large in comparison to
unity) the output is same as the input but with zero dc level. When RC > T, the output is in the form
of a tilt. When RC is comparable to T, the output rises and falls exponentially. When RC « T (i.e.
RCIT\ and RC/T2 are very small in comparison to unity), the output consists of alternate positive and
negative spikes. In this case the peak-to-peak amplitude of the output is twice the peak-to-peak value
of the input.In fact, for any periodic input waveform under steady-state conditions, the average level
of the output waveform from the high-pass circuit of Figure 1.30 is always zero independently of the
dc level of the input. The proof is as follows: Writing KVL around the loop of Figure 1.30,
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Under steady-state conditions, the output waveform (as well as the input signal) is repetitive with a
period T so that v0(T) = v0(0) and v,(T) = v,(0)

Hence Since this integral represents the area under the output waveform over one
cycle, we can say that the average level of the steady-state output signal is always zero. This can also
be proved based on frequency domain analysis as follows. The periodic input signal may be resolved
into a Fourier series consisting of a constant term and an infinite number of sinusoidal components
whose frequencies are multiples of / = 1/T. Since the blocking capacitor presents infinite impedance
to the dc input voltage, none of these dc components reach the output under steady-state conditions.
Hence the output signal is a sum of sinusoids whose frequencies are multiples of/. This waveform is
therefore periodic with a fundamental period T but without a dc component. With respect to the high-
pass circuit of Figure 1.30, we can say that:

1. The average level of the output signal is always zero, .independently of the average level of the
input. The output must consequently extend in both negative and positive directions with respect to
the zero voltage axis and the area of the part of the waveform above the zero axis must equal the area
which is below the zero axis.
2. When the input changes abruptly by an amount V, the output also changes abruptly by an equal
amount and in the same direction.
3. During any finite time interval when the input maintains a constant level, the output decays
exponentially towards zero voltage.
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Under steady-state conditions, the capacitor charges and discharges to the same voltage levels in
each cycle. So the shape of the output waveform is fixed.
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Expression for the percentage tilt

We will derive an expression for the percentage tilt when the time constant RC of the circuit is very
large compared to the period of the input waveform, i.e. RC » T. For a symmetrical square wave with
zero average value
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Ramp Input

A waveform which is zero for t < 0 and which increases linearly with time for / > 0 is called a ramp
or sweep voltage. When the high-pass RC circuit of Figure 1.30 is excited by a ramp input v(r) = at,
where a is the slope of the ramp, then
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Figure 1.36 shows the response of the high-pass circuit for a ramp input when (a) RC» T, and (b) RC
« T, where T is the duration of the ramp. For small values of T, the output signal falls away slightly
from the input as shown in the Figure 1.36(a).

When a ramp signal is transmitted through a linear network, the output departs from the input. A
measure of the departure from linearity expressed as the transmission error e, is defined as the
difference between the input and the output divided by the input. The transmission error at a time

For large values of t in comparison with RC, the output approaches the constant value aRC as
indicated in Figure 1.36(b).
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Exponential Input

When the high-pass RC circuit of Figure 1.30 is excited by an exponential input v,(r) = V(l - e~'H)
shown in Figure 1.8, where T is the time constant of the input, the output taken across the resistor is
given by

If the time constant of the circuit is very high, n is high and the second term of the equation for n #
1 is negligible compared to the first term except for small values of time
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Near the origin of time the output follows the input. Also, the smaller the circuit time constant, the
smaller will be the output peak and the narrower will be the pulse. The larger the circuit time
constant, the larger will be the peak output and also the wider will be the pulse.

The maximum output occurs when

Since τ = t/T, the time to rise to peak tp is given by

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THE HIGH-PASS RC CIRCUIT AS A DIFFERENTIATOR

When the time constant of the high-pass RC circuit is very very small, the capacitor charges very
quickly; so almost all the input v,(0 appears across the capacitor and the voltage across the resistor
will be negligible compared to the voltage across the capacitor. Hence the current is determined
entirely by the capacitance. Then the current
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Thus we see that the output is proportional to the derivative of the input. The high-pass RC circuit
acts as a differentiator provided the RC time , constant of the circuit is very small in comparison
with the time required for the input signal to make an appreciable change. The derivative of a step
signal is an impulse of infinite amplitude at the occurrence of the discontinuity of step. The
derivative of an ideal pulse is a positive impulse followed by a delayed negative impulse, each of
infinite amplitude and occurring at the points of discontinuity. The derivative of a square wave is a
waveform which is uniformly zero except, at the points of discontinuity. At these points, precise
differentiation would yield impulses of infinite amplitude, zero width and alternating polarity. For a
square wave input, an RC high-pass circuit with very small time constant will produce an output,
which is zero except at the points of discontinuity. At these points of discontinuity, there will be
peaks of finite amplitude V. This is because the voltage across R is not negligible compared with that
across C. An RC differentiator converts a triangular wave into a square wave .For the ramp vi = at,
the value of RC(dv/dt) = aRC. This is true except near the origin. The output approaches the proper
derivative value only after a lapse of time corresponding to several time constants. The error near θ=
0 is again due to the fact that in this region the voltage across R is not negligible compared with that
across C.
If we assume that the leading edge of a pulse can be approximated by a ramp, then we can measure
the rate of rise of the pulse by using a differentiator. The peak output is measured on an oscilloscope,
and from the equation = aRC, we see that this voltage divided by the product RC gives the slope a.A
criteria for good differentiation in terms of steady-state sinusoidal analysis is, that if a sine wave is
applied to the high-pass RC circuit, the output will be a sine

wave shifted by a leading angle θ such that :with the output being proportional
to sin(a>t + θ). In order to have true differentiation, we must obtain cos ωt. In other words,θ must
equal 90°. This result can be obtained only if R =,0 or C = 0. However, if ωRC =0.01, then 1/ωRC =
100 and θ = 89.4°, which is sufficiently close to 90° for most purposes. If ωRC = 0.1, then 90 - 84.3°
and for some applications this may be close enough to 90°.If the peakvalue of input is Vm, the output
is

and if ωRC « 1, then the output is approximately VmωRC cos (at. This result agrees with the expected
value RC(dvt/dt). If ωRC = 0.01, then the output amplitude is 0.01 times the input amplitude.
 28

DOUBLE DIFFERENTIATION

Figure 1.38 shows two RC coupling networks in cascade separated by an amplifier A. It is assumed
that the amplifier operates linearly and that its output impedance is small relative to the impedance of
/?2 and C2. so that this combination does not load the amplifier. Let R\ be the parallel combination of
R and the input impedance of the amplifier. If the time constants R\C\ and R2C2 are small relative to
the period of the input waveform, then, this circuit performs approximately a second-order
differentiation. This circuit (Figure 1.38) can convert a ramp voltage into a pulse. The initial slope of
the output wave is the. Initial slope of the input multiplied by the gain of the amplifier. For this
reason this circuit is also called a rate-of-rise amplifier.

ATTENUATORS
Attenuators are resistive networks, which are used to reduce the amplitude of the input signal. The
simple resistor combination of Figure 1.61 (a) would multiply the input signal by the ratio a = R2/(R1
+ R2) independently of the frequency. If the output of the attenuator is feeding a stage of
amplification, the input capacitance C2 of the amplifier will be the stray capacitance shunting the
resistor R2 of the attenuator and the attenuator will be as shown in Figure 1.61(b), and the attenuation
now is not independent of frequency. Using Thevenin's theorem, the circuit in Figure 1.61(b) may be
replaced by its equivalent circuit shown in Figure 1,6l(c), in which R is equal to the parallel
combination of R1 and R2. Normally /?t and R2 must be large so that the nominal input impendence of
the attenuator is large enough to prevent loading down the input signal. But if R1 and R2 are large,
then rise time

tr = 2.2

will be large and a large rise time is normally unacceptable.

The attenuator may be compensated by shunting R\ by a capacitor C\ as shown in Figure 1.61(d), so

that its attenuation is once again independent of frequency. The circuit has been drawn in Figure
1.61(e) to suggest that the two resistors and the two capacitors may be viewed as the four arms of a
bridge. If R1C1 = R2C2, the bridge will be balanced and no current will flow in the branch connecting
the point X to the point Y. For the purpose of computing the output, the branch X-Y may be omitted
and the output will again be equal to CM, independent of the frequency. In practice, C1 will ordinarily
have to be made adjustable.
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Suppose a step signal of amplitude V volts is applied to the circuit. As the input changes abruptly by
V volts at t = 0, the voltages across Ci and C2 will also change abruptly. This happens because at / =
0, the capacitors act as short-circuits and a very large (ideally infinite) current flows though the

capacitors for an infinitesimally small time so that a finite charge is delivered to each
capacitor. The initial output voltage is determined by the capacitors.Since the same current flows
through the capacitors C1 and C2, we have
 30

Or

The final output voltage is determined by the resistors R\ and R2, because the capacitors C[ and C2 act
as open circuits for the applied dc voltage under steady-state conditions. Hence Looking back from
the output terminals (with the input short circuited) we see a resistor R = R{R2/(Ri + R2) in parallel
with C = C1 + C2. Hence the decay or rise of the output (when the attenuator is not perfectly
compensated) from the initial to the final value takes place exponentially with a time constant r =
RC. The responses of an attenuator for Cj equal to, greater than, and less than R2C2/R{ are indicated in
Figure 1.62.
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This is the balanced bridge condition. The extreme values of v0(0+) are 0 for C1 = 0 In the. above
analysis we have assumed that an infinite current flows through the capacitors at t = 0+ and hence the
capacitors get charged instantaneously. This is valid only if the generator resistance is zero. In
general, the output resistance of the generator is not zero but is of some finite value. Hence the
impulse response is physically impossible. So, even though the attenuator is compensated, the ideal
step response can never be obtained. Nevertheless, an improvement in rise time does result if a
compensated attenuator is used. For example, if the output is one-tenth of the input, then the rise time
of the output using the attenuator is one-tenth of what it would be without the attenuator.

The compensated attenuator will reproduce faithfully the signal, which appears at its input terminals.
However, if the output impedance of the generator driving the attenuator is not zero, the signal will
be distorted right at the input to the attenuator. This situation is illustrated in Figure 1.63(a) in which
a generator of step voltage V and of source resistance Rs is connected to the attenuator. Since the lead
which joins the point X and point Y may be open circuited, the circuit may be redrawn as in Figure
1.63(b). Usually Rs « R1+ R2, so the input to the attenuator will be an exponential of time constant
RsC', where C' is the capacitance of the series combination of Cj and C2> i.e. C' = C1 C/(C1 + C2). It
is this exponential waveform rather than the step, which the attenuator will transmit faithfully. If the
generator terminals were connected directly to the terminals to which the attenuator output is
 32

connected, the generator would see a capacitance C2. In this case the waveform at these terminals
would be an exponential with time constant T = RsC2.

Application of Attenuator as a CRO Probe

To measure the signal at a point in the circuit, the input terminals of the oscilloscope are connected to
the signal point. Normally the point at which the signal is available will be at some distance from the
oscilloscope terminals and if the signal appears at a high impedance level, a shielded cable is used to
connect the signal to the oscilloscope. The shielding is necessary in'this case to isolate the input lead
from stray fields such as those of the ever-present power line. The capacitance seen looking into
several feet of cable may be as high as 100 to 150 pF. This combination of high input capacitance
together with the high output impedence of the signal source will make it impossible to make faithful
observations of waveforms. A probe assembly, which permits the use of shielded cable and still
keeps the capacitance low, is indicated in Figure 1.64.
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RL CIRCUITS
In previous session we discussed the behaviour of RC low-pass and high-pass circuits for various
types of input waveforms. Suppose the capacitor C and-resistor R in those circuits are replaced by a
resistor R' and an inductor L respectively, then, if the time constant LIR' equals the time constant RC,
all the preceding results remain unchanged.

When a large time constant is required, the inductor is rarely used because a large value of
inductance can be obtained only with an iron-core inductor which is physically large, heavy and
expensive relative to the cost of a capacitor for a similar application. Such an iron-cored inductor will
be shunted with a large amount of stray distributed capacitance. Also the nonlinear properties of the
iron cause distortion, which may be undesirable. If it is required to pass very low frequencies through
a circuit in which L is" a shunt element, then the inductor may become prohibitively large. Of course
in circuits where a small value of /?' is tolerable, a more reasonable value of inductance may be used.
In low time constant applications, a small inexpensive air-cored inductor may be used.

Figure 1.73(a) shows the RL low-pass circuit. At very low frequencies the reactance of the inductor is
small, so the output across the resistor /?' is almost equal to the input. As the frequency increases, the
reactance of the inductor increases and so the signal is attenuated. At very high frequencies the
output is almost equal to zero. So the circuit in Figure 1.73(a) acts as a low-pass filter.The circuit of
Figure 1.73(b) acts as a high-pass circuit because at low frequencies, since the reactance of the
inductor is small, the output across the inductor is small and the output increases as the frequency
increases because the reactance of the inductor increases as the frequency increases and at high
frequencies the output is almost equal to the input.

Figure 1.74 shows how a square wave may be converted into pulses by means of the peaking coil L.
It is assumed that the bias voltage and the magnitude of the input are such that the transistor
operates linearly. Since the instantaneous voltage L(dildt) across an inductor cannot be infinite, the
current through an inductor cannot change instantaneously. Hence the inductor acts as an open
circuit at the time of an abrupt change in voltage. Figure 1.74(a) shows a transistor peaking circuit.
The input current waveform is shown in Figure 1.74(b). The output voltage waveform is shown in
Figure 1.74(c). If the base input is a square wave of current whose peak-to-peak value is /; then the
output voltage will have the waveform as in Figure 1.74(c). The peak voltage is now hfel/hoe and the
 34

time constant is hoeL assuming that the transistor can be replaced by it low-frequency hybrid
parameter model.

RLC CIRCUITS

RLC Series Circuit

Consider a series RLC circuit shown in Figure 1.75
 35

The response of i(t) and the response of v0(t) for the above three cases are shown in Figures 1.76(a)
and 1.76(b) respectively
 36

RLC Parallel Circuit

In the RL circuit shown in Figure 1.73(b), to include the effect of coil winding capacitance, output
capacitance and stray capacitance to ground, a capacitor is added across the output. So, the RLC
circuit shown in Figure 1.77(a) results. In terms of a current source, the equivalent circuit shown in
Figure 1.77(b) results

is similar to that to the current through the RLC series circuit with the difference that the
input to the RLC parallel circuit is a step current.
In the series RLC network, the current response to a step input voltage ultimately dies to zero because
of the capacitor in series. In the parallel RLC circuit the voltage across the RLC network is zero
because of the inductance.
 37

RINGING CIRCUIT

In a previous section it was seen that to obtain a pulse from a step voltage (peaking) the circuit
should operate in the neighborhood of critical damping. In some applications almost undamped
oscillations are required. A circuit, which can provide as nearly undamped oscillations as
possible is called a ringing circuit. If the damping is very small the circuit will ring for many
cycles. Many times the value of Q of a circuit which has to ring for a given number N of cycles
before the amplitude decreases to 1/6 of its initial value needs to be known. This is given by Q =
nN,
Thus, a circuit with Q = 12 will ring for Q/rc = 4 cycles before the amplitude of the oscillation
decreases to 37 per cent of its initial value. A ringing circuit may be used to generate a sequence
of pulses regularly spaced in time. These pulses find application in many timing operations.
 38

2.NON LINEAR WAVESHAPING

INTRODUCTION:

In the previous chapter we discussed about linear wave shaping. We saw how a change of wave
shape was brought about when a non-sinusoidal signal is transmitted through a linear network
like RC low pass and high pass circuit. In this chapter, we discuss some aspects of nonlinear
wave shaping like clipping and clamping. The circuits for which the outputs are non-sinusoidal
for sinusoidal inputs are called nonlinear wave shaping circuits, for example clipping circuits and
clamping circuits. Clipping means cutting and removing a part. A clipping circuit is a circuit
which removes the undesired part of the waveform and transmits only the desired part of the
signal which is above or below some particular reference level, i.e. it is used to select for
transmission that part of an arbitrary waveform which lies above or below some particular
reference. Clipping circuits are also called voltage (or current) limiters, amplitude selectors or
slicers. Nonlinear wave shaping circuits may be classified as clipping circuits and clamping
circuits. Clipping circuits may be single level clippers or two level clippers. Single level clippers
may be series diode clippers with and without reference or shunt diode clippers with and without
reference. Clipping circuits may use diodes or transistors. Clamping circuits may be negative
clampers (positive peak clampers) with and without reference or positive clampers (negative
peak clampers) with and without reference.

CLIPPING CIRCUITS

In general, there are three basic configurations of clipping circuits.

1. A series combination of a diode, a resistor and a reference voltage.
2. A network consisting of many diodes, resistors and reference voltages.
3. Two emitter coupled transistors operating as a differential amplifier.

Diode Clippers

Figure 2.1(a) shows the v-i characteristic of a practical diode. Figures 2.1(b), (c), (d), and (e) show
the v-I characteristics of an idealized diode approximated by a curve which is piece-wise linear and
continuous. The break point occurs at Vr, where Vr = 0.2 V for Ge and Vr = 0.6 V for Si. Usually Vr is
very small compared to the reference voltage VR and can be neglected.
 39

Shunt Clippers

Clipping above reference level

Using the ideal diode characteristic of Figure 2.2(a), the clipping circuit shown in Figure 2.2(b),
has the transmission characteristic shown in Figure 2.2(c). The transmission characteristic which
is a plot of the output voltage v0 as a function of the input voltage v, also exhibits piece-wise
linear discontinuity. The break point occurs at the reference voltage VR. To the left of the break
point i.e. for vt < VR the diode is reverse biased (OFF) and the equivalent circuit shown in Figure
2.2(d) results. In this region the signal v, may be transmitted directly to the output, since there is
no load across the output to cause a drop across the series resistor /?. To the right of the break
point i.e. for v( > VR the diode is forward biased (ON) and the equivalent circuit shown in
Figure 2,2(e) results and increments in the inputs are totally attenuated and the output is fixed at
VR. Figure 2.2(c) shows a sinusoidal input signal of amplitude large enough so that the signal
makes excursions past the break point. The corresponding output exhibits a suppression of the
positive peak of the signal. The output will appear as if the positive peak had been clipped off or
sliced off
 40

Figure 2.2 (a) v-i characteristic of an ideal diode, (b) diode clipping circuit, which removes that part of the
waveform that is more positive than VR, (c) the piece-wise linear transmission characteristic of the
circuit, a sinusoidal input and the clipped output, (d) equivalent circuit for v( < VR, and (e) equivalent
circuit for v, > VR.

Clipping below reference level

If this clipping circuit of Figure 2.2(b), is modified by reversing the diode as shown in Figure
2.3(a), the corresponding piece-wise linear transfer characteristic and the output for a sinusoidal
input will be as shown in Figure 2.3(b). In this circuit, the portion of the waveform more positive
than VR is transmitted without any attenuation but the portion of the waveform less positive than
VR is totally suppressed. For Vj < VR, the diode conducts and acts as a short circuit and the
equivalent circuit shown in Figure 2.3(c) results and the output is fixed at VR. For v, > VR, the
diode is reverse biased and acts as an open circuit and the equivalent circuit shown in Figure
2.3(d) results and the output is the same as the input.
41
 42

Figure 2.3 (a) A diode clipping circuit, which transmits that part of the sine wave that is more
positive than VR, (b) the piece-wise linear transmission characteristic, a sinusoidal input and the
clipped output, (c) equivalent circuit for v( < VR, and (d) equivalent circuit for v,- > VR.
In Figures 2.1(b) and 2.2(a), we assumed that Rr = °° and Rf = 0. If this condition does not apply, the
transmission characteristic must be modified. The portions of those curves which are indicated as
having unity slope must instead be considered as having a slope of Rrl(Rr + R), and those, having
zero slope as having a slope of /?/(/?/ + /?). In the transmission region of a diode clipping circuit, it is
required that Rr » R, i.e. Rr = kR, where k is a large number, and in the attenuation region, it is
required that R » Rf. From these equations we can deduce that R = J RrxR^ , i.e. the external
resistance R is to be selected as the geometric mean of Rf and /?,. The ratio RrIRf serves as a figure of
merit for the diodes used in these applications. A zener diode may also be used in combination with a
p-n junction diode to obtain single-ended clipping, i.e. one-level clipping.

Series Clippers

Clipping above the reference voltage VR

Figure 2.4(a) shows a series clipper circuit using a p-n junction diode. VR is the reference
voltage source. The diode is assumed to be ideal (/?/ = 0, Rr = °°, Vy= 0) so that it acts as a short
circuit when it is ON and as a open circuit when it is OFF. Since the diode is in the series path
connecting the input and the output it is called a series clipper. The v0 versus v, characteristic
called the transfer characteristic is shown in Figure 2.4(b). The output for a sinusoidal input is
shown in Figure 2.4(c)

The circuit works as follows: For v, < VR, the diode Dj is forward biased because its anode is at
a higher potential than its cathode. It conducts and acts as a short circuit and the equivalent
circuit shown in Figure 2.4(d) results. The difference voltage between the input v,- and the
reference voltage VR i.e. (VR – vi) is dropped across . Therefore v0 = vi and the slope of the
transfer characteristic for vi < VR is 1. Since the input signal is transmitted to the output without
any change, this region is called the transmission region.
 43

Figure 2.4 (a) Diode series clipper circuit diagram, (b) transfer characteristic, (c) output waveform
for a sinusoidal input, (d) equivalent circuit for v; < VR, and (e) equivalent circuit for v( > VR.

For v, > VR, the diode is reverse biased because its cathode is at a higher potential than its anode, it
does not conduct and acts as an open circuit and the equivalent circuit shown in Figure 2.4(e) results.
No current flows through R and so no voltage drop across it. So the output voltage v0 = VR and the
slope of the transfer characteristic is zero. Since the input signal above V R is clipped OFF for v, > VR,
this region is called the clipping region. The equations V0=Vi for Vi < VR and V0= VR for Vi > VR are
called the transfer characteristic equations.

Clipping below the reference voltage VB

Figure 2.5(a) shows a series clipper circuit using a p-n junction diode and a reference voltage
source VR. The diode is assumed to be ideal (Rf = 0, Rr = °°, Vy = 0) so that it acts as a short
circuit when it is ON and as a open circuit when it is OFF. Since the diode is in the series path
connecting the input and the output it is called a series clipper. The transfer characteristic is
shown in Figure 2.5(b). The output for a sinusoidal input is shown in Figure 2.5(c).
 44

Figure 2.5 (a) Diode series clipper circuit diagram, (b). transfer characteristics, (c) output for a
sinusoidal input, (d) equivalent circuit for vi- < VR, and (e) equivalent circuit for vi- > VR.

The circuit works as follows:

For vi < VR, D is reversed biased because its anode is at a lower potential than its cathode. The
diode does not conduct and acts as an open circuit and the equivalent circuit shown in Figure
2.5(d) results. No current flows through R and hence no voltage drop across R and hence vo =
VR- So the slope of the transfer characteristic is zero for v, < VR. Since the input is clipped off
for v, < VR, this region is Called the clipping region. For v, > VR, the diode is forward biased
because its anode is at a higher potential than its cathode. The diode conducts and acts as a short
circuit and the equivalent circuit shown in Figure 2.5(e) results. Current flows through /? and the
difference voltage between the input and the output voltages v, - VR drops across /? and the
output v0 = vi. The slope of the transfer characteristic for v, > VR is unity. Since the input is
transmitted to the output for v; > VR, this region is called the transmission region. The equations

are called the transfer characteristic equations. Some single-ended diode clipping circuits, their
transfer characteristics and the output waveforms for sinusoidal inputs are shown below (Figure 2.6)
 45

Some single-ended clipping circuits

46
47
48
 49

In the clipping circuits, the diode may appear as a series element or as a shunt element. The use
of the diode as a series element has the disadvantage that when the diode is OFF and it is
intended that there be no transmission, fast signals or high frequency waveforms may be
transmitted to the output through the diode capacitance. The use of the diode as a shunt element
has the disadvantage that when the diode is open and it is intended that there be transmission, the
diode capacitance together with all other capacitances in shunt with the output terminals will
round off the sharp edges of the input waveforms and attenuate, the high frequency signals.

Clipping at Two Independent Levels

A parallel, a series, or a series-parallel arrangement may be used in double-ended limiting at two

independent levels. A parallel arrangement is shown in Figure 2.7. Figure 2.8 shows the transfer
characteristic and the output for a sinusoidal input. The input-output characteristic has two
breakpoints, one at v0 = v, = VR1 and the second at v0 = v, = -VR2 and has the following
characteristics.
 50

The two level diode clipper shown in Figure 2.8 works as follows. For v, > VR1, DI is ON and D2 is OFF
and the equivalent circuit shown in Figure 2.9(a) results. So the output v0 = VR1 and the slope of the
transfer characteristic is zero

For v, < - VR2, DI is OFF and D2 is ON and the equivalent circuit shown in Figure 2.9(b) results. So
the output v0 = - VR2 and the slope of the transfer characteristic is zero. For-VR2 < v, < VRI, D! is OFF
and D2 is OFF and the equivalent circuit shown in Figure 2.10 results. So the output v0 = v/ and the
slope of the transfer characteristic is one. The circuit of Figure 2.7 is called a slicer because the
output contains a slice of the input between two reference levels V R! and VR2. Looking at the input
and output waveforms, we observe that this circuit may be used to convert a sine wave into a square
wave, if VDI = Vm. and if the amplitude of the input signal is very large compared with the
difference in the reference levels, the output will be a symmetrical square wave. Two zener diodes in
series opposing may also be used to form a double-ended clipper.
 51

If the diodes have identical characteristics, then, a symmetrical limiter is obtained. Some double-
ended clippers, their transfer characteristics and the outputs for sine wave inputs are shown in
Figure 2.11.

Some double-ended clipping circuits

52
 53

Series and Shunt Noise Clippers

Practically actual signals will be mostly associated with unwanted noise signals. The presence of
noise signals may adversely affect sensitive circuits. So the noise signals must be eliminated to make
the actual signal free from distortions and fluctuations. Noise signals can be eliminated by employing
noise clippers. These clippers use two or more diodes depending upon whether the noise is quite
small or considerably large. Noise clippers are of two types: series noise clippers and shunt noise
clippers.

Series noise clipper

Figure 2.12 shows a series noise clipper. This type of clipper circuits are used when the amplitude of
the noise voltage is not greater than Vr the forward voltage drop of the diode and the signal voltage
has an amplitude larger than VY. When the input signal along with noise shown in Figure 2.13(a) is
applied at the input, the diode Dj will conduct when the amplitude exceeds + Vy, the diode Da will
conduct when the amplitude falls below - Vyand no diode will conduct when the amplitude is
between + Vyand - Vy. Therefore, the noise within the limits of + V yand - Vy is clipped and the signal
above Vy during positive cycle and the signal below - Vy during negative cycle will appear at the
output. The output voltage waveform is shown in Figure 2.13(b). The effective amplitude of the
output voltage is ± (Vimax - Vy)
 54

Shunt noise clipper

A shunt noise clipper shown in Figure 2.14 is used when the noise associated with the input signal at
the peaks is to be eliminated. When the input signal with noise shown in Figure 2.15(a) is applied at
the input, for -Vy< v, < Vy, there is no conduction as both the diodes get reverse biased and are OFF.
Hence output voltage will follow the input voltage,V0 = V,-.When v, > Vr , the diode Dt is ON and the
diode D2 is OFF. Hence the output voltage v0 = Vr and it remains at Vy until the signal amplitude falls
below Vy. Thus the noise riding the signal voltage positive peaks is eliminated. When v, < -Vy , the
diode DI is OFF and the diode D2 is ON. Hence the output voltage v0 = -Vy and it remains at -Vy until
the signal amplitude rises above -Vy. Thus the noise riding the signal voltage negative peak is
eliminated. The output waveform is as shown in Figure 2.15(b).

Transistor Clippers
A nonlinear device is required for clipping purposes. A diode exhibits a nonlinearity, which
occurs when it goes from OFF to ON. On the other hand, the transistor has two pronounced
nonlinearities, which may be used for clipping purposes. One occurs when the transistor crosses
from the cut-in region into the active region and the second occurs when the transistor crosses
from the active region into the saturation region. Therefore, if the peak-to-peak value of the input
waveform is such that it can carry the transistor across the boundary between the cut-in and
active regions, or across the boundary between the active and saturation regions, a portion of the
input waveform will be clipped. Normally, it is required that the portion of the input waveform,
which keeps the transistor in the active region shall appear at the output without distortion. In
that case, it is required that the input current rather than the input voltage be the waveform of the
signal of interest. The reason for this requirement is that over a large signal excursion in the
active region, the transistor output current responds nominally linearly to the input current but is
related in a quite nonlinear manner to the input voltage. So, in transistor clippers a current drive
needs to be used.

A transistor clipper is shown in Figure 2.19. The resistor R which represents either the signal source
impedance or a resistor deliberately introduced must be large compared with the input resistance of
the transistor in the active region. Under these circumstances, the input base current will very nearly
have the waveform of the input voltage, because the base current is given by where Vr
is the base-to-emitter cut-in voltage. Vy » 0.1 V for Ge and Vy ~ 0.5 V for Si
 55

If a ramp input signal vi which starts at a voltage below cut-off and carries the transistor into
saturation is applied, the base voltage, the base current, and the collector current waveforms of the
transistor clipper will be as shown in Figure 2.20.
 56

The waveforms which result when a sinusoidal voltage v, carries the transistor from cut-off to
saturation are shown in Figure 2.21. The base circuit is biased so that cut-in occurs when VBE reaches
the voltage V.
 57

Figure 2.21 Waveforms for the transistor clipper of figure 2.19: (a) in put voltage and the base –to-
emitter voltage (b) the base current (c) the collector current (d) the output voltage
 58

Emitter-Coupled Clipper

An emitter-coupled clipper is shown in Figure 2.22. It is a two-level clipper using transistors. The
base of Q2 is fixed at a voltage VBB2, and the input is applied to B1. If initially the input is negative,
Q1 is OFF and only Q2 carries the current. Assume that VBB2 has been adjusted so that Q2 operates in
its active region. Let us assume that the current / in the emitter resistance is constant. This is valid if
IVBE2I is small compared to VBB2 + VEE,When vt is below the cut-off point of Q1, all the current 7
flows through Q2. As v, increases, Q1 will eventually come out of cut-off, both the transistors will be
carrying currents but the current in Q2 decreases while the current in Q1 increases, the sum of the
currents in the two transistors remaining constant and equal to 7. The input signal appears at the
output, amplified but not inverted. As v1 continues to increase, the common emitter will follow the
base of Q1. Since the base of Q2 is fixed, a point will be reached when the rising emitter voltage cuts
off Q2. Thus, the input signal is amplified but twice limited, once by the cutoff of Q 1 and once by the
onset of cut-off in Q2. The total rangeAv0, over which the output can follow the input is VE and is
constant and therefore adjustable through an adjustment of 7. The absolute voltage of the portion
of the input waveform selected for transmission may be selected through an adjustment of a
biasing voltage on which v, is superimposed or through an adjustment of VBB2- The total range of
input voltage Av, between the clipping limits is Av0/A, where A is the gain of the amplifier stage.
Figure 2.23 shows the transfer characteristic of an emitter-coupled clipper.
 59

Comparators

A comparator circuit is one, which may be used to mark the instant when an arbitrary waveform
attains some particular reference level. The nonlinear circuits, which can be used to perform the
operation of clipping, may also be used to perform the operation of comparison. In fact, the clipping
circuits become elements of a comparator system and are Usually simply referred to as comparators.
The distinction between comparator circuits and the clipping circuits is that, in a comparator there is
'no interest in reproducing any part of the signal waveform, whereas in a clipping circuit, part of the
signal waveform is needed to be reproduced without any distortion
 60

Figure 2.70 shows the circuit diagram of a diode comparator. As long as the input voltage v, is less
than the reference voltage VR, the diode D is ON and the output is fixed at VR. When v, > VR, the
diode is OFF and hence v0 = v,. The break occurs at v, = VR at time t = t\. So, this circuit can be used
to mark the instant at which the input voltage reaches a particular reference level VR.
Comparators

Comparators may be non-regenerative or regenerative. Clipping circuits fall into the category of non-
regenerative comparators. In regenerative comparators, positive feedback is employed to obtain an
infinite forward gain (unity loop gain). The Schmitt trigger and the blocking oscillator are examples
of regenerative comparators. The Schmitt trigger comparator generates approximately a step input.
The blocking oscillator comparator generates a pulse rather than a step output waveform. Most
applications of comparators make use of the step or pulse natures of the input. Operational amplifiers
and tunnel diodes may also be used as comparators.

Applications of voltage comparators

Voltage comparators may be used:
1. In accurate time measurements
2. In pulse time modulation
3. As timing markers generated from a sine wave.
4. In phase meters
5. In amplitude distribution analyzers
6. To obtain square wave from a sine wave
7. In analog-to-digital converters.

CLAMPING CIRCUITS

Clamping circuits are circuits, which are used to clamp or fix the extremity of a periodic waveform to
some constant reference level V.R. Under steady-state conditions, these circuits restrain the extremity
of the waveform from going beyond VR. Clamping circuits may be one-way clamps or two-way
clamps. When only one diode is used and a voltage change in only one direction is restrained, the
circuits are called one-way clamps. When two diodes are used and the voltage change in both the
directions is restrained, the circuits are called two-way clamps
The Clamping Operation

When a signal is transmitted through a capacitive coupling network (RC high-pass circuit), it looses
its dc component, and a clamping circuit may be used to introduce a dc component by fixing the
positive or negative extremity of that waveform to some reference level. For this reason, the
clamping circuit is often referred to as dc restorer or dc reinserter. In fact, it should be called a dc
inserter, because the dc component introduced may be different from the dc component lost during
transmission. The clamping circuit only changes the dc level of the input signal. It does not affect its
shape

Classification of clamping circuits

Basically clamping circuits are of two types: (1) positive-voltage clamping circuits and (2) negative-
voltage clamping circuits.
 61

In positive clamping the negative extremity of the waveform is fixed at the reference level and the
entire waveform appears above the reference level, i.e. the output waveform is positively clamped
with reference to the reference level. In negative clamping, the positive extremity of the waveform is
fixed at the reference level and the entire waveform appears below the reference, i.e. the output
waveform is negatively clamped with respect to the reference level. The capacitors are essential in
clamping circuits. The difference between the clipping and clamping circuits is that while the clipper
clipps off an unwanted portion of the input waveform, the clamper simply clamps the maximum
positive or negative peak of the waveform to a desired level. There will be no distortion of waveform

Negative Clamper

Figure 3.1 (a) shows the circuit diagram of a basic negative clamper. It is also termed a positive peak
clamper since the circuit clamps the positive peak of a signal to zero level. Assume that the signal
source has negligible output impedance and that the diode" is ideal, Rf= 0 n and Vy = 0 V in that, it
exhibits an arbitrarily sharp break at 0 V, and that its input signal shown in Figure 2.71(b) is a
sinusoid which begins at t = 0. Let the capacitor C be uncharged at t = 0.
During the first quarter cycle, the input signal rises from zero to the maximum value. The diode
conducts during this time and since we have assumed an ideal diode, the voltage across it is zero. The
capacitor C is charged through the series combination of the signal source and the diode and the
voltage across C rises sinusoidally. At -the end of the first quarter cycle, the voltage across the
capacitor, vc = Vm. When, after the first quarter cycle, the peak has been passed and the input signal
begins to fall, the voltage vc across the capacitor is no longer able to follow the input, because there is
no path for the capacitor to discharge. Hence, the voltage across the capacitor remains constant at v c
= Vm, and the charged capacitor acts as a voltage source of V volts and after the first quarter cycle,
the output is given by v0 = v, - Vm. During the succeeding cycles, the positive extremity of the signal
will be clamped or restored to zero and the output

Waveform shown in Figure 2.7 l(c) results. Therefore

 62

Suppose that after the steady-state condition has been reached, the amplitude of the input signal is
increased, then the diode will again conduct for at most one quarter cycle and the dc voltage across
the capacitor would rise to the new peak value, and the positive excursions of the signal would be
again restored to zero. Suppose the amplitude of the input signal is decreased after the steady-state
condition has been reached. There is no path for the capacitor to discharge. To permit the voltage
across the capacitor to decrease, it is necessary to shunt a resistor across C, or equivalently to shunt a
resistor across D. In the latter case, the capacitor will discharge through the series combination of the
resistor R across the diode and the resistance of the source, and in a few cycles the positive extremity
would be again clamped at zero as shown in Figure 2.72(b). A circuit with such a resistor 'R is shown
in Figure 2.72(a)

Positive Clamper

Figure 2.73(a) shows a positive clamper. This is also termed as negative peak clamper since this
circuit clamps the negative peaks of a signal to zero level. The negative peak clamper, i.e. the
positive clamper introduces a positive dc.
 63

Let the input voltage be vi = Vm sin (ot as shown in Figure 2.73(b). When v, goes negative, the diode
gets forward biased and conducts and in a few cycles the capacitor gets charged to Vm with the
polarity shown in Figure 2.73(a). Under steady-state conditions, the capacitor acts as a constant
voltage source and the output is

Based on the above relation between v0 and v,, the output voltage waveform is plotted. As seen in
Figure 2.73(c) the negative peaks of the input signal are clamped to zero level. Peak-to-peak value
of output voltage = peak-to-peak value of input voltage = 2Vm. There is no distortion of waveform.
To accommodate for variations in amplitude of input, the diode D is shunted with a resistor as
shown in Figure 2.74(a). When the amplitude of the input waveform is reduced, the output will
adjust to its new value as shown in Figure 2.74(b).

Biased Clamping

If a voltage source of VR volts is connected in series with the diode of a clamping circuit, the input
waveform will be clamped with reference to VR. Depending on the position of the diode, the input
waveform may be positively clamped with reference to V R, or negatively clamped with reference to
VR.

Clamping Circuit Taking Source and Diode Resistances Into Account

In the discussion of the clamping circuit of Figure 2.71, we neglected the output resistance of the
source as well as the diode forward resistance. Many times these resistances cannot be neglected.
Figure 2.79 shows a more realistic clamping circuit taking into consideration the output resistance of
the source Rs, which may be negligible or may range up to many thousands of ohms depending on
the source, and the diode forward resistance Rf which may range from tens to hundreds of ohms.
Assume that the diode break point Vy occurs at zero voltage.

Figure 2.79 Clamping circuit considering the source resistance and the diode forward resistance.
 64

The precision of operation of the circuit depends on the condition that R » Rf, and Rr » R. When the
input is positive, the diode is ON and the equivalent circuit shown in Figure 2.80(a) results. When the
input is negative, the diode is OFF and the equivalent circuit shown in Figure 2.80(b) results.
Figure 2.80 (a) Equivalent circuit when the diode is conducting and (b) the equivalent circuit when
the diode is not conducting.

Figure 2.80 (a) Equivalent circuit when the diode is conducting and (b) the equivalent circuit when
the diode is not conducting.

The transient waveform

When a signal is suddenly applied to the circuit shown in Figure 2.79 the capacitor charges (transient
period) and gradually the steady-state condition is reached in which the positive peaks will be
clamped to zero. The equivalent circuits shown in Figures 2.80(a) and 2.80(b) may be used to
calculate the transient response.
Relation between tilts in forward and reverse directions

The steady-state output waveform for a square wave input. Consider that the square wave input
shown in Figure 2.82(a) is applied to the clamping circuit shown in Figure 2.79. The general form of
the output waveform would be as shown in Figure 2.82(b), extending in both positive and negative
directions and is determined by the voltages V1, V2, V11, and V'2. These voltages may be calculated as
discussed below.

In the interval 0 < t < T, the input is at its higher level; so the diode is ON and the capacitor charges
with a time constant (Rs + Rf)C, and the output decays towards zero with the same time constant.

Hence, ------- (i)

In the interval T1< t < T1 + T2, the input is at its lower level; so the diode is OFF and the capacitor
discharges with a time constant (R + RS)C, and the output rises towards zero with the same time
constant.
Hence --------- (ii)
 65

Considering the conditions at t= 0. At t = 0~, vs = V", v0 = V2, the diode D is OFF and the equivalent
circuit of Figure 2.80(b) results. The voltage across the capacitor is given by

--------- (iii)
At t = 0+, the input signal jumps to V, the output jumps to Vt, the diode conducts and the equivalent
circuit of Figure 2.80(a) results. The voltage across the capacitor is given by

----------(iv)

Since the voltage across the capacitor cannot change instantaneously, equating equations (iii) and
(iv), we have

----------(viii)

Figure 2.82 (a) A square wave input signal of peak-to-peak amplitude V, (b) the general form
of the steady-state output of a clamping circuit with;' the input as in (a)
 66

Considering the conditions at t= Tr. At t = Tr, vs = V, v0 = V1, the diode D is ON, and the equivalent
circuit of Figure 2,80(a) results. The voltage across the capacitor is given by

----------- (vi)

At t = Tr, , vs = V"=v0 = V2, the diode D is OFF, and the equivalent circuit of Figure 2.80(b) results.

The voltage across the capacitor is given by

---------- (vii)

Since the voltage across the capacitor cannot change instantaneously, equating equations (vi) and
(vii), we get

---------- (viii)

From equations (i), (ii), (v) and (viii), the values V1, V’, V2 and V2’ can be computed and the output
waveform determined.

If the source impedance is taken into account, the output voltage jumps are smaller than the abrupt
discontinuity V in the input. Only if Rs = 0, are the jumps in input and output voltages equal. Thus,
when Rs = 0,Observe that the response is independent of the absolute levels V' and V" of the input
signal and is determined only by the amplitude V. It is possible, for example, for V" to be negative or
even for both V and V" to be negative.

The average level of the input plays no role in determining the steady-state output waveform.
Under steady-state conditions, there is a tilt in the output waveform in both positive and negative
directions. The relation between the tilts can be obtained by subtracting Eq. (viii) from Eq. (v), i.e.

Where,

Since Rs is usually much smaller than R, then, the tilt in the forward direction Ay is almost
always less than the tilt Ar in the reverse direction. Only when Rs « Rf, are the two tilts almost equal.
 67

Clamping Circuit Theorem

Under steady-state conditions, for any input waveform, the shape of the output waveform of a
clamping circuit is fixed and also the area in the forward direction (when the diode conducts) and the
area in the reverse direction (when the diode does not conduct) are related.

The clamping circuit theorem states that, for any input waveform under steady-state conditions,
the ratio of the area Af under the output voltage curve in the forward direction to that in the
reverse direction Ar is equal to the ratio R/Rf-

This theorem applies quite generally independent of the input waveform and the magnitude of the
source resistance
.
The proof is as follows:

Consider the clamping circuit of Figure 2.79, the equivalent circuits in Figures 2.80(a) and 2.80(b),
and the input and output waveforms of Figures 2.82(a) and 2.82(b) respectively.

In the interval 0 < t < T, the input is at its upper level, the diode is ON, and the equivalent circuit of
Figure 2.80(a) results. If v/(f) is the output waveform in the forward direction, then the

capacitor charging current is

Therefore, -the charge gained by the capacitor during the forward interval is

In the interval TJ < t < T{ + T2, the input is at its lower level, the diode is OFF, and the equivalent
circuit of Figure 2.80(b) results. If vr(t) is the output voltage in the reverse directionthen the current

which discharges the capacitor is

Therefore, the charge lost by the capacitor during the reverse interval is

Under steady-state conditions, the net charge acquired by the capacitor over one cycle must be equal
to zero. Therefore, the charge gained in the interval 0 < t < T}, will be equal to the charge lost in the
interval T1 < t < T1 + T2, i.e. Qg = Ql
 68

3. SWITCHING CHARACTERISTICS OF DEVICES

INTRODUCTION:

Electronic devices such as junction diodes, thermionic diodes, transistors, and vacuum tubes all have
extreme regions of operation in which they nominally do not conduct even when large voltages are
applied, and there are regions in which they conduct heavily even when relatively small voltages are
applied- In the first of these regions, the device is described as being OFF, OPEN, or non-
conducting. In the other extreme region the device is described as being ON, CLOSED or
conducting, when the device is driven from one extreme condition to the other, it operates much like
a switch.

JUNCTION DIODE—SWITCHING TIMES

Diode forward recovery time

When a diode is driven from the: reverse-biased condition to the forward-biased condition or in the
opposite direction, the diode response is accompanied by a transient, and an interval of time elapses
before the diode recovers to its steady state. The nature of the forward recovery transient depends on the
magnitude of the current being driven through the diode and the rise time of the driving signal.

Figure 3.1(aj Input step current to a diode, (b) diode voltage when the current is large, arid (c) diode
voltage when the current is small
 69

Consider the voltage which develops across the diode when the input is a current source
supplying a step current Iv as shown in Figure 3,1 (a). If the current amplitude is comparable to
or larger than the diode rated current, and if the rise time of the current step is small enough, then
the waveform of the voltage which appears across the diode is shown in Figure 3.1(b). The
overshoot results from the fact that initially the diode acts not as a p-n junction diffusion device
but as a resistor, tn the steady-state condition, the current which flows through the diode is a
diffusion current which results from the gradient in the density of minority carriers. If the current
is large enough, then there will also be an ohmic drop across the diode. The ohmic drop is
initially very large, for immediately after the application of the current, the holes, say, will npn
have time to diffuse very far into the n-side in order to build up a minority carrier density.
Therefore except near the junction, there will be no minority charge to establish a density
gradient, and the current flow through the mechanism of diffusion will not be possible. Indeed,
an electric field will be required to achieve current flow by exerting force on the majority
carriers. This electric field gives rise to the ohmic drop. With the passage of time, however, the
ohmic drop will decrease as more and more minority carriers become available from the
junction, and current by diffusion takes over
The magnitude of the overshoot will increase as the magnitude of the input current increases. At
large current amplitudes, the diode behaves as a combination of a resistor and an inductor. At
low currents the diode is representable by a parallel resistor-capacitor combination. At
intermediate currents, the diode behaves as a resistor, inductor, and capacitor circuit and
oscillations may be produced. The forward recovery time ffr, for a specified rise time of the input
current is the time difference between the 10% point of the diode voltage and the time when this
voltage reaches and remains within 10% of its final value. The forward recovery time does not
usually constitute a serious problem.

Diode reverse recovery time

When an external voltage is impressed across a junction in the direction that reverse biases it,
very little current called the reverse saturation current flows. This current is because of the
minority carriers. The density of minority carriers in the neighborhood of the junction in the
steady state is shown in Figure 3.2(a). Here the levels pnl) and n are the thermal equilibrium
values of the minority carrier densities on the two sides of the junction in the absence of an
externally impressed voltage. When a reverse voltage is applied, the density of minority carriers
is shown by the solid Sines marked pn and np. Away from the junction, the minority carrier
density remains unaltered, but as these carriers approach the junction they are rapidly swept
across and the density of minority carriers diminishes to zero at the junction. The reverse
saturation current which flows is small because the density of thermally generated minority
carriers is very small.
 70

Figure 3.2 Minority-carrier density distribution as a function of the distance x from a junction; (a) a
reverse-biased junction and (b) a forward-biased junction.

When the external voltage forward biases the junction, the steady-state density of minority
carriers is as shown in Figure 3.2(b). The injected or excess hole density is (pn - pnQ) and the
excess electron density is (np - npQ). In a diode circuit which has been carrying current in the
forward direction, if the external voltage is suddenly reversed, the diode current will not
immediately fall to its steady-state reverse value. The current cannot attain its steady-state value
until the minority carrier distribution changes the form in Figure 3.2(b) to the distribution shown
in Figure 3.2(a). Until such time as the injected or excess minority carrier density pn - pnQ (or np
-np0) drops nominally to zero, the diode will continue to conduct easily and the current will be
determined by the external resistance in the diode circuit.
 71

Figure 3.3 The waveform in (b) is applied to the diode circuit in (a), (c) the excess carrier density at
the junction, (d) the diode current, and (e) the diode voltage.

Storage and transition times

The sequence of events which occurs when a conducting diode is reverse biased is shown in Figure
3.3. The input voltage shown in Figure 3.3(b) is applied to a diode circuit shown in Figure 3.3(a). Up
to t = t\, v, = Vf. The resistance RL is assumed large so that the drop across RL is large compared
with the drop across the diode

At the time t ~ t[, the input voltage reverses abruptly to the value V; = - VR, the current reverses,

until the time t - t2. At t ~ t^ as shown in Figure 3.3(c) the injected minority carrier
density at the junction drops to zero, that is, the minority carrier density reaches its equilibrium state.
If the diode ohmic resistance is RA, then at time t\, the diode voltage falls slightly by [(VF + VR)]
but does not reverse as shown in Figure 3.3(e). At t = ?2 when the excess minority carriers in the
immediate neighborhood of the junction have been swept back across the junction, the diode voltage
begins to reverse as shown in Figure 3.3(e) and the magnitude of the diode current begins to decrease
as shown in Figure 3.3(d). The interval from t\ to t2 for the minority charge to become zero is called
 72

the storage time ts. The time which elapses between r2 and the time when the diode has nominally
recovered is called the transition time tt. The recovery interval will be completed when the minority
carriers which are at some distance from the junction have diffused to the junction, crossed it and
then, in addition, the junction transition capacitance across the reverse-biased junction has charged
through RL to the voltage -VR as shown in Figure 3.3(e).

PIECE-WISE LINEAR DIODE CHARACTERISTICS

A large-signal approximation which often leads to a sufficiently accurate engineering solution is the
piece-wise linear representation. The piece-wise linear approximation for a semiconductor diode
characteristic is shown in Figure 3.4. The breakdown is at Vy, which is called the offset or threshold
voltage. The diode behaves like an open-circuit if v < Vr The characteristic shows a constant
incremental resistance r =dvldi if v > Vr Here r is called the forward resistance. The static resistance
Rf = Vγ is not constant and is not useful.

The numerical values of Vy and Rf to be used depend upon the type of diode and the contemplated
voltage and current swings. Typically: For current swings from cut-off to 10 mA

For current swings up to 50 mA

 73

BREAKDOWN IN P-N JUNCTION DIODES

When the p-n junction diode is reverse biased, reverse saturation current /0 flows due to minority
carriers. There is a gradual increase in reverse current with increasing bias due to the ohmic leakage
currents around the surface of the junction. When the reverse bias voltage approaches the breakdown
voltage VBO» tnere 's a sudden increase in reverse current due to breakdown. Once breakdown
occurs, the diode no longer blocks current, and the diode current can now be controlled only by the
resistance of the external circuit.

Avalanche breakdown

Thermally generated minority carriers cross the depletion region and acquire sufficient kinetic energy
from the applied potential to produce new carriers by removing valance electrons from other bonds.
These new carriers will in turn collide with other atoms and thus increase the number of electrons
and holes available for conduction. Because of the cumulative increase in carrier density after each
collision, the process is known as avalanche breakdown.

Zener breakdown

Even if the initially available carriers do not gain enough energy to disrupt bonds, it is possible to
initiate breakdown through a direct rupture of the bonds because of the existence of a strong electric
field. Under these circumstances the breakdown is referred to as zener breakdown. Zener breakdown
occurs at voltages below 6 V. The operating voltages in avalanche breakdown are from several volts
to several hundred volts with power rating up to 50 W. The breakdown in a p-n junction diode is
shown in Figure 3.5.

True zener diode action displays a negative temperature coefficient, i.e. the breakdown voltage
decreases with increase in temperature. True avalanche diode action exhibits a positive temperature
coefficient, i.e. the breakdown voltage increases with increase in temperature.The breakdown voltage
for a particular diode can be controlled during manufacture by altering the doping levels in the
 74

junction. The breakdown voltage for silicon diodes can be made to occur at a voltage as low as 5 V
with 1017 impurity atoms/cm3 or as high as 1000 V when doped to a level of only 104 impurity
atoms/cm3

TRANSISTOR AS A SWITCH

A transistor can be used as a switch. It has three regions of operation. When both emitter^ base and
collector-base junctions are reverse biased, the transistor operates in the cut-o! region and it acts as
an open switch. When the emitter base junction is forward biased and the collector base junction is
reverse biased, it operates in the active region and acts as auf amplifier. When both the emitter-base
and collector-base junctions are forward biased, it! operates in the saturation region and acts as a
closed switch. When the transistor is switched! from cut-off to saturation and from saturation to cut-
off with negligible active region, thej transistor is operated as a switch. When the transistor is in
saturation, junction voltages are'i very small but the operating currents are large. When the transistor
is in cut-off, the currents* are zero (except small leakage current) but the junction voltages are
large.In Figure 3.6 the transistor Q can be used to connect and disconnect the load RL from the
source Vcc When Q is saturated it is like a closed switch from collector to emitter and when Q is cut-
off it is like an open switch from collector to emitter.

Referring to the output characteristics shown in Figure 3.6(b), the region below the IB = 0 curve is
the cut-off region. The intersection of the load line with IB = 0 curve is the cut-off point. At this
point, the base current is zero and the collector current is negligible. The emitter diode comes out of
forward bias and the normal transistor action is lost, i.e, VCE(cut-off) = Vcc. The transistor appears
like an open switch.

The intersection of the load line with the IB - Ie(sat) curve is called the saturation point. At this point,
the base current is IB(sat) and the collector current is maximum. 'At saturation, the collector diode
comes out of cut-off and again the normal transistor action is lost, i.e. Ic(sat) = Vcc/RL.Ib(sat)
 75

represents the minimum base current required to bring the transistor into saturation. For 0 < IB <
IB(sat), the transistor operates in the active region. If the base current is greater than IB(sat), the
collector current approximately equals VCC/IC and the transistor appears like a closed switch.

TRANSISTOR SWITCHING TIMES

When the transistor acts as a switch, it is either in cut-off or in saturation. To consider the behaviour
of the transistor as it makes transition from one state to the other, consider the circuit shown in Figure
3,7(a) driven by the pulse waveform shown in Figure 3.7(b). The pulse waveform makes transitions
between the voltage levels V2 and V1. At V2 the transistor is at cut-off and at V the transistor is in
saturation. The input waveform v; is applied between the base and the emitter through a resistor RB.

Figure 3.7 (a) Transistor as a switch, (b) input waveform, and (c) the response of collector current
versus time.

The response of the collector current ic to the input waveform, together with its time relationship to
the waveform is shown in Figure 3.7(c), The collector current does not immediately respond to the
input signal. Instead there is a delay, and the time that elapses during this delay, together with the
time required for the current to rise to 10% of its maximum (saturation) value (ICs = Vcc/Rc) is
called the delay time td. The current waveform has a nonzero rise time fr, which is the rise time
required for the current to rise from 10% to 90% of Ics- The total turn-on time TON is the sum of the
delay time and the rise time, i.e. TON = td + tr. When the input signal returns to its initial state, the
collector current again fails to respond immediately. The interval which elapses between the
transition of the input waveform and the time when /c has dropped to 90% of /Cs is called the storage
time ts. The storage interval is followed by the fall time ly, which is the time required for 7C to fall
from 90% to 10% of Ics- The turn-off time ^OFF is defined as the sum of the storage and fall times,
i.e. TOFF = tr + tf We shall now consider the physical reasons for the existence of each of these
times.

The delay time

There are three factors that contribute to the delay time. First there is a delay which results from the
fact that, when the driving signal is applied to the transistor input, a non-zero time is required to
 76

charge up the junction capacitance so that the transistor may be brought, from cut-off to the active
region. Second, even when the transistor has been brought to the point where minority carriers have
begun to cross the emitter junction into the base, a nonzero time is required before these carriers can
cross the base region to the collector junction and be recorded as collector current. Finally, a nonzero
time is required before the collector current can rise to 10% of its maximum value. Rise time and fall
time The rise time and fall time are due to the fact that, if a base current step is used to saturate the
transistor or to return it from saturation into cut-off, the collector current must traverse the active
region. The collector current increases or decreases along an exponential curve. Storage time The
failure of the transistor to respond to the trailing edge of the driving pulse for the time interval ts,
results from the fact that a transistor in saturation has a saturation charge of excess minority carriers
stored in the base. The transistor cannot respond until the saturation excess charge has been removed.

BREAKDOWN VOLTAGES OF A TRANSISTOR

In a transistor switch", the voltage change which occurs at the collector with switching is nominally
equal to the collector supply voltage Vcc, Since this voltage will be used to operate other circuits and
devices, then for the sake of reliability of operation, VCc should be made as large as possible. The
maximum allowable voltage depends not only on the characteristics of the transistor but also on the
associated transistor base circuitry. The maximum reverse biasing voltage which may be applied
before breakdown between the collector and base terminals of the transistor, under the condition that
the emitter lead be open-circuited is represented by the symbol BVCB0. This breakdown voltage is a
characteristic of the transistor alone. Breakdown occurs because of the avalanche multiplication of
the current ICo that crosses the collector junction. As a result of this multiplication the current
becomes AIco, in which M is the factor by which the original current ICo is multiplied by the
avalanche effect. At a high enough voltage, namely BVCBO, the multiplication factor M becomes
nominally infinite and the region of breakdown is then attained. Here the current rises abruptly and
large changes in current accompany small changes in applied voltage.

The avalanche multiplication factor M depends on the voltage VCB between the collector and the
base, i.e.

The parameter n lies in the range 2 to 10 and controls the sharpness of the onset of breakdown. When
n is large, M continues at nearly unity until VCB approaches very close to BVcBO at. which point M
soars upwards abruptly. When n is small, the onset of breakdown is gradual.
 77

In Figure 3.8(a) the CB characteristics have been extended into the breakdown region. The curve for
IF = 0 is a plot, as a function of VCB of the product of the reverse collector current Ico and the
avalanche multiplication factor M. The abrupt growth in Ic as BVcBO is approached, is shown along
with the slower increase in Ic over the active region that results from the small but not negligible
avalanche multiplication.

Figure 3.8 (a) CB characteristics extended into the breakdown region and (b) idealized CE
characteristics extended into the breakdown region.

If a current IE is caused to flow through the emitter junction, then neglecting the avalanche effect, a
fraction α IE reaches the collector junction, where a is the common base current gain. Taking
multiplication into account, /c has the magnitude Mα. Consequently it appears that in the presence of
avalanche multiplication, the transistor behaves as though its common base current gain were

Now α is a positive number with a maximum magnitude less than unity but A/a may equal unity in
magnitude at which point /IFE becomes infinite. Accordingly, any base current no matter how small,
will give rise to an arbitrarily large collector current whenever Ma = 1 . It means breakdown has
occurred. Therefore, whenever the base current is kept fixed, breakdown occurs at the voltage VCB
which satisfies the equation

or breakdown occurs at the voltage VCB given by

 78

Since VCB at breakdown .is much larger than the small forward base-to-emitter voltage
VBE, we may replace VCB by VCE in the above equation. Also

Therefore, the collector-to-emitter breakdown voltage, with open-circuited base, BVCEO is

For an n-p-n Ge transistor, a reasonable value for n is 6. If hfe= 50, then ,If
BVCEO = 40 V, BVCBO is about half of that, i.e. about 20 V. The breakdown voltage with base not
open-circuited

Assume that the base is returned to the emitter through a resistor RB as shown in Figure 3.9(a). We
accept that the breakdown voltage BVCEO lies between BVCER and 5VCBO-To estimate BVCEO
some assumptions are made concerning the emitter-base junction diode. The semiconductor junction
diode exhibits a threshold voltage Vr in the forward direction. That is, until the forward voltage
attains about 0.2 V in Ge or 0.6 V in Si, the forward current is very small. We shall assume that until
the threshold has been reached, the collector current will flow entirely to the base and hence through
IB. We also assume that once the threshold voltage is exceeded, nearly all the additional collector
current will flow through the emitter junction and the corresponding breakdown voltage is 5VCBO.
Therefore, when the collector-to-emitter voltage is larger than BVceo the threshold voltage of the
emitter junction is reached, breakdown will occur. On this, we accept breakdown when the collector
current A//CO satisfies the relation,

Figure 3.9 (a) Plot extended into the breakdown region of collector current against VCE for various
connections to the base. The sustaining voltage is (Vcgo and 0>) common collector transistor circuit.
 79

This equation is valid if the current in Rs is very large compared with the currents in collector and
emitter. If Rs = 0, i.e. if the base is short-circuited to emitter,

If r'BB is present, then base spreading resistance must also be taken into account along with
is to be considered. Accordingly, even when RB = 0, BVCES is lower in magnitude
than BVCBO After breakdown has occurred, the collector and the emitter currents will become very
large compared with the base current. Therefore, at large currents, the presence of Ag makes no
difference and the voltage across the transistor will drop from #VCER to BVcex The breakdown
voltage may also be increased by returning the resistor J?B to a voltage VBB as shown in Figure
3.9(b) which provides some back bias for the emitter junction. In this case the condition which
determines the onset of breakdown is and the breakdown voltage, now
represented by the symbol BVcEX is approximately given by

THE TRANSISTOR SWITCH IN SATURATION

When a transistor switch is driven from saturation to cut-off, one of the factors which has an
important effect on the speed of response is the time required to charge the capacitance which
appears in shunt across the output terminals of the transistor. This capacitance must charge through
the load resistance RL, and for this reason, in fast switching circuits, RL must be kept small. In
saturation, the transistor current is nominally VCC/RL, and since RL is small, it may be necessary to
keep Vcc correspondingly small in order to stay within the limitations imposed by the transistor on
the maximum current and dissipation. The total voltage swing at the transistor switch is Vcc -
VCE(sat). The largest possible output swing is desirable in order to reduce the sensitivity of the
switching circuit to noise, supply voltage fluctuations, transistor ageing, and replacement.

For the transistor switch of Figure 3.10(a), it is difficult to read VCE(sat) from Figure 3.10(b). By
changing scale, Figure 3.10(b) can be drawn as shown in Figure 3.10(c).

In these characteristics, the 0 to - 0.5 V region of Figure 3.10(b) has been expanded and the same
load line is drawn. At /B = - 0.15 mA, the transistor is in saturation and 1VCEI = 175 mV. At IB= -
0.35 mA, Ice' has dropped to 100 mV. For a transistor operating in the saturation region, a quantity of
interest is the ratio VCE(sat)/Ic- This parameter is called the common emitter saturation resistance.

The saturation voltage VCE(sat) depends not only on the operating point but also on the
semiconductor material (Ge or Si) and on the type of transistor construction. Alloy-junction
transistors and epitaxial transistors give the lowest values for VCE(sat), whereas the grown junction
transistors yield the highest. Germanium transistors have lower values for VcE(sat) than those for
silicon. An alloy-junction Ge transistor may allow, with adequate base currents, values for VCE(sat)
 80

as low as tens of milli-volts at collector currents which are some tens of milli-amperes. Similarly,
epitaxial silicon transistors may yield saturation voltage as low as 0.2 V with collector currents as
high as an ampere. On the other hand, the grown junction Ge transistors have saturation voltages
which are several tenths of a volt and silicon transistors of this type may have saturation voltages as
high as several volts.

In the saturation region, h is a useful parameter and is supplied by the manufacturer. Once we know,
(Ic-VccIRi) and hFE, the amount of base current IB = IC hFE needed to saturate the transistor can be
found.

TEMPERATURE SENSITIVITY OF SATURATION PARAMETERS At constant base and

collector currents, the forward base-to-emitter voltage H/BE' has a typical temperature sensitivity in
 81

the range -1.5 to -2 mV/°C. This applies both to Ge and Si transistors. A plot for Ge of VBE versus
the ambient temperature is shown in Figure 3.1l(a). A similar characteristic for silicon has
approximately the same slope. In saturation, the transistor consists of two forward-biased junctions
back-to-back, series opposing. It is consequently to be anticipated that the temperature induced
voltage change in one junction will be cancelled in some measure by the change in the other junction.
Such is the case for VBE(sat) as well, as shown in Figure 3.11(b). The temperature dependence of
hFE is shown in Figure 3.11(c). At small and moderate currents, increases substantially with
temperature. At high currents, /IFE may well become rather insensitive to temperature.
 82

DESIGN OF TRANSISTOR SWITCH

Any transistor amplifier that has the property of inversion, can.be used as an inverter. The transistor
that acts as a switch is driven between cut-off and saturation. A transistor inverter is shown in Figure
3.12.For low input vi = V(0), the transistor is kept at cut-off, so the output is Vcc or V(l). For high
input, i.e. for vi = V(l), the transistor is driven into saturation. So the output v0 = VCE(sat) = V(0).
Thus the circuit acts as a switch. To improve the transient response of
 83

4.MULTIVIBRATORS
INTRODUCTION

Multi means many; vibrator means oscillator. A circuit which can oscillate at a number of
frequencies is called a multi vibrator. Basically there are three types of multivibrators: 1. Bistable
multi vibrator 2. Mono stable multi vibrator 3. Astable multi vibrator

Each of these multivibrators has two states. As the names indicate, a bistable multivibrator has got
two stable states, a monostable multivibrator has got only one stable state (the other state being quasi
stable) and the astable multivibrator has got no stable state (both the states being quasi stable). The
stable state of a multivibrator is the state in which the device can stay permanently. Only when a
proper external triggering signal is applied, it will change its state. Quasi stable state means
temporarily stable state. The device cannot stay permanently in this state. After a predetermined time,
the device will automatically come out of the quasi stable state. In this chapter we will discuss
multivibrators with two-stage regenerative amplifiers. They have two cross-coupled inverters, i.e. the
output of the first stage is coupled to the input of the second stage and the output of the second stage
is coupled to the input of the first stage. In bistable circuits both the coupling elements are resistors
(i.e. both are dc couplings). In monostable circuits, one coupling element is a capacitor (ac coupling)
and the other coupling element is a resistor (dc coupling) In astable multivibrators both the coupling
elements are capacitors (i.e. both are ac couplings). A bistable multivibrator requires a triggering
signal to change from one stable state to another. It requires another triggering signal for the reverse
transition. A monostable multivibrator requires a triggering signal to change from the stable state to
the quasi stable state but no triggering signal is required for the reverse transition, i.e. to bring it from
the quasi stable state to the stable state. The astable multivibrator does not require any triggering
signal at all. It keeps changing from one quasi stable state to another quasi stable state on its own the
moment it is connected to the supply. A bistable multivibrator is the basic memory element. It is used
to perform many digital operations such as counting and storing of binary data. It also finds extensive
applications in the generation and processing of pulse type waveforms. The monostable multivibrator
finds extensive applications in pulse circuits. Mostly it is used as a gating circuit or a delay circuit.
The astable circuit is used as a master oscillator to generate square waves. It is often a basic source of
fast waveforms. It is a free running oscillator. It is called a square wave generator. It is also termed a
relaxation oscillator.

BISTABLE MULTIVIBRATOR

A bistable multivibrator is a multivibrator which can exist indefinitely in either of its two stable
states and which can be induced to make an abrupt transition from one state to the other by means of
external excitation. In a bistable multivibrator both the coupling elements are resistors (dc coupling).
The bistable multivibrator is also called a multi, Eccles-Jordan circuit (after its inventors), trigger
circuit, scale-of-two toggle circuit, flip-flop, and binary. There are two types of bistable
multivibrators:
1. Collector coupled bistable multivibrator
2. Emitter coupled bistable multivibrator
 84

There are two types of collector-coupled bistable multivibrators:

1. Fixed-bias bistable multivibrator
2. Self-bias bistable multivibrator

A FIXED-BIAS BISTABLE MULTIVIBRATOR

Figure 4.1 shows the circuit diagram of a fixed-bias bistable multivibrator using transistors
(inverters). Note, that the output of each amplifier is direct coupled to the input of the other amplifier.
In one of the stable states, transistor Q[ is ON (i.e. in saturation) and Q2 is OFF (i.e. in cut-off), and in
the other stable state Qj is OFF and Q2 is ON. Even though the circuit is symmetrical, it is not
possible for the circuit to remain in a stable state with both the transistors conducting (i.e. both
operating in the active region) simultaneously and carrying equal currents. The reason is that if we
assume that both the transistors are biased equally and are carrying equal currents /[ and 7 2 and
suppose there is a minute fluctuation in the current 1\~—let us say it increases by a small amount—
then the voltage at the collector of Qi decreases. This will result in a decrease in voltage at the base
of Q2. So Q2 conducts less and /2 decreases and hence the potential at the collector of Q2 increases.
This results in an increase in the base potential of Qi. So, Qi conducts still more and /[ is further
increased and the potential at the collector of Qt is further reduced, and so on. So, the current I\ keeps
on increasing and the current /2 keeps on decreasing till Q( goes into saturation and Q2 goes into cut-
off. This action takes place because of the regenerative feedback incorporated into the circuit and
will occur only if the loop gain is greater than one.A stable state of a binary is one in which the
voltages and currents satisfy the Kirchhoff's laws and are consistent with the device characteristics
and in which, in addition, the condition of the loop gain being less than unity is satisfied.
The condition with respect to loop gain will certainly be satisfied, if either of the two devices is
below cut-off or if either device is in saturation. But normally the circuit is designed such that in a
stable state one transistor is in saturation and the other one is ir cut-off, because if one transistor is
biased to be in cut-off and the other one to be in active region, as the temperature changes or the
devices age and the device parameters vary, the quiescent point changes and the quiescent output
voltage may also change appreciably Sometimes the drift may be so much that the device operating
in the active region may gc into cut-off, and with both the devices in cut-off the circuit will be
useless.
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Selection of components in the fixed-bias bistable multivibrator

In the fixed-bias binary shown in Figure 4.1., nearly the full supply voltage Vcc will appear across
the transistor that is OFF. Since this supply voltage Vcc is to be reasonably smaller than the collector
breakdown voltage SVce. Vcc *s restricted to a maximum of a few tens of volts. Under saturation
conditions the collector current Ic is maximum. Hence RC must be chosen so that this value of 7C (=
VCC/^G) does not exceed the maximum permissible limit. The values of R\, /?2 and VBB must be
selected such that in one stat>le state the base current is large enough to drive the transistor into
saturation whereas in the second stable state the emitter junction must be below cut-off. The signal at
a collector called the output swing Vw is the change in collector voltage resulting from a transistor
going from one state to the other, i.e. Vw = VCi - ^C2- If the loading caused by RI can be neglected,
then the collector voltage of the OFF transistor is Vcc. Since the collector saturation voltage is few
tenths of a volt, then the swing Vw = Vcc, independently of RQ- The component values, the supply
voltages and the values of /CBO, h^, VBE(sat), and VCE(sat) are sufficient for the analysis of
transistor binary circuits.

Loading
The bistable multivibrator may be used to drive other circuits and hence at one or both the collectors
there are shunting loads, which are not shown in Figure 4.1. These loads reduce the magnitude of the
collector voltage VC1 of the OFF transistor. This will result in reduction of the output voltage swing.
A reduced VC[ will decrease 7B2 and it is possible that Q2 may not be driven into saturation- Hence
the flip-flop circuit components must be chosen such that under the heaviest load, which the binary
drives, one- transistor remains in saturation while the other is in cut-off. Since the resistor Rl also
loads the OFF transistor, to reduce loading, the value of R] should be as large as possible compared
to the value of Rc. But to ensure a loop gain in excess of unity during the transition between the
states, R^ should be selected such that For some applications, the loading varies with the operation
being performed. In such cases, the extent to which a transistor is driven into saturation is variable. A
constant output swing V\v = V, arid a constant base saturation current IB2 can be obtained by
clamping the collectors to an auxiliary voltage V < Vcc through the diodes DI and D2 as indicated in
Figure 4.2. As Qi cuts OFF, its collector voltage rises and when it reaches V, the "collector catching
diode" D| conducts and clamps the output to V. J
 86

Transistor as an ON-OFF switch

In digital circuits transistors operate either in the cut-off region or in the saturation region. Specially
designed transistors called switching transistors with negligible active region are used. In the cut-off
region the transistor does not conduct and acts as a open switch. In the saturation region the transistor
conducts heavily and acts as a closed switch-In a binary which uses two cross-coupled transistors,
each of the transistors is alternately cut-off and driven into saturation. Because of regenerative
feedback provided both the transistors cannot be.ON or both cannot be OFF simultaneously. When
one transistor is ON, the other is OFF and vice versa.
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COMMUTATING CAPACITORS
We know that the bistable multivibrator has got two stable states and that it can remain in either of its
two stable states indefinitely. It can change state only when a triggering signal such as a pulse from
some external source is applied. When a triggering signal is applied, conduction has to transfer from
one device to another. The transition time is defined as the interval during which conduction transfers
from one transistor to another. The reason for this transition time is—even 'though the input signal at
the base of a transistor may be transferred to the collector with zero rise time, the signal at the
collector of the transistor cannot be transferred to the base of the other transistor instantaneously.
This is because the input capacitance C, present at the base of the transistor makes the R\-R2
attenuator act as an uncompensated attenuator and so it will have a finite rise time, tr = (R[\\R2)Ci.
The transition time may be reduced by compensating this att'.nuator by introducing a small capacitor
in parallel with the coupling resistors R{ and R\ of the binary as shown in Figure 4.21. Since these
capacitors are introduced to increase the speed of operation of the device, they are called speed-up
capacitors. They are also called transpose or commutating capacitors. So, commutating capacitors are
small capacitors connected in parallel with the coupling resistors in order to increase the speed of
operation. The commutating capacitors hasten the removal of charge stored at the base of the ON
transistor due to minority carriers. If the commutating capacitors are arbitrarily large, the /?]-/?2
network acts as an overcompensated attenuator and the signal at the collector will be transmitted to
the base of the other transistor very rapidly, but large values of capacitors have some disadvantages.
In the flip-flop shown in Figure 4.21, if for example Oj is OFF and Q2 is ON, the voltages across C]
and C'\ are not alike because, when Q2 is ON and Qj is OFF, the voltage across C[ is VCK2(sat) -
VBi(off) which is very small = 0.3 - (-1) = 1.3 V, and the voltage across C\ is equal to Vcc -
VBE2(sat) ~ 12 - 0.7 = 11.3 V. When the circuit is triggered so that Q2 is OFF and Oj is ON, then
the voltage-across C[ must be 11.3 V and that across C[ must be 1.3 V. The flip-flop would not have
settled in its new state until the interchange of voltages had been completed. A transistor having been
induced to change the state by a triggering signal, a certain minimum time must elapse before a
succeeding signal is able to reliably induce the reverse transition. The smallest allowable interval
between triggers is called the resolving time of the flip-flop, and its reciprocal is the maximum
frequency at which the binary will respond.

The 'complete transfer of conduction from one device to another involves two phases. The first of
these is the transition time during which conduction transfers from one device to another. For this
transfer of conduction to take place, the voltages across the input and output capacitances of the
transistor have to change. The voltages across the commutating capacitors C[ and Cj need not change
during this transfer of conduction. After this transfer of conduction, the capacitors are allowed to
interchange their voltages. This additional time required for the purpose of completing the recharging
of capacitors after the transfer of conduction is called the settling time. Of course, no clear-cut
distinction can be made between the transition time and the settling time. The sum of the transition
time and the settling time is called the resolution time. If the commutating capacitors are too small,
the transition time is increased but the settling time will be small and if the commutating capacitors
are too large, -the transition time is reduced but the settling time will be large. So, a compromise is
called for.
 88

The maximum frequency of operation /max is given by

Methods of improving resolution

The resolution of a binary can be improved by taking the following steps:

1. By reducing all stray , capacitances. Reductions in the values of stray capacitances reduce their
charging time, resulting in a reduction in the time taken by the transistors to go to the opposite state.

2. By reducing the resistors R^, R2, and Rc. Reductions in the values of /?j and /?2 result in a
reduction in the charging time of the commutating capacitors with a consequent improvement in
transition speed. Reducing resistors also reduces the recovery time.

3. By not allowing the transistors to go into saturation. When the transistors do not saturate, the
storage time will be reduced resulting in fast change from ON to OFF
 89

A NON-SATURATING BINARY

The binary discussed earlier is a saturated binary. When the transistors are driven into saturation,
because of the storage time delay, the speed of operation is reduced. The speed of operation can be
increased by not allowing the transistors to go into saturation. Such a binary in which the transistors
always operate in the active region only, is called a non-saturating binary.

Figure 4.22 shows the circuit diagram of a non-saturating binary. This is obtained adding two zener
diodes and two p-n junction diodes to the collector-coupled binary sho' in Figure 4.21. These diodes
ensure that the collector ta» junctions are reverse biased hence the transistor is always operating in
the active region. Both the zener diodes D3 D4 are always biased in the breakdown direction and
each has a voltage Vz < VQC it. The voltage across the diode DI or D2 is very small in the forward
direction. When is ON, its emitter junction is forward biased with VBE2 * 0 V. So, the left side of
D2 is at Vz and the right side is at VcE(sat). Therefore, D2 is ON and acts as a short circuit. Hence
C2 = ^z> making the collector junction reverse biased, and the transistor Ch operates in the active
region.

Figure 4.22 A non-saturated binary.

 90

This negative voltage keeps Qt cut-off. With Q, cut-off, VCEI is HIGH and so the diode DI is back
biased. The output swing is approximately equal to VCG - Vz. The non-saturating binary is preferred
over the saturated binary only when an extremely high speed of operation is required because of the
following drawbacks:

1. The non-saturating circuits are more complicated than the saturated, circuits.

2. The non-saturating circuits consume more power than the saturated circuits.

3. The voltage swing is less stable with temperature, ageing and component replacement than in the
case of saturated binary.

TRIGGERING THE BINARY

We know that a bistable multivibrator has got two stable states and that it can remain in any one of
the states indefinitely. The process of applying an external signal to induce a transition from one state
to the other is called triggering. The triggering signal, which is usually employed is either a pulse of
short duration or a step voltage. There are two methods of triggering—unsymmetrical triggering and
symmetrical triggering. Unsymmetrical triggering is one in which the triggering signal is effective in
inducing a transition in only one direction. In this, a second triggering signal from a separate source
must be introduced in a different manner to achieve reverse transition, Symmetrical triggering is one
in which each successive triggering signal induces a transition regardless of the state in which the
binary happens to be, i.e unsymmetrical triggering requires two separate sources whereas
symmetrical triggering requires only one source. Unsymmetrical triggering finds extensive
applications in logic circuitry (in registers, coding, etc.)- It can be used as a generator of a gate whos
width equals the interval between the triggers. Symmetrical triggering is used in binary counting
circuits and other applications.
 91

Figure 4,23 Unsymmetrical triggering through a resistor and a capacitor (a) at the collectors
and (b) at the bases.

The sensitivity of the binary to a pulse of such polarity as to turn OFF the conducting device will
appreciably exceed the sensitivity to a pulse of opposite polarity. The triggering signal may be
applied at the output of a stage or at the input of a stage. In transistor circuits the triggering signal
may be applied at the collector of the transistor, or at the base. An excellent method for triggering a
binary unsymmetrically on the leading edge of a pulse is to apply the pulse from a high impedance
source to the output of the non-conducting device For p-n-p transistors, a positive pulse needs to be
applied.

The triggering signal may be applied through a resistor and a capacitor or through a unilateral device
such as a diode. Figure 4.23 shows a method of triggering un-symmetncally through a resistor and a
capacitor. If p-n-p transistors are employed, the polarity of the . triggering signal should be reversed.

TRIGGERING UNSYMMETRICALLY THROUGH A UNILATERAL DEVICE (DIODE)

Figure 4.24 shows unsymmetrical triggering through a unilateral device when the signals are applied
at the collectors. Suppose in one stable state Q [ is ON and Q2 is OFF. When Q| is ON, the diode D
at the collector of Qj is back biased by the drop across Rc because its anode is at VCE(sat) and
cathode is at Vcc. So the diode will not transmit a positive pulse and even the negative pulse cannot
be transmitted unless it has an amplitude larger than this voltage drop which anyway cannot affect
the state of Q2. So no change of state can take place by the application of a pulse at the collector of
Qj when Q1 is ON, When Q2 is OFF, both anode and cathode of the diode at its collector are at Vcc
and so the drop across D is zero. The diode will still fail to transmit a positive-going trigger, but will
 92

transmit a negative pulse or step to the input (base) of Qj (which is ON) which will result in a change
of state. So when Qi is ON and Q2 is OFF, only a negative pulse applied at 'R' can change the state.
The resistor R must be large enough not to load down the trigger source. On the other hand, R must
be small enough so that any charge which accumulates on C during the interval when D conducts
will have time to decay during the time between pulses. If the triggering rate is high, then it may be
necessary to replace R with a diode. Figure 4.25 shows unsymmetrical triggering through a diodei
when triggering signals are applied at the bases of the transistors. Here the negative pulse is applied
through D to the base of the ON stage. R is returned to ground rather than to the supply voltage.

If the trigger amplitude available is small, it may be necessary to amplify the signal before applying
it to the flip-flop. In this case a diode need not be used because the amplifier can provide the
unilateral action previously supplied by the diode.

Figure 4.24 Unsymmetrical triggering at collectors

Figure 4.25 Unsymmetrical triggering at bases

 93

TRIGGERING SYMMETRICALLY THROUGH A UNILATERAL DEVICE

Figure 4.26(a) shows an arrangement for symmetrical triggering through diodes at the collectors of
the transistors. If Q2 is ON and Qj is OFF in one of the stable states, the collector of Q2 is at
Vcfi(sat) and the collector of Q[ is at VCc- Therefore, D2 is reverse biased by Vcc and D] is at zero
bias. Hence a negative input signal will be transmitted through D] to the collector of Qi and thus to
the base of the ON stage Q2 via the R\C\ combination connecting the output of Qi to the input of Q2.
This negative pulse at the base of Q2 which is ON, turns it to OFF state thus causing a transition.
After the transition is completed, D( will be reverse biased and D2 will be at zero bias. So the next
negative pulse will pass through D2 instead of through Dj. Hence these diodes are called steering
diodes. The binary will transfer at each successive negative input pulse or step but will not respond to
the triggers of opposite polarity. The diode D3 serves the purpose of R in unsymmetrical triggering.
If p-n-p transistors are used, then the diodes must be reversed and a positive triggering signal would
be required. Figure 4.26(b) shows the arrangement of symmetrical triggering through the diodes at
the bases of the transistors. Triggering may also be done symmetrically without the use of the
auxiliary diodes. The presence of commutating capacitors facilitates this, but for this, the
commutating capacitors

Figure 4.26 Symmetrical triggering through diodes (a) at the collectors iind (b) at the bases.
 94

must be large, and large values of commutating capacitors lengthen the settling time of the binary.
Therefore this method of triggering without the auxiliary steering diodes is not employed where the
shortest possible resolution time is required. Figure 4.27 shows the arrangement for triggering a self-
biased bistable multivibrator without steering diodes. Here a positive step is applied at the common
emitters of the flip-flop.

Figure 4.27 Symmetrical triggering of a self-biased binary

A DIRECT-CONNECTED BINARY

Figure 4.28 shows a direct-connected binary. No coupling elements are used and the collector of
each transistor is connected to the base 6f the other transistor directly by a wire. In one stable state,
transistor Qi is in saturation and Q2 is conducting slightly, and in the other stable state, Q2 is in
saturation and Q! is conducting slightly
 95

Initially if we assume that Q] is ON, since its emitter is grounded and since its base and collector are
connected to Vcc through a resistor Rc, then

and hence Q] is driven heavily into saturation. So for a Ge transistor, VCE1 = 0.05 V and VBEi = 0.3
V. Because of the direct connection between the collector of Qi and the base of Qi> ^BEZ - ^CEI =
0-05 V; a small positive value. So Q2 is not OFF and it will be conducting slightly. The output swing
= VCE2 - VCE1 = VBE»,- VCEi = 0.3 - 0.05 = 0.25 V, Even though it has some advantages, there
are many serious disadvantages too, and so this circuit is not used these days. It was available in 1C
form as DCTL earlier, The advantages of direct connected binary are: \. Its extreme simplicity 2.
Only one supply voltage of low value about 1.5 V is required. 3. Low power dissipation 4.
Transistors with low breakdown voltages may be used. 5. The direct connected binary may be easily
constructed as an 1C because of the few elements involved. The disadvantages of direct connected
binary are: \. As temperature increases, the reverse saturation current /CBO may increase sufficiently
to bring Qt into active region and may even take Q2 out of saturation. 2. Since Q2 is driven heavily
into saturation, the storage time delay will be large and the switching speed will be low. 3. The
output voltages are equal to their saturation base and collector voltages, and these parameters may
vary appreciably from transistor to transistor. 4. The voltage swing is only a fraction of a volt and
hence the binary is susceptible to spurious voltages. 5. Since an OFF collector is tied directly to an
ON base, it is difficult to trigger the binary by the usual method of applying a pulse to the OFF
transistor. To supply sufficient current to take the ON transistor out of saturation, an amplifier trigger
circuit is usually required.

THE EMITTER-COUPLED BINARY (THE SCHMITT TRIGGER CIRCUIT)

Figure 4.29 shows the circuit diagram of an emitter-coupled bistable multivibrator using n-p-n
transistors. Quite commonly it is called Schmin trigger after the inventor of its vacuum-tube version.
It differs from the basic collector-coupled binary in that the coupling from the output of the second
stage to the input of the first stage is missing and the feedback is obtained now through a common
emitter resistor RE. It is a bistable circuit and the existence of only two stable states results from the
fact that positive feedback is incorporated into the circuit, and from the further fact that the loop gain
of the circuit is greater than unity. There are several ways to adjust the loop gain. One way of
adjusting the loop gain is.by varying /?C1. Suppose RC] is selected such that the loop gain is less
than unity. When flcl is small, regeneration is not possible.

For the circuit of Figure 4.29, under quiescent conditions Qi is OFF and Q2 is ON because it gets the
required base drive from VCc through RCi and /?j. So the output voltage
 96

is at its lower level. With Q2 conducting, there will be a voltage drop across RE -7B2)/?E> and this
will elevate the emitter of Q\. As the input v is increased from zero, the circuit will not respond until
Qi reaches the cut-in point (at v = Vt). Until then the output remains at its lower level. With Oj
conducting (for v > V|) the circuit will amplify because Q2 is already conducting and since the gain
Av</Av is positive, the output will rise in response to the rise in input. As v continues to rise, Ct and
hence B2 continue to fall and E2 continues to rise. Therefore a value of v will be reached at which
Qa is turned OFF. At this point v0 = VCc and the output remains constant at this value of Vcc, even
if the input is further increased. A plot of va versus v is shown in Figure 4.30(a) for loop gain < 1.

Suppose the loop gain is increased by increasing the resistance Rci. Such a change will have
negligible effect on the cut-in point V| of Qj. However in the region of amplification (i.e. for v > V{)
the amplifier gain Av</Av will increase and so the slope of the rising portion of the plot in Figure
4.30(a) will be steeper. This increase in slope with increase in loop gain continues until at a loop gain
of unity where the circuit has just become regenerative the slope will become infinite. And finally
when the loop gain becomes greater than unity, the- slope becomes negative and the plot of va versus
v assumes the S shape shown in Figure 4.30(b).
 97

Figure 4.30 Response of emitter-coupled binary for (a) loop gain < 1 and (b) loop gain > 1.
 98

The behavior of the circuit may be described by using this S curve. As v rises from zero voltage, v0
will remain at its lower level (= VCc ~ 'c2 ^ca) unt*l v reaches V\. (This value of v = V, at which the
transistor Qi just enters into conduction is called the upper triggering point, UTP.) As v exceeds V}
the output will make an abrupt .transition to its higher level (= Vcc). For v > Vh Qj is ON and Q2 is
OFF. Similarly if v is initially greater than V], then as v is decreased, the output will remain at its
upper level until v attains a definite level V2 at which point the circuit makes an abrupt transition to
its lower level. For v < ^2> Qi is OFF and Q2 is ON. (This value of v = V2 at which the transistor Q2
resumes conduction is called the lower triggering point, LTP.) This circuit exhibits hysteresis, that is,
to effect a transition in one direction we must first pass beyond the voltage at which the reverse
transition took place.

A vertical line drawn at v = V which lies between V2 and Vi intersects the S curve at three points a, b
and c. The upper and lower points a and c are points of stable equilibrium. The S curve is a plot of
values which satisfy Kirchhoff's laws and which are consistent with the transistor characteristics. At
v = V, the circuit will be at a or c, depending on the direction of approach of v towards V. When v =
V in the range between V2 and V|, the Schmitt circuit is in one of its two possible stable states and
hence is a bistable circuit.

Applications of Schmitt trigger circuit

Schmitt trigger is also a bistable multivibrator. Hence it can be used in applications where a normal
binary is used. However for applications where the circuit is to be triggered back-and-forth between
stable states, the normal binary is preferred because of its symmetry. Since the base of Q] is not
involved in regenerative switching, the Schmitt trigger is preferred for applications in which the
advantage of this free terminal can be taken. The resistance KC2 m me output circuit of Q2 is not
required for the operation of the binary. Hence this resistance may be selected over a wide range to
obtain different output signal amplitudes. A most important application of the Schmitt trigger is its
use as an amplitude comparator to mark the instant at which an arbitrary waveform attains a
particular reference level. As input v rises to Vi or falls to V2, the circuit makes a fast regenerative
transfer to its other state.

Another important application of the Schmitt trigger is as a squaring circuit. It can convert a sine
wave into a square wave. In fact, any slowly varying input waveform can be converted into a square
wave with faster leading and trailing edges as shown in Figure 4.31, if the input has large enough
excursions to carry the input beyond the limits of the hysteresis range, VH = V\ - V2
 99

In another important application, the Schmitt trigger circuit is triggered between its two stable states
by alternate positive and negative pulses. If the input is biased at a voltage V between V2 and V\ and
if a positive pulse of amplitude greater than V\ - V is coupled to the input, then Qj will conduct and
Q2 will be OFF. If now a negative pulse of amplitude larger than V - V2 is coupled to the input, the
circuit will be triggered back to the state where Qj is OFF and Q2 is ON.

Hysteresis
If the amplitude of the periodic input signal is large compared with the hysteresis range VH, then the
hysteresis of the Schmitt trigger is not a matter of concern. In some applications, a large hysteresis
range will not allow the circuit to function properly. Hysteresis may be eliminated by adjusting the
loop gain of the circuit to unity. Such an adjustment may be made in a number of ways:

(1) The loop gain may be increased or decreased by increasing or decreasing the resistance ^ci-

(2) The loop gain may be increased or decreased by adding a resistance /?E1 in series with the
emitter of Qi, or by adding a resistance 7?^ in series with the emitter of Q2 and then decreasing or
increasing REl and RE2. Since /?C1 and RE] are in series with Qi, these resistors will have no effect
on the circuit when Qi is OFF. Therefore, these resistors will not change V\ but may be used to move
V2 closer to or coincident with V\. Similarly, RE2 will affect V\ but not V2.

(3) The loop gain may also be varied by varying the ratio R[/(Ri + /?2). Such an adjustment will
change both V\ and V2.

(4) The loop gain may be increased by increasing the value of R$. If /?E1 or RE2 is larger than the
value required to give zero hysteresis, then the gain will be less than unity and the circuit will not
change state. So, usually RE\ or /?E2 is chosen so that a small amount of hysteresis remains in order
to ensure that the loop gain is greater than unity. Vi is independent of Rs but V2 depends on R$ and
increases with an increase in the value of Rs. So for a large value of Rs it is possible for V2 to be
equal to V\, Hysteresis is thus eliminated and the gain is unity. If Rs exceeds this critical value, the
loop gain falls below unity and the circuit cannot bs triggered. If Rs is too small, the speed of
operation of the circuit is reduced.

Derivation of expression for UTP

The upper triggering point UTP is defined as the input voltage Vl at which the transistor Qi just
enters into conduction. To calculate Vb we have to first find the current in Q2 when Q! just enters
into conduction. For this we have to find the Thevenin's equivalent voltage V’ and the Thevenin's
equivalent resistance Rb at the base of Q2, where

It is possible for Q2 to be in its active region or to be in saturation. Assuming that Q2 is in its active
region
 100

In the circuit shown in Figure 4.32, to calculate V\, we replace Vcc, KCI> ^i anc* ^2 of Figure 4.29
by V and RB at the base of Q2.

Writing KVL around the base loop of Q2,

Since VyJ is the voltage from base to emitter at cut-in where the loop gain just exceeds unity, it
differs from VBE2 in the active region by only 0.1 V for either Ge or Si
 101

This indicates that V, may be made almost independent of h^, of the emitter resistance RE, of the
temperature and of whether or not a silicon or germanium transistor is used. Hence the discriminator
level Vt is stable with transistor replacement, ageing, temperature changes, provided that (/IPE +
l)/?E » RB and that V" » 0.1. Since V depends on Vcc, RCI, R\ and R2, where stability is required it
is necessary that a stable supply and stable resistors are selected. Derivation of expression for LTP

The lower triggering point LTP is defined as the input voltage V2 at which the transistor Q2 resumes
conduction. Vi can be calculated from the circuit shown in Figure 4.33 which is obtained by
replacing Vcc, J?C1, RI and R2 of Figure 4.29 by Thevenin's equivalent voltage VTH and Thevenin's
equivalent resistance R at the collector of Q(, where

Figure 433 The equivalent circuit of Figure 4.29 when Q2 just resumes conduction.

The voltage ratio from the collector of Qi to the base of Q2 is Figure 4.33, the input signal to Qi is
decreasing, and when it reaches V2 then Q2 comes out of cut-off.,Writing KVL around the base
circuit of Q2,
 102

Since VBE| is higher for silicon than germanium, the LTP Va is a few tenths of a volt higher for a
Schmitt trigger using silicon transistors than for one using germanium transistors

MONOSTABLE MULTIVIBRATOR

As the name indicates, a monostable multivibrator has got only one permanent stable state, the other
state being quasi stable. Under quiescent conditions, the monostable multivibrator will be in its stable
state only. A triggering signal is required to induce a transition from the stable state to the quasi
stable state. Once triggered properly the circuit may remain in its quasi stable state for a time which
is very long compared with the time of transition between the states, and after that it will return to its
original state. No external triggering signal is required to induce this reverse transition. In a
monostable multivibrator one coupling element is a resistor and another coupling element is a
capacitor. When triggered, since the circuit returns to its original state by itself after a time T, it is
known as a one-shot, a single-step, or a univibrator. Since it generates a rectangular waveform which
can be used to gate other circuits, it is also called a gating circuit. Furthermore, since it generates a
fast transition at a predetermin6d time T after the input trigger, it is also referred to as a delay circuit.
The monostable multivibrator may be a collector-coupled one, or an emitter-coupled one.
 103

THE COLLECTOR COUPLED MONOSTABLE MULTIVIBRATOR

Figure 4.41 shows the circuit diagram of a collector-to-base coupled (simply called collector-
coupled) monostable multivibrator using n-p-n transistors. The collector of Q2 is coupled to the base
of Qi by a resistor R} (dc coupling) and the collector of Qt is coupled to the base of Q2 by a
capacitor C (ac coupling). Ci is the commutating capacitor introduced to increase the speed of
operation. The base of Qi is connected to -VBB through a resistor R2, to ensure that Q! is cut off
under quiescent conditions. The base of Q2 is connected to VCc through R to ensure that Q2 is ON
under quiescent conditions. In fact, R may be returned to even a small positive voltage but
connecting it to Vcc is advantageous. The circuit parameters are selected such that under quiescent
conditions, the monostable multivibrator finds itself in its permanent stable state with Q2ON (i.e. in
saturation) and Q! OFF (i.e. in cut-off)- The multivibrator may be induced to make a transition out of
its stable state by the application of a negative trigger at the base of Q2 or at the collector of Q|. Since
the triggering signal is applied to only one device and not to both the devices simultaneously,
unsymmetrical triggering is employed. When a negative signal is applied at the base of Q2 at t ~ 0,
due to regenerative action Q2 goes to OFF state and Qi goes to ON state. When Q, is ON, a current /i
flows through its Rc and hence its collector voltage drops suddenly by I\RC This drop will be
instantaneously transmitted through the coupling capacitor C to the base of Q2. So at t = 0+, the base
voltage of Q2 is

Figure 4.41 Circuit diagram of a collector-coupled monostable multivibrator

The circuit cannot remain in this state for a long time (it stays in this state only for a finite time T)
because when Qt conducts, the coupling capacitor C charges from Vcc through the conducting
transistor Qi and hence the potential at the base of Q2 rises exponentially with a time constant
 104

where R0 is the conducting transistor output impedance including the resistance Rc. When it passes
the cut-in voltage Vy of Q2 (at a time t = T), a regenerative action takes place turning Q| OFF and
eventually returning the multivibrator to its initial stable state. The transition from the stable state to
the quasi-stable state takes place at t = 0, and the reverse transition from the quasi-stable state to the
stable state takes place at t = T. The time T for which the circuit is in its quasi-stable state is also
referred to as the delay time, and also as the gate width, pulse width, or pulse duration. The delay
time may be varied by varying the time constant t(= RC).

Expression for the gate width T of a monostable multivibrator neglecting the reverse saturation
current /CBO

Figure 4.42(a) shows the waveform at the base of transistor Q2 of the monostable multivibrator
shown in Figure 4.41. For t < 0, Q2 is ON and so vB2 = VBE(sat). At t = 0, a negative signal applied
brings Q2 to OFF state and Q[ into saturation. A current /| flows through Rc of Qt and hence vci
drops abruptly by /|7?c volts and so vB2 also drops by I\RC instantaneously. So at t - 0, vB2 =
VBE(sat) - I}RC. For t > 0, the capacitor charges with a time constant RC, and hence the base
voltage of Q2 rises exponentially towards VCc with the same time constant. At t = T, when this base
voltage rises to the cut-in voltage level Vy of the transistor, Q2 goes to ON state, and Qj to OFF state
and the pulse ends

In the interval 0 < t < 7", the base voltage of Q2, i.e. vB2 is given by

Figure 4.42(a) Voltage variation at the base of Q2 during the quasi-stable state.
 105

Normally for a transistor, at room temperature, the cut-in voltage is the average of the
saturation junction voltages for either Ge or Si transistors, i.e

Neglecting the second term in the expression for T

but for a transistor in saturation Ra « R. Gate width, T = 0.693KC The larger the Vcc is, compared to
the saturation junction voltages, the more accura the result is. The gate width can be made very stable
(almost independent of transistor characteristic supply voltages, and resistance values) if Ql is driven
into saturation during the quasi-stab state

Expression for the gate width of a monostable multivibrator considering the reverse saturation
current ICBO

In the derivation of the expression for gate width T above, we neglected the effect of tt reverse
saturation current ICBO on the gate width T. In fact, as the temperature increases, the reverse
saturation current increases and the gate width decreases.
 106

In the quasi-stable state when Q2 is OFF, /CBO flows out of its base through R to th supply Vcc.
Hence the base of Q2 will be not at Vcc but at Vcc + ICBO^> ^ C *s disconnect from the junction of
the base of Q2 with the resistor R. It therefore appears that the capacitance C in effect charges
through R from a source Vcc + ICBO^- See Figure 4.42(b).

Figure 4.42(b) Voltage variation at the base of Q2 during the quasi stable state
 107

Neglecting the junction voltages and the cut-in voltage of the transistor

Since ICBO increases with temperature, we can conclude that the delay time T decreases as
temperature increases.

Waveforms of the collector-coupled monostable multivibrator The waveforms at the collectors and
bases of both the transistors Q] and Q2 of the monostable multivibrator of Figure 4.41 are shown in
Figure 4.44. The triggering signal is applied at t = 0, and the reverse transition occurs at t = T. The
stable state. For t < 0, the monostable circuit is in its stable state with Q2 ON and Q, OFF. Since Q2
is ON, the^ase voltage of Q2 is vB2 = VBE2(sat) and the collector voltage of Q2 is vC2 =
VCE2(sat). Since Q, is OFF, there is no current in Rc of Q! and its base voltage must be negative.
Hence the voltage at the collector of Q| is, vC1 = VCC and the voltage at the base of Q] using the
superposition theorem is

The quasi-stable state. A negative triggering signal applied at t = 0 brings Q2 to OFF state and Qi to
ON state. A current /, flows in tfc of Q]. So, the collector voltage of Qj drops suddenly by I}RC
volts. Since the voltage across the coupling capacitor C cannot change instantaneously, the voltage at
the base of Q2 also drops by /itfc, where I{RC = Vcc -VcE2(sat)- Since Qi is ON,
 108

In the interval 0 < t < T, the voltages VGI, VBI and Vc2 remain constant at their values at f = 0, but
the voltage at the base of. Q2, i.e. vB2 rises exponentially towards Vcc with a time constant, t - RC,
until at t = T, vB2 reaches the cut-in voltage Vx of the transistor. Waveforms for t > T. At / = 7*1",
reverse transition -takes place. Q2 conducts and Qi is cut-off. The collector voltage of Q2 and the
base voltage of Qi return to their voltage levels for / < 0. The voltage vclnow rises abruptly since Qt
is OFF. This increase in voltage is transmitted to the base of Q2 and drives Q2 heavily into
saturation. Hence an overshoot develops in vB2 at t = 7**", which decays as the capacitor recharges
because of the base current. The magnitude of the base current may be calculated as follows. Replace
the input circuit of Q2 by the base spreading resistance rBB in series with the voltage VsE(sat) as
shown in Figure 4.43. Let 7B be the base current at t = 1*. The current in R may be neglected
compared to I'B.

From Figure 4.43,

Figure 4.43 Equivalent circuit for calculating the overshoot at base 62 of Q3.

The jumps in voltages at B2 and C| are, respectively, given by

Since C] and B2 are connected by a capacitor C and since the voltage across the capacitts cannot
change instantaneously, these two discontinuous voltage changes 5 and 5' must bl equal.

Equating them,

vB2 and vcl decay to their steady-state values with a time constant
 109

Figure 4.44 Waveforms at the collectors and bases of the collector-coupled monostable multivibrator.
(a) at the base of Q2, (b) at the collector of Qt, (c) at the collector of Q2, and (d) at the base

Mono-stable multi-vibrator as a voltage-to-time converter (as a pulse width modulator) Figure

4.45(a) shows the circuit diagram of a mono-stable multi-vibrator as a voltage- to-time converter. By
varying the auxiliary supply voltage V, the pulse width can be changed. It can be seen that the
resistor R is connected to the auxiliary voltage source V instead of to the collector resistance of a
Transistor.The waveform of the voltage vB2 at the base of Q2 is shown in Figure 4.45(b).
 110

Figure 4.45 Mono-stable multi-vibrator as voltage to time converter

Thus the pulse width is a function of auxiliary voltage V. For this reason the mono-stable multi-
vibrator shown in Figure 4 .45 (a) is termed a voltdge-to-time converter. It is also called a pulse
width modulator
 111

THE EMITTER-COUPLED MONOSTABLE MULTIVIBRATOR

Figure 4.51 shows the circuit diagram of an emitter-coupled mono-stable multi-vibrator. It differs
from the collector-coupled one-shot in that the collector of Q2 is not coupled to the base of Q] and
instead the feedback has been provided through a common emitter resistance R& Also, there is no
need for a negative power supply. Since the signal at C2 is not directly involved in the regenerative
loop, this collector makes an ideal point from which to obtain an output voltage waveform. Since the
base of Qj is not connected to any other point in the circuit, it makes a good point at which to inject a
triggering signal. Hence the trigger source cannot load the circuit. The gate width of a one-shot can
be controlled through /,. In the case of collector-coupled one-shot it is not possible to stabilize 7j, but
in an emitter-coupled one-shot, the presence of the emitter resistance RE serves to stabilize /]. The
current l\ may be adjusted through the bias voltage V, and T varies linearly with V. Hence an emitter-
coupled configuration makes an excellent gate wave generator whose width is easily and linearly
controllable by means of an electrical signal

Figure 4.51 An emitter-coupled mono-stable multi-vibrator

 112

The waveforms of the emitter-coupled mono-stable multi-vibrator are shown in Figure 4.52.

Figure 4.52 Waveforms of emitter-coupled mono-stable multi-vibrator

In the stable state, Q2 is ON because it gets the required base drive from Vcc through R and develops
a potential VEN across the resistor RE. The biasing resistors R] and R2 are selected such that VBi is
smaller than VEN to ensure that Ch is OFF. This is the stable state. When a positive going triggering
pulse is applied at the base of Q,, the circuit goes into the quasi-stable state because VB1 > VEN2.
When Q[ goes ON its collector potential drops, consequently a negative step is applied to the base of
Q2 turning Q2 OFF. Due to conduction of Ch, a voltage drop VEN| is developed across KE. In the
quasi-stable state, VBI > VENI and Q! is ON and Q2 is OFF. However when Q, is ON, the capacitor
C charges from Vcc through R. When the potential VBN2 reaches the value of VEN, + Vr the
transistor Q2 conducts and due to regenerative feedback Q2 goes into saturation and Q! into cut-off
and the pulse ends
 113

Expression for gate width

When Q2 is ON, voltage across RE = VEN2. Hence

When Q| conducts, the voltage at the collector of Qj and hence the voltage at the base of Q2 drops by
IcRc\- Therefore,

If Q2 did not conduct, then as t —» «, VBN2 would approach VCc- Hence the instantaneous voltage
at the base of Q2 is given by

TRIGGERING THE MONOSTABLE MULTIVIBRATOR

A monostable multivibrator needs to be triggered by a suitable signal in order to switch it from the
stable state to the quasi stable state. However after remaining in the quasi stable state for a time T =
0.693 RC, it automatically switches back to the original stable state, without any triggering signal
applied. Thus unlike a bistable multivibrator, a monostable multivibrator requires only one triggering
signal. Hence only unsymmetrical triggering techniques are adopted for monostable multivibrators.
Generally speaking, all the triggering methods which are applicable to the binary are also applicable
to the monostable multivibrator. The collector-coupled monostable multivibrator is normally
triggered by applying a negative pulse at the collector of the OFF transistor (n-p-n) Qi through an RC
differentiator circuit which converts it into positive and negative spikes as shown in Figure 4.50. The
positive spike is blocked by the diode and the negative spike is transmitted through it and the
capacitor C to the base of the ON transistor Q2. So Q2 goes to the OFF state and Qi to the ON state.
This method has two advantages: one is as we know; the multi-vibrator is more sensitive to a pulse of
such a polarity which brings the ON device to the OFF state. The second is, at the instant of the
transition, the collector of Qi drops, the diode no longer conducts, and the multivibrator does not
respond to the triggering signal till the quasi-stable state is completed. The emitter-coupled mono-
stable multivi-brator may be triggered by applying a positive pulse of sufficient amplitude at the base
of Qt to bring the OFF transistor Q! to the ON state as shown in Figure 4.51.
 114

ASTABLE MULTIVIBRATOR
As the name indicates an astable multi-vibrator is a multi-vibrator with no permanent stable state.
Both of its states are quasi stable only. It cannot remain in any one of its states indefinitely and keeps
on oscillating between its two quasi stable states the moment it is connected to the supply. It remains
in each of its two quasi stable states for only a short designed interval of time and then goes to the
other quasi stable state. No triggering signal is required. Both the coupling elements are capacitors
(ac coupling) and hence both the states are quasi stable. It is a free running multi-vibrator. It
generates square waves. It is used as a master oscillator. There are two types of astable multi-
vibrators: 1. Collector-coupled astable multi-vibrator 2. Emitter-coupled astable multi-vibrator

THE COLLECTOR-COUPLED ASTABLE MULTIVIBRATOR

Figure 4.53 shows the circuit diagram of a collector-coupled astable multi-vibrator using n-p-n
transistors. The collectors of both the transistors Qj and Q2 are connected to the baseof the other
transistors through the coupling capacitors Cs and C2. Since both are ac couplings, neither transistor
can remain permanently at cut-off. Instead, the circuit has two quasi-stable states, and it makes
periodic transitions between these states. Hence it is used as a master oscillator. No triggering signal
is required for this multivibrator. The component values are selected such that, the moment it is
connected to the supply, due to supply transients one transistor will go into saturation and the other
into cut-off, and also due to capacitive couplings it keeps on-oscillating between its two quasi stable
states. The waveforms at the bases and collectors for the astable multivibrator, are shown in Figure
4.54. Let us say at t = 0, Q2 goes to ON state and Q] to OFF state. So, for t < 0, Q2 was OFF and Qi
was ON. Hence for t < 0, vB2 is negative, vC2 = Vcc, VB! = VBE(sat) and vcj = VCE(sat). The
capacitor C2 charges from Vcc through R2 and vB2 rises exponentially towards Vcc. At t = 0, vB2
reaches the cut-in voltage Vy and Q2 conducts. As Q2 conducts, its collector voltage Vc2 drops by
/2/?c - ^cc ~ VcE(saO- This drop in vc2 is transmitted to the base of Qj through the coupling
capacitor C2 and hence vB1 also falls by /2/?c- Qi goes to OFF state. So, VB] = VBE(sat) - /2tfc, and
its collector voltage vcl rises towards VCc- This rise in vc] is coupled through the coupling capacitor
C2 to the base of Q2, causing an overshoot § in vB2 and the abrupt rise by the same amount 8 in
VCL as shown in Figure 4.51(c). Now since Q2 is ON, C\ charges from Vcc through Rlt and hence
VB] rises exponentially. At t = 7"], when VB! rises to VY, Qi conducts and due to regenerative
action Qi goes into saturation and Q2 to cut-off. Now, for t > T\, the coupling capacitor C2 charges
from Vcc through R2 and at / = 7", + 7"2, when vB2 rises to the cut-in voltage Vr, Q2 conducts and
due to regenerative feedback Q2 goes to ON state and Q| to OFF state. The cycle of events repeats
and the circuit keeps on oscillating between its two quasi-stable states. Hence the output is a square
wave. It is called a square wave generator or square wave oscillator or relaxation oscillator. It is a
free running
 115

Figure 4.53 A collector-coupled astable multivibrator

Expression for the frequency of oscillation of an astable multivibrato

On similar lines considering the waveform of Figure 4.54(b), we can show that the time T2 for
which Q2 is OFF and Q1 is ON is given by
 116

The frequency of oscillation is given by

If R = R2 = R1, and Cs = C2 = C, then TI = T2 = T/2

The frequency of oscillation may be varied over the range from cycles to mega cycles by varying
RC. It is also possible to vary the frequency electrically by connecting R\ and R2 to an auxiliary
voltage source V (the collector supply remains +VCC) and then varying this voltage V.

The astable multivibrator as a voltage-to-frequency converter

 117

Figure 4.55 shows the circuit diagram of an astable multivibrator used as a voltage-to-frequency
converter. The frequency can be varied by varying the magnitude of the auxiliary voltage source
V. Now the supply voltage is VCG only> but the voltage level to which the coupling capacitors
Q and C2 try to charge is not Vcc but V.

For 0 < t < TI, Qi is OFF and Q2 is ON. From the base waveform shown in Figure 4.56(a) the
voltage at the base of Qi is given by

Neglecting the junction voltages and the cut-in voltage of the transistor

Figure 4.55 The astable multivibrator as a voltage-to-frequency converter

 118

Figure 4.56 (a) Waveform at the base of Q, and (b) waveform at the base of Q2 for the circuit of
Figure 4.55.
 119

This shows that by varying V, the frequency / can be varied and hence this circuit acts as a
voltage-to-frequency converter.

The astable multivibrator with vertical edges

The collector-coupled astable multivibrator shown in Figure 4.53 produces the output waveforms
at the collectors of Qi and Q2 with rounded edges as shown in Figure 4.54. An astable
multivibrator which can generate collector waveforms with vertical edges can be obtained by the
addition of two diodes and two resistors as shown in Figure 4.57. If Q2 is driven OFF, its
collector voltage rises immediately to Vcc so that D2 is reverse biased and Qj goes into
saturation, The saturation base current of Qi passes through Ci and R^ rather than through RQ.
Since /B no longer passes through Kc, the collector waveform now has vertical edges as desired.

Figure 4.57 The astable multivibrator with vertical edges

The astable multivibrator which does not block

 120

For the astable multivibrator shown in Figure 4.53 if the supply voltage is increased slowly from
zero to its full value Vcc, both the transistors may go into saturation simultaneously and remain
in that state. This blocked condition does not occur if the voltage is applied suddenly. A circuit
which cannot block is shown in Figure 4.58.

Figure 4.58 The astable multivibrator which does not block

The gated astable multivibrator

Figure 4.59 shows the circuit diagram of a gated astable multivibrator. This is obtained by
adding a transistor Q3 in series with the emitter of Q| or Q2 of the collector-coupled astable
multivibrator. This gated astable multivibrator can start or stop oscillating at definite times
 121

The input v, to Q3 can assume one of two values. One level is chosen such that Q3 is OFF. With
Q3 OFF, Qj will be OFF, and Q2 will be ON and the circuit is quiescent, i.e. it does not oscillate.
The second binary level is chosen such that Q^ is driven into saturation. Hence, at any instant
(say t - 0) that this voltage is applied, Q, goes ON and Q2 is driven OFF. The circuit operates as
an astable multivibrator with waveforms which are essentially those in Figure 4.54 starting at t =
0.
 122

THE EMITTER-COUPLED ASTABLE MULTIVIBRATOR

An emitter-coupled astable multivibrator may be obtained by using three power supplies or a
single power supply.Figure 4.63 shows the circuit diagram of a free-running emitter coupled
multivibrator using n-p-n transistors. Figure 4.64 shows its waveforms. Three power supplies are
indicated for the sake of simplifying the analysis. A more practical circuit using a single supply
is indicated in Figure 4.65. Let us assume that the circuit operates in such a manner that Qi
switches between cut-off and saturation and Q2 switches between cut-off and its active region

Figure 4.63 The astable emitter-coupled multivibrator

 123

During the interval preceding t = t\, the capacitor C charges from a fixed voltage ^BB ~ V0
through the resistor RE2. All circuit voltages remain constant except vEN2, which falls
asymptotically towards zero. The transistor Q2 will begin to conduct when vEN2 falls to

Calculations at f = tf
When Q2 conducts, vEN2 and vEN1 rise. As vENi rises, Q] comes out of saturation and vCN1
(= vBN2) also increases, causing a further increase in the current in Q2. Because of this
regenerative action, Qi is driven OFF and Q2 is driven into its active region where its base-to-
emitter voltage is VBE2, its base current is /B2 and its collector current is /C2. From Figure 4.64,
we see that after transition, at t = rf.

At t\ there is an abrupt change Vp in vEN2.Because of the capacitive coupling between emitters

there must also be the same discontinuity VD in VENI. Hence,

Neglecting junction voltages and /B2^ci compared with VCCi

The period

The interval T\ when Q2 conducts and Qi is OFF ends at t = t2- The transistor Qt will turn ON
when the base-to-emitter voltage reaches the cut-in value Vy or when VENi reaches the voltage
 124

Since the base voltage of Qi is fixed, then to carry the transistor from the cut-in point to
saturation the emitter must drop. However this drop S is small, since S = Va~ Vr= 0.2 V.
Because the emitters are capacitively coupled there will be an identical jump S in vEN2, After /
= t2, in the interval T2, conditions are the same as they were for t < t\. Therefore, the cycle of
From Figure 4.64(a), we see that the voltage VENI starts at V\ at t = t\ and falls to *^BB - Vj,at f
= t2. Since this decay is exponential with a time constant #E|C and approacheszero
asymptotically,events described above is repeated and the circuit behaves as an astable
multivibrator.
 125

Assuming that the supply voltages are large compared with the junction voltages and assuming
also that

Subject to the same approximations, T2 is given by

If VCC| and VBB are arranged to be proportional to one another, then the frequency is
independent of the supply voltages.When QJ is OFF, its collector-to-ground voltage is
approximately VCC1 and equals the base-to-ground voltage of Q2. Since it is desired that Q2 be
in its active region, then VBN2 should be less than VCN2 or VCC[ < VCC2. Since Qj is to be
driven into saturation, then its base voltage may be almost as large as its collector supply voltage.
However, to avoid driving Q\ too deeply into saturation it is better to arrange that VBB < VCC1,
A circuit which uses a single supply and which satisfies the requirements that VBB be
proportional to Vca and that VBB < VCC1 < VCC2 is shown in Figure 4.65. Since C' is a bypass
capacitor intended to maintain VBB constant, it is not involved in the operation of the circuit.
We assume that /?! and RI are small enough so that the voltage VBB at the junction of R} and
R2 remains normally constant during the entire cycle of operations of the multivibrator. Using
Thevenin's theorem we see that the circuit of Figure 4.65 is of the same form as that of Figure
4.63 with VCc2 ~ ^cc a°d with

The advantages and disadvantages of the emitter-coupled astable multivibrator over the
collector-coupled astable multivibrator are given below:
 126

Advantages

1. It is inherently self-starting.

2. The collector of Q2 where the output is taken may be loaded heavily even capacitively.

3. The output is free of recovery transients. 4. Because it has an isolated input at the base of Qi,
synchronization is convenient. 5. Frequency adjustment is convenient because only one capacitor
is used.

Disadvantages

1. This circuit is more difficult to adjust for proper operating conditions. 2. This circuit cannot
be operated with T\ and T2 widely different.

3. This circuit uses more components than does the collector-coupled circuit
 127

5.VOLTAGE TIMEBASE GENERATORS

INTRODUCTION

A time-base generator is an electronic circuit which generates an output voltage or current

waveform, a portion of which varies linearly with time. Ideally the output waveform should be a
ramp. Time-base generators may be voltage time-base generators or current time-base
generators. A voltage time-base generator is one that provides an output voltage waveform, a
portion of which exhibits a linear variation with respect to time. A current time-base generator is
one that provides an output current waveform, a portion of which exhibits a linear variation with
respect to time. There are many important applications of time-base generators, such as in CROs,
television and radar displays, in precise time measurements, and in time modulation. The most
important application of a time-base generator is in CROs. To display the variation with respect
to time of an arbitrary waveform on the screen of an oscilloscope it is required to apply to one set
of deflecting plates a voltage which varies linearly with time. Since this waveform is used to
sweep the electron beam horizontally across the screen it is called the sweep voltage and the
time-base generators are called the sweep circuits

GENERAL FEATURES OF A TIME-BASE SIGNAL

Figure 5.1(a) shows the typical waveform of a time-base voltage. As seen the voltage starting
from some initial value increases linearly with time to a maximum value after which it returns
again to its initial value. The time during which the output increases is called the sweep time and
the time taken by the signal to return to its initial value is called the restoration time, the return
time, or the flyback time. In most cases the shape of the waveform during restoration time and
the restoration time itself are not of much consequence. However, in some cases a restoration
time which is very small compared with the sweep time is required. If the restoration time is
almost zero and the next linear voltage is initiated the moment the present one is terminated then
a saw-tooth waveform shown in Figure 5.1(b) is generated. The waveforms of the type shown in
Figures 5.1 (a) and (b) are generally called sweep waveforms even when they are used in
applications not involving the deflection of an electron beam. In fact, precisely linear sweep
signals are difficult to generate by time-base generators and moreover nominally linear sweep
signals may be distorted when transmitted through a couplingnetwork.
 128

Figure 5.1 (a) General sweep voltage and (b) saw-tooth voltage waveforms

The deviation from linearity is expressed in three most important ways:

1. The slope or sweep speed error, (es )

2. The displacement error,( ed)
3. The transmission error, (et)

The slope or sweep-speed error, (es)

An important requirement of a sweep is that it must increase linearly with time, i.e. the rate of
change of sweep voltage with time be constant. This deviation from linearity is defined as

The displacement error,( ed)

Another important criterion of linearity is the maximum difference between the actual sweep
voltage and the linear sweep which passes through the beginning and end points of the actual
sweep. The displacement error ed is defined as

As shown in Figure 5.2(a), vs is the actual sweep and v's is the linear sweep.

The transmission error, (et)

When a ramp signal is transmitted through a high-pass circuit, the output falls away from the
input as shown in Figure 5.2(b). This deviation is expressed as transmission error et, defined as
the difference between the input and the output divided by the input at the end of the sweep

et =(Vs’-Vs)/Vs’

where as shown in Figure 5.2(b), V's is the input and Vs is the output at the end of the sweep,
i.e.at t = Ts
 129

Figure 5.2 (a) Sweep for displacement error and (b) sweep for transmission error

If the deviation from linearity is small so that the sweep voltage may be approximated by the
sum of linear and quadratic terms in t, then the above three errors are related as

which implies that the sweep speed error is the more dominant one and the displacement error is
the least severe one.

METHODS OF GENERATING A TIME-BASE WAVEFORM In time-base circuits, sweep

linearity is achieved by one of the following methods.

1. Exponential charging. In this method a capacitor is charged from a supply voltage through a
resistor to a voltage which is small compared with the supply voltage.

2. Constant current charging. In this method a capacitor is charged linearly from a constant
current source. Since the charging current is constant the voltage across the capacitor increases
linearly.

3. The Miller circuit. In this method an operational integrator is used to convert an input step
voltage into a ramp waveform.

4. The Phantastron circuit. In this method a pulse input is converted into a ramp. This is a version
of the Miller circuit.

5. The bootstrap circuit. In this method a capacitor is charged linearly by a constant current
which is obtained by maintaining a constant voltage across a fixed resistor in series with the
capacitor.

6. Compensating networks. In this method a compensating circuit is introduced to improve the

linearity of the basic Miller and bootstrap time-base generators.
 130

7. An inductor circuit. In this method an RLC series circuit is used. Since an inductor does not
allow the current passing through it to change instantaneously, the current through the capacitor
more or less remains constant and hence a more linear sweep is obtained.

EXPONENTIAL SWEEP CIRCUIT

Figure 5.3(a) shows an exponential sweep circuit. The switch S is normally closed and is open at
t = 0. So for t > 0, the capacitor charges towards the supply voltage V with a time constant RC.
The voltage across the capacitor at any instant of time is given by After an
interval of time Ts when the sweep amplitude attains the value Vs, the switch again closes. The
resultant sweep waveform is shown in Figure 5.3(b)

Figure 5.3 (a) Charging a capacitor through a resistor from a fixed voltage and (b) the
resultant exponential waveform across the capacitor.

The relation between the three measures of linearity, namely the slope or sweep speed error es,
the displacement error ed, and the transmission error e, for an exponential sweep circuit is
derived below.

Slope or sweep speed error, es

We know that for an exponential sweep circuit of Figure 5.3(a),

Rate of change of output or slope is

 131

For small Ts, neglecting the second and higher order terms

Neglecting the second and higher order terms

So the smaller the sweep amplitude compared to the sweep voltage, the smaller will be the slope
error.

The transmission error, et,

From Figure 5.2(b),
 132

The displacement error, ed

From Figure 5.2(a), we can see that the maximum displacement between the actual sweep and
the linear sweep which passes through the beginning and end points of the actual sweep occurs at
t =T S / 2

The actual sweep vs is given by

 133

The displacement error ed is given by

 134

If a capacitor C is charged by a constant current /, then the voltage across C is ft/C. Hence the
rate of change of voltage with time is given by Sweep speed = I/C

UNIJUNCTION TRANSISTOR
As the name implies a UJT has only one p-n junction, unlike a BJT which has two p-n junctions.
It has a p-type emitter alloyed to a lightly doped n-type material as shown in Figure 5.4(a). There
are two bases: base B| and base B2, base B] being closer to the emitter than base B2. The p-n
junction is formed between the p-type emitter and n-type silicon slab. Originally this device was
named as double base diode but now it is commercially known as UJT.

The equivalent circuit of the UJT is shown in Figure 5.4(b). B] is the resistance between base B!
and the emitter, and it is basically a variable resistance, its value being dependent upon the
emitter current i'E. /?B2 is the resistance between base 62 and the emitter, and its value is fixed.

Figure 5.4 (a) Construction of UJT, (b) equivalent circuit of UJT, and (c) circuit when iE = 0

If IE = 0, due to the applied voltage VBB, a current i results as shown in Figure 5.4(c)

From the equivalent circuit, it is evident that the diode cannot conduct unless the emitter voltage
 135

where Vy is the cut-in voltage of the diode.

This value of emitter voltage which makes the diode conduct is termed peak voltage and is
denoted by VP.

It is obvious that if VE < VP, the UJT is OFF and if VE > VP, the UJT is ON.The symbol of
UJT is shown in Figure 5.5(a). The input characteristics of UJT (plot of VE versus /E) are shown
in Figure 5.5(b). The main application of UJT is in switching circuits wherein rapid discharge of
capacitors is very essential. UJT sweep circuit is called a relaxation oscillator.

SWEEP CIRCUIT USING UJT

Many devices are available to serve as the switch S. Figure 5.6(a) shows the exponential sweep
circuit in which the UJT serves the purpose of the switch. In fact, any current-controlled
negative-resistance device may be used to discharge the sweep capacitor.The supply voltage
VyY and the charging resistor R must be selected such that the load line intersects the input
characteristic in the negative-resistance region. Assume that the UJT is OFF. The capacitor C
charges from VYY through R. When it is charged to the peak value VP, the UJT turns ON and
the capacitor now discharges through the UJT. When the capacitor discharges to the valley
voltage Vv» tne UJT turns OFF, and again the capacitor starts charging and the cycle repeats.
The capacitor voltage appears as shown in Figure 5.6(b). The expression for the sweep time Ts
can be obtained as follows
 136

Figure 5.6 (a) UJT sweep circuit and (b) output waveform across the capacitor.
 137

SWEEP CIRCUIT USING A TRANSISTOR SWITCH

Figure 5.8(a) shows the circuit diagram of a sweep circuit using a transistor switch. The input
gating waveform v,- may be the output of a monostable circuit in which case we get a triggered
sweep circuit or it might be the output of an astable circuit in which case we get a free-running
sweep circuit. The input and output waveforms are shown in Figure 5.8(b).In the quiescent state,
i.e. for t < 0, the input is clamped near ground and hence the transistor gets enough base drive
from VYY through R' and therefore goes into saturation. Hence the output voltage is at its lowest
magnitude (= VCE(sat) = Vv). At t = 0, the input goes to its lower level and remains at that level
for t = Ts. So for 0 < t < Ts, the transistor remains cut-off, the capacitor charges through R
towards VYy with a time constant RC. At t = Ts, the output is at its peak value. At the end of
sweep time Ts, the capacitor discharges and its final value is Vv.
 138

A TRANSISTOR CONSTANT-CURRENT SWEEP

For a transistor in the common base configuration, except for very small values of collector-to-
base voltage, the collector current is very nearly constant when the emitter current is held
constant. This characteristic may be used to generate a quite linear sweep by causing a constant
current to flow through a capacitor connected in the collector circuit.

Figure 5.9(a) shows the circuit diagram of a transistor constant-current sweep circuit. In Figure
5.9(a), ifVEB is the emitter-to-base voltage, the emitter current is

The switch S is opened at t = 0. Assuming that VEB remains constant for t > 0, the collector
current will be a constant whose nominal value is

On applying KVL to the input mesh and KCL to the output node of Figure 5.9(b), we have
 139

At t - 0, vs = 0, the solution to these equations is given by

Expanding the exponential into a power series in t/T and retaining only the first term

If the capacitor current were to remain constant at this value, then

At t = Ts
 140

MILLER AND BOOTSTRAP TIME-BASE GENERATORS—BASIC PRINCIPLES

The linearity of the time-base waveforms may be improved by using circuits involving feedback.
Figure 5.10(a) shows the basic exponential sweep circuit in which S opens to form the sweep. A
linear sweep cannot be obtained from this circuit because as the capacitor charges, the charging
current decreases and hence the rate at which the capacitor charges, i.e. the slope of the output
waveform decreases. A perfectly linear output can be obtained if the initial charging current / =
VIR is maintained constant. This can be done by introducing an auxiliary variable generator v
whose generated voltage v is always equal to and opposite to the voltage across the capacitor as
shown in Figure 5.10(b). Two methods of simulating the fictitious generator are discussed below.

Figure 5.10 (a) The current decreases exponentially with time and (b) the current remains constant.

In the circuit of Figure 5.10(b) suppose the point Z is grounded as in Figure 5.11(a). A linear sweep will
appear between the point Y and ground and will increase in the negative direction. Let us now replace the
fictitious (imaginary) generator by an amplifier with output terminals YZ and input terminals XZ as
 141

shown in Figure 5.11(b). Since we have assumed that the generated voltage is always equal and opposite
to the voltage across the capacitor,

Figure 5.11 (a) Figure 5.10(b) with Z grounded and (b) Miller integrator circuit.
the voltage between X and Z is equal to zero. Hence the point X acts as a virtual ground.
Now for the amplifier, the input is zero volts and the output is a finite negative value. This can be
achieved by using an operational integrator with a gain of infinity. This is normally referred to as
the Miller integrator circuit or the Miller sweep.
Suppose that the point Y in Figure 5.10(b) is grounded and the output is taken at Z. A linear
sweep will appear between Z and ground and will increase in the positive direction. Let us now
replace the fictitious generator by an amplifier with input terminals XY and output terminals ZY
as shown in Figure 5.12. Since we have assumed that the generated voltage v at any instant is
equal to the voltage across the capacitor vc, then v0 must be equal to v,-, and the amplifier
voltage gain must be equal to unity. The circuit of Figure 5.12 is referred to as the Bootstrap
sweep circuit.

Figure 5.12 Bootstrap sweep circuit.

The Miller sweep

The Miller integrating circuit of Figure 5.11(b) is redrawn in Figure 5.13(a). A switch S at the
closing of which the sweep starts is included. The basic amplifier has been replaced at the input
 142

side by its input resistance and on the output side by its Thevenin's equivalent. R0 is the output
resistance of the amplifier and A its open circuit voltage gain. Figure 5.13(b) is obtained by
replacing V, R and tf, on the input side by a voltage source V in series with a resistance R' where

Neglecting the output resistance in the circuit of Figure 5.13{b), if the switch is closed at t = 0
and if the initial voltage across the capacitor is zero, then v0 (f = 0+) = 0, because at / = 0~, V; ~
0 and since the voltage across the capacitor cannot change instantaneously.

This indicates that the sweep starts from zero.

At t = ∞, the capacitor acts as an open-circuit for dc. So no current flows and therefore

Figure 5.13 (a) A Miller integrator with switch S, input resistance Rf and Thevenin's equivalent
on the output side and (b) Figure 5.13(a) with input replaced by Thevenin's equivalent.
This indicates that the output is exponential and the sweep is negative-going since A is a negative
number.
 143

where Vs is the sweep amplitude and V is the peak-to-peak value of the output

The deviation from linearity is times that of an RC circuit charging directly from a
source V.
If R0 is taken into account, the final value attained by v0 remains as before, AV = - \A\V. The
initial value however is slightly different.
To find v0 at t = 0+, writing the KVL around the mesh in Figure 5.13(b), assuming zero voltage
across the capacitor, we have

From the above equations, we find

Therefore, if R0 is taken into account, v0(t = 0+) is a small positive value and still it will be a
negative-going sweep with the same terminal value. Thus the negative-going ramp is preceded
by a small positive jump. Usually this jump is/small compared to the excursion AV', Hence,
improvement in linearity because of the increase in total excursion is negligible.
The bootstrap sweep
Figure 5.14 shows the bootstrap circuit of Figure 5.12. The switch S at the opening of which the
sweep starts is in parallel with the capacitor C. Here, /?,- is the input resistance, A is the open-
circuit voltage gain, and R0 is the output resistance of the amplifier.
 144

Figure 5.14 Bootstrap circuit of Figure 5.12 with switch S which opens at ( = 0, input resistance
Rf, and Thevenin's equivalent of the amplifier on the output side.
At t = 0~, the switch was closed and so vt - 0, Since the voltage across the capacitor cannot
change instantaneously, at t = 0* also, v(- = 0 and hence Av, = 0, and the circuit shown in Figure
5.15 results.

The output has the same value at t = 0 and hence there is no jump in the output voltage at t = 0.

Figure 5.15 Equivalent circuit of Figure 5.14 aU = 0.

At t = <*>, the capacitor acts as an open-circuit and the equivalent circuit shown in Figure 5.16
results.

Writing KVL in the circuit of Figure 5.16,

 145

Since A « 1, and if R0 is neglected, we get

Since R0 « /?, v0 at t = 0 can be neglected compared to the value of v0 at t - <». Then the total
excursion of the output is given by

and the slope error is.

This shows that the slope error is [1 - A + (R/Rj)] times the slope error that would result if the
capacitor is charged directly from V through a resistor.
Comparing the expressions for the slope error of Miller and bootstrap circuits, we can see that it
is more important to keep R/Rj small in the bootstrap circuit than in the Miller circuit. Therefore,
the Miller integrator has some advantage over the bootstrap circuit in that in the Miller circuit a
higher input impedance is less important.
THE TRANSISTOR MILLER TIME-BASE GENERATOR
Figure 5.17 shows the circuit diagram of a transistor Miller time-base generator. It consists of a
three-stage amplifier. To have better linearity, it is essential that a high input impedance
amplifier be used for the Miller integrator circuit. Hence the first stage of the amplifier of Figure
5.17 is an emitter follower. The second stage is a common-emitter amplifier and it provides the
necessary voltage amplification. The third stage (output stage) is also an emitter follower for two
reasons. First, because of its low output impedance R0 it can drive a load such as the horizontal
 146

amplifier. Second, because of its high input impedance it does not load the collector circuit of the
second stage and hence the gain of the second stage can be very high. The capacitor C placed
between the base of Qi and the emitter of Q3 is the timing capacitor. The sweep speed is changed
from range to range by switching R and C and may be varied continuously by varying VBB.

Under quiescent condition, the output of the Schmitt gate is at its lower level. So transistor Q4 is
ON. The emitter current of Q4 flows through RI and hence the emitter is at a negative potential.
Therefore the diode D conducts. The current through R flows through the diode D and the
transistor Q4. The capacitor C is bypassed and hence is prevented from charging. When a
triggering signal is applied, the output of the Schmitt gate goes to its higher level. So the base
voltage of Q4 rises and hence the transistor Q4 goes OFF. A current flows now from 10 V source
through RI. The positive voltage at the emitter of Q4 now makes the diode D reverse biased. At
this time the upper terminal of C is connected to the collector of Q4 which is in cut-off. The
capacitor gets charged from VBB and hence a run down sweep output is obtained at the emitter
of Q3. At the end of the sweep, the capacitor C discharges rapidly through D and Q4.
Considering the effect of the capacitance C\, the slope or sweep speed error is given by

THE TRANSISTOR BOOTSTRAP TIME-BASE GENERATOR

Figure 5.18 shows a transistor bootstrap time-base generator. The input to transistor Q] is the
gating waveform from a monostable multivibrator (it could be a repetitive waveform like a
square wave). Figure 5.19(a) shows the base voltage of Qj. Figure 5.19(b) shows the collector
 147

current waveform of Qj and Figure 5.19(c) shows the output voltage waveform at the emitter of
q2

Figure 5.18 A voltage time-base generator.

Quiescent conditions
Under quiescent conditions, i.e. before the application of the gating waveform at t - 0, Q| is in
saturation because it gets enough base drive from YCC through ^B- So the voltage across the
capacitor which is also the voltage at the collector of Qj and the base of Q2 is VCE (sat). Since
Q2 is conducting and acting as an emitter follower, the voltage at the emitter of Q2 which is also
the output voltage is less than this base voltage by VBE2,
is a small negative voltage (a few tenths of a volt negative). If we neglect this small voltage as
well as the small drop across the diode D, then the voltage across C\ as well as across R is Vcc-
Hence the current i> through R i§ Vcc/R- Since the quiescent output voltage at the emitter of Q2
is close to zero, the emitter current of Q2 is VEE/J?E. Hence the base current of Q2 is
iB2 = VEE / hFE RE
iR = iC1 + iB2
Since the base current of Q2, i.e. /B2 is very small compared with the collector current iC1 of Q1

For Qj to be really in saturation under quiescent condition, its base current ((Bi = VCC/RB) t be
at least equal to I'CI#*FE> i.e. VCC//IFE^. so that
 148

Formation of sweep
When the negative-going gating waveform is applied at t - 0, the transistor Q] is driven OFF. The
current /Ci now flows into the capacitor C and so the voltage across the capacitor rises according
to the equation

Assuming unity gain for the emitter follower,

Since the voltage across C\ is constant and equal to VGO when the sweep starts, the diode is
reverse biased and the current through R is supplied by the capacitor C\ .
The equation, v0 ~ Vcct/RC is valid only if the gate duration Tg is small enough so that the
calculated value of v0 does not exceed Vcc- From Figure 5.18 it can be seen that when v0
approaches VCG, the voltage VCE of Q2 approaches zero and the transistor Q2 goes into
saturation. Then it no longer acts as an emitter follower. Hence v0 (also vc) remains constant at
Vcc. The current Vcc/K through Ci and R now flows from base to emitter of Q2.
If the output v0 reaches the voltage Vcc m a time Ts < Tg, then Vcc = Vcc TS / RC or TS = RC

Figure 5.19 Voltage time-base generator of Figure 5.18: (a) the base voltage of Q1% (b) the
collector current of Qi, and (c) the output voltage at the emitter of Q2-
whereas if the sweep amplitude Vs is less than Vcc> then the maximum ramp voltage is given by
 149

Retrace interval
At t = Tg, when the gate terminates, the transistor Qi goes into conduction and a current r'Bi =
VCC/R-Q flows into the base of Qi. Hence a current/ci =/IFE*BI flows into the collector of Qj.
This current remains constant till the transistor goes into saturation. Since Q] is ON the capacitor
C discharges through Qi. Because of emitter follower action, when vc falls, v0 also falls by the
same amount and so the voltage across R remains constant at Vcc. The constant current iR =
Vcc/R also flows through Qi. Applying KVL at the collector of Qi and neglecting /B2,

Since the discharging current of C, i.e. IA is constant, the voltage across C and hence the output
voltage falls linearly to its initial value.
If the retrace time is Tr, then the charge lost by the capacitor = IA Tr

where Vs is the sweep amplitude. That is,

After C is discharged, the collector current is now supplied completely through R and becomes
established at the value V^c/R-
The retrace time can be reduced by choosing a small value of Rs. However if RR is reduced

greatly, then the collector current currentmay increase to the point where the
transistor dissipation may be excessive.
The recovery process

During the entire interval the capacitor C[ discharges at a constant rate because
the

Current through it has remained constant. So it would have lost a charge

Hence at the time T when the voltage across C and at the base of Q2 returns to its value for t< 0,
 150

the voltage across Ci is smaller than it was at the beginning of the sweep. The diode D starts
conducting at t - T, and the end of Ci, which is connected to D, returns to its initial voltage, i.e.
Vcc- Therefore,.the other terminal of Ci which is connected to the emitter of Ch is at a more
positive potential than it was at t = 0 and so Q2 goes to cut-off. So the capacitor Ci charges
through the resistor RE with a current,

The maximum recovery time T\ for C\ can be calculated as follows.

Charge lost by capacitor Ci in time T is

Charge gained by capacitor Ci in minimum recovery time T\ Is

This shows that T\ is independent of C\ and varies inversely with VEE. T\ can be reduced by
increasing VEE. However this modification will increase the quiescent current in Q2 and hence
its dissipation.
CURRENT TIME-BASE GENERATORS
We have mentioned earlier that a linear current time-base generator is one that provides an
output current waveform a portion of which exhibits a linear variation with respect to time. This
linearly varying current waveform can be generated by applying a linearly varying voltage
waveform generated by a voltage time-base generator, across a resistor. Alternatively, a linearly
varying current waveform can be generated by applying a constant voltage across an inductor.
Linearly varying currents are required for magnetic deflection applications.
A SIMPLE CURRENT SWEEP
Figure 5.26(a) shows a simple transistor current sweep circuit. Here the transistor is used as a
switch and the inductor L in series with the transistor is bridged across the supply voltage. Rd
represents the sum of the diode forward resistance and the damping resistance. The gating
waveform shown in Figure 5.26(b) applied to the base of the transistor is in two levels. These
levels are selected such that when the input, is at the lower level the transistor is cut-off and
when it is at the upper level the transistor Is in saturation. For t < 0, the input to the base is at its
lower level (negative). So the transistor is cut-off. Hence no currents flow in the transistor and iL
= 0 and VCE = Vcc- At f = 0, the gate signal goes to its upper level (positive). So the transistor
conducts and goes into saturation. Hence the collector voltage falls to vCE(sat) and the entire
supply voltage Vcc is applied across the inductor. So the current through the inductor
 151

increases linearly with time. This continues till t = Tg, at which time the gating signal comes to
its lower level and so the transistor will be cut-off. During the sweep interval Ts (i.e. from t = 0
to t = Tg), the diode D is reverse biased and hence it does not conduct. At t ~ Ts, when the
transistor is cut-off and no current flows through it, since the current through the inductor cannot
change instantaneously it flows through the diode and the diode conducts. Hence there will be a
voltage drop of lLRd across the resistance Rd. So at t = Tg, the potential at the collector terminal
rises abruptly to Vcc + fiftd* i-e- there is a voltage spike at the collector at t = Tg. The duration
of the spike depends on the inductance of Z-^but the amplitude of the spike does not. For t > Tg,
the inductor current decays exponentially to zero with a time constant T- LIRd. So the voltage at
the collector also decays exponentially and settles at Vcc under steady-state conditions. The
inductance L normally represents a physical yoke and its resistance RL may not be negligible. If
RCs represents the collector saturation resistance of the transistor, the current increases in
accordance with the equation

If the current increases linearly to a maximum value IL, the slope error is given by

The inductor current waveform and the waveform at the collector of the transistor are shown in
Figures 5.26(c) and 5.26(d) respectively. To maintain linearity, the voltage (RL + /?csXt across
the total circuit resistance must be kept small compared with the supply voltage Vcc.
A TRANSISTOR CURRENT TIME-BASE GENERATOR
Figure 5.30 shows the circuit diagram of a transistor current time-base generator. Transistor Q! is
a switch which serves the function of S in Figure 5.29. Transistor Qi gets enough base drive from
VCC1 through KB a°d hence is in saturation under quiescent conditions. At / = 0, when the
gating signal is applied it turns off Qi and a trapezoidal voltage waveform appears at the base of
Q2. Transistors Q2 and Q3 are connected as darlington pair to increase the input impedance so
that the trapezoidal waveform source is not loaded. Such loading would cause nonlinearity in the
ramp part of the trapezoid. The emitter resistor RE introduces negative current feedback into the
output stage and thereby improves the linearity with which the collector current responds to the
base voltage. For best linearity it is necessary to make the emitter resistance as large as possible.
RE is selected so that the voltage developed across it will be comparable to the supply voltage
152
 153

UNIT – VI
SYNCHRONIZATION & FREQUENCY DIVISION
---------------------------------------------------------------------------------------
SYNCHRONIZATION AND FREQUENCY DIVISION
Principles of Synchronization, Frequency division in sweep circuit, Astable relaxation circuits,
Monostable relaxation circuits, Synchronization of a sweep circuit with symmetrical signals,
Sine wave frequency division with a sweep circuit.
A pulse or digital system may involve several different basic waveform generators and the
system may require that all these generators be operated synchronously—in step with one
another, i.e. each one of them arrives at some reference point in the cycle at exactly the same
time. Two or more waveform generators are said to operate in synchronism if each one of them
arrives at some reference point in its cycle at the same time. Synchronization is the process of
making two or more waveform generators arrive at some reference point in the cycle at exactly
the same time. Synchronization may be on a one-to-one basis or with frequency division.
Synchronization is said to be on a one-to-one basis if all the generators operate at exactly the
same frequency and arrive at some reference point in the cycle exactly at the same time.
Synchronization is said to be with frequency division if the generators operate at different
frequencies which are integral multiples of each other but arrive at some reference point at the
same time. The two processes, i.e. (i) synchronization and (ii) synchronization with frequency
division are basically very nearly alike and no clear-cut distinction can be drawn between them.
Counting circuits are an example of frequency division.
PULSE SYNCHRONIZATION OF RELAXATION DEVICES
Relaxation circuits are circuits in which the timing interval is established through the gradual
charging of a capacitor, the timing interval being terminated by the sudden discharge (relaxation)
of a capacitor. The multivibrator, the sweep generator, the blocking oscillator which we have
discussed in earlier chapters are examples of relaxation circuits. All these circuits have in
common a timing interval and a relaxation (or recovery) interval and each exists in an astable or
monostable form. The mechanism of synchronization and frequency division is the same for all
these devices. In the monostable circuits the matter of synchronization is a trivial one. The
monostable circuit normally remains in its quiescent condition and a single cycle of operation is
initiated by the application of a triggering pulse. The only requirement is that the interval
between triggers should be larger than the timing interval and the recovery period should be
combined. Figure 6.1 shows an arrangement for pulse synchronization of a sweep generator
using UJT. In the absence of an external synch, signal, the capacitor stops charging when the
voltage vc reaches the peak or breakdown voltage VP of the negative-resistance device.
Thereafter, the capacitor discharges abruptly through the negative resistance device UJT. When
the capacitor voltage vc falls to the valley voltage Vy, the UJT goes OFF and the capacitor
begins to recharge. A negative pulse applied at the base B2 of the UJT will lower Vp. In fact, any
current-controlled negative-resistance device such as a silicon-controlled switch, thyristor, etc.
can be used in place of the UJT. In such a case, a positive pulse applied at the gate or base will
lower the breakdown voltage..
 154

Figure 6.2(a) shows the situation which results when synchronizing pulses are applied. The
effect of the synchronization pulse is to lower the peak or breakdown voltage Vp for the duration
of the pulse. A pulse train of regularly-spaced pulses is shown in Figure 6.2(a), starting at an
arbitrary time t = 0. The first several pulses have no influence on the sweep generator, because
the amplitude of the sweep at the occurrence of the pulse plus the amplitude of the pulse is less
than VP. Hence, the sweep generator runs unsynchronized. Eventually, however, the exact
moment at which the UJT goes ON is determined by the instant of occurrence of a pulse [at time
T in Figure 6.2(a)] as is also each succeeding beginning of the ON interval. From this point
onwards, the sweep generator runs synchronously with the pulses. For synchronization to result,
the time of occurrence of the pulse should be such that it can serve to terminate the cycle
prematurely. This requirement means that the interval between pulses Tpt must be less than the
natural period T0 of the generator. Figure 6.2(b) shows the case in which Tp > T0. Here
synchronization of each cycle does not occur. The pulses do serve to establish that four sweep
cycles shall occur during the course of three pulse periods, but synchronization of this type is
normally of no use. Figure 6.2(c) shows a case in which Tp < T0 as required, but
synchronization does not result because the pulse amplitude is too small. In fact, even if the
requirement Tp < T0 is met, synchronization cannot result unless the pulse amplitude is at least
large enough to bridge the gap between the quiescent breakdown voltage and the sweep voltage
vc.
 155

Figure 6.2 (a) Tp < T0: synchronization results, (b) Tp > TQ: no synchronization results and (c)
Tp < T0 but amplitude of synch pulse is small, hence no synchronization results.
FREQUENCY DIVISION IN THE SWEEP CIRCUIT
In Section 6.1 we saw that synchronization (1:1 division) occurs when Tp < TQ and the
amplitude of the pulse is sufficient to terminate each cycle prematurely. Even if Tp < T0, if the
pulse amplitude is too small, then each cycle may not get terminated. Figure 6.3 shows a case in
which the sweep cycles- are terminated only by alternate pulses marked "2". The pulses marked
"1" would be required to have an amplitude at least equal to Vl if they were to be effective. The
pulses marked "2" are effective because they occur closer to the time when the cycle would
terminate of its own accord. The sweep generator now acts as a divider, the division factor being
2, since exactly one sweep cycle occurs for every two synchronizing pulses. If Ts is the sweep
generator period after synchronization, TJTp = 2.
Observe that the amplitude V's of the sweep after synchronization is less than the
unsynchronized amplitude Vs.
Suppose Tp in Figure 6.3 is progressively decreased, eventually a point would be reached
where even the alternate pulses would be too small in amplitude to fire the switch device. At this
point, if 7"0 > 3Tp, division by a factor of 3 would result. If the condition T0 > 3Tp were not
met, then again there would be no synchronization. On the other hand, if the pulse is made large
enough, every (« + l)st pulse will be in a position to ensure synchronization before the nth pulse
loses control.

Figure 6.3 Frequency division by a factor of 2 in a sweep generator.

 156

The basic principle of synchronization and use for counting purposes of other relaxation devices
is same as the basic principle of synchronization of the sweep generator.
OTHER ASTABLE RELAXATION CIRCUITS
Blocking oscillator
Figure 6.4 shows the circuit diagram indicating the use of an ffC-controIled astable blocking
oscillator to obtain frequency division by 4. Positive synch triggers are introduced through a
separate transistor Q2. These positive triggers applied at the base of Q2, appear as negative
triggers at the common collector, and because of the polarity inversion of the transformer
windings they appear as positive triggers at the base of Qj. The waveform vj across the R\C{
combination of Figure 6.4 is shown in Figure 6.5(a).
During the interval tp the capacitor charges and the pulse is generated. At the end of the pulse (at
t = tp), V] = Vi, Qi goes OFF and the capacitor discharges through /?j, and so the voltage vj
decreases. In the absence of the synchronizing pulse, a new blocking oscillator pulse will form
when v\ falls to the level VBB - Vy. In Figure 6.5(a) the injected triggers are shown
superimposed on the level VBB - Vy The pulse number 4 occurs at this time and has sufficient
amplitude to cause a premature firing of the oscillator. The oscillator therefore fires at a moment
dictated by the occurrence of a trigger and is not permitted to terminate its cycle naturally.

Figure 6.4 Frequency division by an tfC-controlled astable blocking oscillator.

Figure 6.5 The waveform Vj across of Qi showing frequency division by 4.

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Astable multivibrator
The astable multivibrator shown in Figure 6.6 may be synchronized or used as a divider by
applying either positive or negative triggering pulses to either transistor or to both the transistors
simultaneously. These pulses may be applied to the collector, base, or emitter. If for example,
positive pulses are applied to Bt or C2 or negative pulses to E\, these triggers may produce
synchronization by establishing the exact instant at which Qj comes out of cut- off. If negative
pulses are applied to B2 or Q or positive pulses to E2, then when Q2 conducts, these pulses will
be amplified and inverted and appear as positive pulses at B]. Hence again the pulses may
establish the instant when Qt comes out of cut-off. The negative pulses will not be effective
unless they succeed in moving the transistor at least slightly into the active region. Therefore,
such negative pulses must be large enough in amplitude and be supplied from a low impedance
source to divert enough current from the base to draw the transistor out of saturation.

In Figures 6.7(a) and (b) are shown the waveforms for the case where positive pulses are applied
to one base, say BI- The division ratio is 6. The cycle would normally have terminated at t = T0,
when the base voltage reached the cut-in level Vy, as shown by the dashed extension of the base
waveform in Figure 6.7(a). The cycle is prematurely terminated at the sixth pulse since the
amplitude of the sixth pulse added to the base waveform Bj, at the time of the sixth pulse, raises
the base voltage above VT Observe that while the complete multi period has been synchronized,
the individual portions have not been synchronized. Thus T' in Figure 6.7(a) is the same as it
would be without synchronization because the waveform at B2 is unaltered by the application of
the synch pulses.
Figures 6.7(c) and (d) show the base waveforms for the case where negative pulses are applied to
both multi bases simultaneously. Here the division ratio is 5. Both timing portions of the multi
waveform are synchronized and are necessarily of unequal duration since the division ratio is an
odd number. The positive pulses superimposed on the exponential portions of the waveforms
result from the combination of the negative pulses applied directly and the inverted and
amplified (hence positive and larger) pulses received from the other transistor. A special
situation of interest is illustrated in Figure 6.8. Here positive pulses are being applied to BI
through a small capacitor from a low-impedance source. During the time when Q! is conducting,
the base draws current at each input pulse. At the end of the pulse the input capacitor discharges,
giving rise to a negative overshoot. Alternatively, we may say that during the conduction period
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of Qj, the pulse input time constant is small and the input pulse is quasi differentiated. The
negative overshoot is amplified and inverted by Q! arid appears a t Q2 as a positive overshoot,
which may then serve to mark the end of the cut-off period of Q2. Hence the net result is that
both portions of the multi cycle have been synchronized without the need for applying pulses to
both transistors simultaneously. Observe that one portion of the cycle is terminated at the leading
edge of a synch, pulse and the second portion is terminated at the trailing edge of another pulse.

Figure 6.7 (a) and (b) base waveforms for division by 6 through the application of positive
pulses to one base, (c) and (d) base waveforms for division by 5 through the application of
negative pulses to both bases.
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MONOSTABLE RELAXATION CIRCUITS AS DIVIDERS

Figure 6.9(a) shows the use of a monostable relaxation device, a monostable multivibrator for
frequency division. The input pulses may be applied at Bf or Cj depending on the polarity. A
coupling diode may be used to minimize the reaction of the multivibrator on the pulse source.
The waveforms of Figure 6.9(b) show the voltage at BI and B2- Each fourth pulse causes a
transition of the multivibrator, the remaining pulses occurring at a time when they are
ineffective. Observe that while the total multivibrator cycle consisting of timing portion and
recovery period is synchronized, the two separate portions are not synchronized. If positive
pulses are applied, say, directly at B! through a small capacitance from a low impedance source,
the pulses are quasi differentiated during the conduction period of Qj. The negative overshoot is
amplified and inverted by Q[ and appears as positive overshoot at B2, and it may serve to
terminate the cycle prematurely as shown in Figure 6.9(c). In this case, the two portions of the
multivibrator waveform would be synchronized. Also, the counting ratio will change with
increasing amplitude of pulse input. If the overshoot is large enough, the exponential will be
terminated by the overshoot at-pulse 2 or pulse 1 and in
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Figure 6.9 (a) Monostable multivibrator for frequency division, (b) waveform at 62 with no
pulse overshoot and (c) waveform at B2 with pulse overshoot.
which case the counting ratio will become respectively 3 or 2. Finally, with a large overshoot,
the timing portion will terminate at the trailing edge of pulse 4, and the circuit will not operate as
a multivibrator at all.
PHASE DELAY AND PHASE JITTERS
The delay between the input pulse to a divider and the output pulse is referred to as phase delay.
It results from the finite rise time of the input trigger pulse and the finite response time of the
relaxation time devices. The phase delay may vary with time due to variations in device
characteristics, supply voltages, etc. Occasionally some extraneous signal may be coupled
unintentionally into the divider. Such a signal may have an influence on the exact moment at
which a basic waveform, say, reaches cut-off. In this case the phase delay may be subject to
periodic variations. All these factors which affect the phase delay give rise to what is termed
phase jitter. In large-scale counters consisting of many stages, the phase jitter is compounded. In
many applications, phase jitter is of no particular consequence but it constitutes an important
difficulty in connection with nanosecond pulses.
A method for achieving division without phase jitter is illustrated in Figure 6.10. The train of
regularly spaced input pulses (I) is applied to the divider input. The output of the divider consists
of the pulses (D). These latter pulses trigger a gating waveform generator, say, a monostable
multivibrator which provides a gate of duration Tg adequate to encompass each pulse labeled T.
This waveform is applied to a sampling gate which opens for a time Tg. The input pulse train is
sampled and the output waveform then consists of each pulse labeled T. The condition for proper
transmission is Tp < Tg < 2Tp, i.e. it is enough if Tg
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is longer than the interval between the pulses Tp and shorter than the interval between the
alternate pulses.
SYNCHRONIZATION OF A SWEEP CIRCUIT WITH SYMMETRICAL SIGNALS
In the previous sections we discussed the phenomenon of synchronization only for the case of
pulse-type synchronizing signals. It was assumed that the synchronizing signal consists of a train
of waveforms with leading edges which rise abruptly. In this section we will consider the case in
which the voltage variation is gradual rather than abrupt. The mechanism of synchronization for
a gradually varying synch signal is very nearly identical for all types of relaxation oscillators. Let
us consider the synchronization of a ramp generator for illustration.
Sinusoidal synchronization signal
Consider the sweep generator of Figure 6.1, which uses a current-controlled negative-resistance
device, a UJT, as a switch. Let us assume for simplicity that as a result of the synchronization
signal, the breakdown voltage of the negative-resistance device varies sinusoidally. The polarity
and the precise waveform required of the synchronization signal for such sinusoidal variation
will depend on the particular negative-resistance device being employed. It is to be noted,
however, that the circuit behaviour to be described does not depend on the sinusoidal nature of
the breakdown voltage variation. The results depend only on the relatively gradual variation of
the breakdown voltage in contrast to the abrupt variation with pulse-type sync signals.
In Figure 6.11, the dashed voltage level VPO is the breakdown voltage of the negative-resistance
device in the absence of a synch signal and the solid curve Vp is the breakdown voltage in the
presence of the synchronization signal. The sync signal has a period T, and the natural period is
TQ. Consider that synchronization has been established with T = TQ.
Figure 6.11 The timing relationship
 162

Figure 6.11 The timing relationship that must exist between VP and the sweep voltage in a
synchronized sweep when T = T0.

Such synchronization requires that the period of the sweep shall not be changed in the sync
signal. Hence the voltages which mark the limits of the excursion of the sweep voltage must
remain unaltered. The sweep cycle must therefore continue to terminate at Vpo- This result, in
turn, means that the intersection of the sweep voltage with the waveform Vp must occur as
shown in Figure 6.11, at the time when VP crosses Vpo, at the points labeled O in the figure. It is
possible that the sweep will terminate at the points marked O' in the figure. In the case of pulse
synchronization, we noted that synchronism could result only if the synch signal period was
equal to or less than the natural period. This feature resulted from the fact that a pulse could
serve reliably only to terminate a timing cycle prematurely and not to lengthen it. In the case of
synchronization with symmetrical signals, however, synchronization is possible both when T <
TQ and when T > TQ. The timing relationship between the sweep voltage and the breakdown
voltage for both the cases is shown in Figure 6.12(a). The sweep voltage drawn as a solid line
has a natural period TQ > T. The sweep voltage meets the VP curve at a point below VPO and is
consequently prematurely terminated. The sweep voltage drawn as a dashed line has a natural
period T'Q < T. This sweep meets the VP curve at a point above VPQ and is consequently
lengthened. In each case the synchronized period Ts equals the period 7".

Figure 6.12 (a) Shows the timing of the sweep voltage with respect to Vp for a case in which T <
TQ = TO'(dashed line) and (b) pertains to the general case, T * T0.
 163

The general situation may be described by reference to Figure 6.12(b). When T = TQ, the sweep
is terminated at point O, leaving the period unaltered. When T > TQ, the sweep terminates at a
point such as X—between O and the positive maximum A. When T < TQ, the sweep terminates
at a point such as Y—between O and the negative maximum B. When the period T is such that
the sweep terminates either at the point A or B, the limits of synchronization have been reached
since at A the sweep period has been lengthened to the maximum extent possible whereas at B
the shortening is at maximum.
SINE WAVE FREQUENCY DIVISION WITH A SWEEP CIRCUIT
In Section 6.6, we discussed synchronization of a sweep generator using a symmetrical
(sinusoidal) signal. The operation of a sweep circuit as a divider is an extension of the process of
synchronization. Figure 6.13 shows the operation of the sweep circuit for frequency division.
The solid lines in the figure show the sweep and synchronizing waveforms for division by a
factor of 4. This case is one in which the natural period TO is slightly smaller than 47". The sync
signal changes the sweep period from T0 to Tf, where 7^ = 47. An increase in amplitude of the
sync signal can change the division (counting) ratio from 4 to 3 as shown by the dashed sweep
and synchronizing waveforms. A general observation that can be made with a sweep circuit as a
counter is that if the sweep terminates on the descending portion of the Vp curve and if as a
consequence the period T0 is lengthened or shortened to Ts, where Ts = nT, then the circuit will
operate stably as an n:\ counter.

Figure 6.13 Frequency division using a sweep circuit. Illustrating the change in frequency
division ratio with synch signal amplitude.

Earlier it was conveniently assumed that the range of synchronization (or counting) extends from
the point where the sweep intersects the VP curve at a maximum to the point where the
intersection is at a minimum of the VP curve. This normally holds only for small values of sync
voltage, but may not hold when the sync amplitude is comparable to the sweep amplitude. In
 164

Figure 6.13, we can observe that the sweep will never be able to terminate at a maximum of VP,
because to do so, it is required that the sweep must first cross the previous negative excursion of
the Vp waveform.
Figure 6.14 illustrates a case (dashed sweep) where the sync amplitude, in principle, is just large
enough to cause 1:1 synchronization. The actual sweep waveform, however, as shown consists of
alternate long and short sweeps. So, when a sweep is used in connection with a scope, it is
advisable always to use as small a sync signal as possible.

Figure 6.14 Illustrating a possible result of excessive amplitude of the sync signal in a sweep.
Sine wave synchronization may be compared with pulse synchronization as follows:
1. Even though for small sync signals, synchronization holds over a small range in the
neighbourhood of integral relations between T and T0 for both pulses and sine waves, pulse
synchronization persists for variation of T0 / T in only one direction, whereas sine-wave
synchronization persists for variation of T0 / T in either direction.
2. In both cases, the range of synchronization increases with the increasing sync signal
amplitude.
3. With pulses, for large sync signal amplitudes, synchronization holds for all values of T0/Tp >
1, whereas with sine waves, however, there is no guarantee that synchronization in a useful
fashion occurs for all values of T0 / T > 1.
comparison of the important characteristics of various IC logic families.

(i) CMOS inverter

(ii) Tristate logic
(i) CMOS Inverter: It is complementary MOSFET obtained by using P-channel MOSPET and n-
channel MOSFET simultaneously. The P and N channel are connected in series, their drains are
 165

connected together, output is taken from common drain point. Input is applied at common gate
terminal. CMOS is very fast and consumes less power.

Case 1. When input Vi = 0. The (Gate source) voltage of Q1 will be 0 volt, it will be off.
But Q2 will be ON; Hence output will be equal to +VDD or logic 1.

Case 2. When input Vi = 1, The (Gate source) voltage of Q2 will be 0 volt, it will be
OFF, But Q1 will be ON. Hence output will be connected to ground or logic 0.
In this way, CMOS function as an inverter.

(ii) Tri-state logic: When there are three states i.e. state 0, state 1 and high impendence i.e.
called Tri-state logic. High impedance is considered as state when no current pass through
circuit. Although in state 0 and state 1 circuit functions and current flows through it.
 Propagation delay is the average transition delay time for a pulse to propagate from input
to output of a switching circuit.
 Fan-in is the number of inputs to the gate which it can handle.
 Fan-out is the number of loads the output of a gate can drive without effecting its
operation.
 Power dissipation is the supply voltage required by the gate to operate with 50% duty
cycle at a given frequency
 RTL, DTL, DTL are the logic families which are now obsolete. TTL is the most
widely used logic family. TTL gates may be:
 Totem pole
 Open collector
 Tri-state .
 TTL is used in SSI and MSI Integrated circuits and is the fastest of all standard logic
families.
 Totem pole TTL has the advantage of high speed and low power dissipation but its
 disadvantage is that it cannot be wired ANDed because of current spikes generation.
 Tri-state has three states : .
 High
 Low
 High Impedance
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 ECL is the fastest of all logic families because its propagation delay is very small i.e. of
about 2 nsec.
 ECL can be wired ORed.
 MOS logic is the simplest to fabricate.
 MOS transistor can be connected as a resistor.
 MOSFET circuitry are normally constructed from NMOS devices because they are 3
times faster than PMOS devices.
 CMOS uses both P-MOS and N-MOS.
 CMOS needs less power as compared to ECL as they need maximum power.

 Both NMOS and PMOS are more economical than CMOS because of their greater
packing densities.
 Speed of CMOS gates increases with increase in VDD.
 CMOS has large fan-out because of its low output resistance.
schematic of RTL NOR gate and explain its operation.
Ans. RTL was the first to introduced. RTL NOR gate is as shown in fig.

Working:
Case I: When A = B = 0.
Both T1 and T2 transistors are in cut off state because the voltage is insufficient to drive the
transistors i.e. VBE < 0.6 V: Thus, output Y will be high, approximately equal to supply voltage
Vcc. As no current flows through Rc and drop across Rc is also zero.
Thus, Y = 1, when A = B = 0.
Case II : When A = 0 and B = 1 or A = 1 and B = 0.
The transistor whose input is high goes into saturation where as other will goes to off cut state.
This positive input to transistor increases the voltage drop across the collector resistor and
decreasing the positive output voltage.
Thus, Y = 0,when A= 0 and B = 1 or A = 1 and B = 0.
Case III : When A = B = 1. Both the transistors T1 and T2 goes into saturation and output
voltage is equal to saturation voltage.
Thus, Y = 0,when A = B = 1
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Truth Table

Which is the output of NOR gate.

DCTL NAND gate with the help of suitable circuit diagram.

Ans. DCTL NAND gate circuit diagram is as shown:

Working
Case I: When A = B = 0. Both transistors T1 and T2 goes to cut off state. As the voltage is not
sufficient to drive the transistor into saturation. Thus, the output voltage equal to Vcc.
When A = B = 0, output Y = 1
Case II: When A = 0 and B = 1 or A = 1 and, B = 0. The corresponding transistor goes to cut off
state and the output voltage equals to Vcc.
Thus, When A = 0 and B = 1 or A = 1 and B = 0, Output Y = 1.
Case III: When A = B = 1. Both transistors T1 and T2 goes into saturation state and output
voltage is insufficient to consider as ‘1’
Thus when A B = 1, output Y = 0.
Truth Table

Which is the output of NAND gate.

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Compare standard TTL, Low power TTL and high speed TTL logic families.

characteristics and specification of CMOS.

1 Power supply (VDD) = 3 — 15 Volts
2. Power dissipation (Pd) = 10 nW
3. Propagation delay (td) = 25 ns
4. Noise margine (NM) = 45% of VDD
5, Fan out (FO) = >50
Two input ECL NOR gate?
The circuit diagram of two input ECL NOR gate is as shown:

Working
Case I : When A = B = 0, the reference voltage of T3 is more forward biased then T1 and T2.
Thus, T3 is ON and T1, T2 remains OFF. The value of R1 is such-that the output of NOR gate is
high .i.e. ‘1’.
Case II: When A = 1 or B = 1 or A = B = 1, the corresponding transistors are ON, as they are
more forward biased that T3 and thus T3 is OFF. Which makes the NOR output to be low i.e.
‘0’.
This shows that the circuit works as a NOR gate.
TTL inverter

.
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Tristate TTL inverter utilizer the high-speed operation of totem-pole arrangement while
permitting outputs to be wired ANDed (connected together). It is called tristate TTL because it
allows three possible output stages. HIGH, LOW and High-Impedance. We know that transistor
T3 is ON when output is HIGH and T4 is ON when output is LOW. In the high impedance state
both transistors, transistor T3 and T4 in the totem pole arrangement are med OFF. As a result the
output is open or floating, it is neither LOW nor HIGH. The above fig. shows the simplified
tristate inverter. It has two inputs A and E. A is the normal logic input whereas E is an ENABLE
input. When ENABLE input is HIGH, the circuit works as a normal inverter. Because when E is
HIGH, the state-of the transistor T1 (either ON or OFF) depends on the logic input A and the
additional component diode is open circuited as cathode is at logic HIGH. When ENABLE input
is LOW, regardless of the state of logic input the base-emitter junction of T is forward biased and
as a result it turns ON. This shunts the current through R1 away from T2 making it OFF. As T2
is OFF, there is no sufficient drive for T4 conduct and hence T4 turns OFF. The LOW at
ENABLE input also forward biases diode D2, which shunt the current away from the base of T3,
making it OFF. In this way, when ENABLE output is LOW, both transistors are OFF and output
is at high impedance state.
ECL OR gate
ECL or gate : Emitter-coupled logic (ECL) is the fastest of all logic families and thus it is used
in applications where very high speed is essential. High speeds have become possible in ECL
because the transistors are used in difference amplifier configuration, in which they are never
driven into saturation and thereby the storage time is eliminated. Here, rather than switching the
transistors from ON to OFF and vice-versa, they are switched between cut-off and active regions.
Propagation delays of less than 1 ns per gate have become possible in ECL.
Basically, ECL is realized using difference amplifier in which the emitters of the two transistors
are connected and hence it referred to as emitter-coupled logic. A 3-input ECL gate is shown in
Fig. (A) which has three parts. The middle part is the difference amplifier which performs the
logic operation.
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Emitter followers are used for d.c. level shifting of the outputs, so that V (0) and V (1) are same
for the inputs and the outputs. Note that two output Y1 and Y2 are available in this circuit which
are complementary. Y1. corresponds to OR logic and Y2 to NOR logic and hence it is named as
an OR/NOR gate.
Additional transistors are used in parallel to T1 to get the required fan-in. There is a fundamental
difference between all other logic families (including MOS logic) and ECL as far as the supply
voltage is concerned. In ECL, the positive end of the supply is connected to ground in contrast to
other logic families in which negative end of the supply is grounded. This is done to minimize
the effect of noise induced in the power supply and protection of the gate from an accidental
short circuit developing between the output of a gate and ground. The voltage corresponding to
V (0) and V (1) are both negative due to positive end of the supply being connected to ground.
The symbol of an ECL OR/NOR gate is shown in Fig. (B)

Open collector TTL NAND gate and explain its operation

The circuit diagram of 2-input NAND gate open-collector TTL gate is as shown:

Working:
Case.1 : When A = 0,B = 0
When both inputs A and B are low, both functions of Q1 are forward biased and Q2 remains off.
So no current flows through R4 and Q3 is also off and its collector voltage is equal to Vcc i.e. Y
=1
Case2 : When A = 0, B = 1 and
Case 3: When A = 1, B = 0
When one input is high and. other is low, then one junction is forward biased so Q2 is off and Q3
is also off. So collector voltage is equal to Vcc i.e. Y = 1
Case 4: When A = 1, B = 1
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When both inputs are high, Q1 is turned off and Q2 turned ‘ON’ Q3 goes into saturation and
hence Y = 0. The open-collector output has main advantage that wired ANDing is possible in it.
TTL NAND gate
Two input TTL NAND gate-is given in fig. (1). In this transistor T3 and T4 form a totem pole.
Such type of configuration is called-as totem-pole output or active pull up output.

So, when A = 0 and B = 1 or (+5V). T1 conducts and T2 switch off. Since T2 is like an open
switch, no current flows through it. But the current flows through the resistor R2 and into the
base of transistor T3 to turn it ON. T4 remains OFF because there is no path through which it can
receive base current. The output current flows through resistor R4 and diode D1. Thus, we get
high’ output.
When both inputs are high i.e. A = B = 1 or (+ 5V), T2 is ON and it drives T4 turning it ON. It is
noted that the voltage at the base of T3 equals the sum of the base to emitter drop of T4 and

of T2.
The diode D1 does not allow base-emitter junction of T3 to be forward-biased and hence, T3
remains OFF when T4 is ON. Thus, we get low output.
It works as TTL NAND gate.
Totem pole NAND gate
In TTL Totem pole NAND gate, multiple emitter transistor as input is used. The no. of inputs
may be from 2 to 8 emitters. The circuit diagram is as shown
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Case 1:
When A = 0, B = 0
Now D1 and D2 both conduct, hence D3 will be off and make Q2 off. So its collector voltage
rises and make Q3 ‘ON’ and Q4 off; Hence output at Y = 1 (High)
Case 2 and Case 3:
If A = 0, B = 1 and A = 1, B=0
In both cases, the diode corresponding to low input will conduct and hence diode P3 will be OFF
making Q2 OFF. In a similar way its collector voltage rises Q3 ‘ON’ and Q4 ‘OFF’. Hence
output voltage Y = 1 (High).
Case 4: A = 1, B = 1
Both diodes D1 and D2 will be off. D3 will be ‘ON’ and Q2 will ‘ON’ making Q4 also ‘ON’.
But Q3 will be ‘OFF’. So output voltage Y = 0.
All the four cases shows that circuit operates as a NAND gate.
Totem pole can’t be Wired ANDed due to current spike problem. The transistors used in circuits
may get damaged over a period of time though not immediately. Sometimes voltage level rises
high than the allowable.