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What Is An HDL? (Verilog/VHDL) : I I I I I I

HDLs (Hardware Description Languages) like Verilog and VHDL were developed to describe, simulate, and design complex integrated circuits and hardware systems. HDLs allow designers to express hardware designs at different levels of abstraction from the algorithmic behavior down to the register-transfer level structure. Using HDLs improves designer productivity through logic synthesis, easy design exploration and changes, and leveraging of software design tools. Some key advantages of HDLs include expressing large designs, flexible modeling capabilities, reusability, documentation, and adherence to standards.

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Sergio Canchumani
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36 views11 pages

What Is An HDL? (Verilog/VHDL) : I I I I I I

HDLs (Hardware Description Languages) like Verilog and VHDL were developed to describe, simulate, and design complex integrated circuits and hardware systems. HDLs allow designers to express hardware designs at different levels of abstraction from the algorithmic behavior down to the register-transfer level structure. Using HDLs improves designer productivity through logic synthesis, easy design exploration and changes, and leveraging of software design tools. Some key advantages of HDLs include expressing large designs, flexible modeling capabilities, reusability, documentation, and adherence to standards.

Uploaded by

Sergio Canchumani
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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HDLs

I What is an HDL? (Verilog/VHDL)


I A Language to describe, simulate, and create hardware
I Cannot be used like typical languages (C and Java)
I Express the dimensions of timing and concurrency
I At RTL, describes a hardware structure, not an algorithm
I At behavioral level, describes behavior with no implied structure
I ”If you can’t draw it, don’t try to code it”
HDLs

I Why were HDLs developed?


I DOD VHSIC program extended integration and performance of ICs
I Very large, complex, high speed ICs were successfully fabricated
I Schematics were becoming unwieldy quickly
I The number of transistors and complexity exploded
I Needed a way to describe and simulate complex designs
I VHDL considered as an alternative to IC datasheets
VHDL, Verilog, System Verilog

I VHDL:
I more difficult to learn
I strongly typed
I widely used for FPGAs, military
I Verilog
I simpler to learn
I looks like C
I weakly typed
I 85% of ASIC designs use Verilog
I Once either is used, the other is learned quickly
I System Verilog is Verilog with lots of goodies added from VHDL
Logic Synthesis was a later thought (1985)

I Enabled enormous increases in productivity


I Time to market is critical to survival
I Only about 10 percent of Verilog/VHDL is synthesible
I Remainder is for testbenches, stimulus generation
What are the advantages of using HDLs

I Can express large, complex designs (>107 gates)


I Flexible modeling capabilities
I Description can include the very abstract to the very structural
I Can utilize top down or bottom up methodologies
I Complexity hiding by abstraction is natural
What are the advantages of using HDLs(cont.)

I Productivity!
I Logic Synthesis
I 10-20K gates/day/designer
I Design changes are fast and easily done (text vs. drawing)
I Leverage of SW design tools
I vi, source control, make files, Unix text tools
I Optimization of designs is easier
I Exploration of alternative designs can be done quickly
I Easy to trade off time and complexity (speed vs. area)
What are the advantages of using HDLs(cont.)

I Reusability
I Packages, libraries, designs all can be reusable
I Vendor and technology independence
I CMOS, ECL, GaAs, NEC, TI, TSMC,... same code
I Documentation
I Textual documentation is part of the code, not a separate document
I Standards
I There is no such thing as a schematic standard
I Strict standards promote clear and consistent delivery of design intent
What does Verilog HDL look like?

//-------------------------------------------------------------------
//This module creates an adder/accumulator
//-------------------------------------------------------------------

module adder(
input clk, //input clock
input reset_n, //reset async active low
input first_select, //on first data item use this
input rd_fifo, //enable for ff
input [7:0] data, //data in
output logic [11:0] acc_out //data out of accumulator
);

always_ff@(posedge clk, negedge reset_n)


if (!reset_n) acc_out <= 12’h000;
else
if (rd_fifo)
if (first_select) acc_out <= data;
else acc_out <= acc_out + data;
endmodule
What structure does that code infer?
What does that code synthesize to?
What can’t an HDL do?

I Can not make architectural tradeoffs for you, it can help however
I Does not relieve you of understanding digital design
I Guess what it is that you want something to do
I If you can’t draw the structure you are looking for, stop coding

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