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Thapar University, Patiala Department of Electronics and Communication Engineering

The document contains 5 questions about computer architecture topics such as the Von Neumann and Harvard architectures, CISC and RISC architectures, CPU cycles, clock rates, CPI, and analyzing instruction sequences. It asks the reader to differentiate between the Von Neumann and Harvard models, highlight differences between CISC and RISC, calculate CPU cycles and clock rates, compare machine performance, and analyze two instruction sequences to determine which is faster and their CPI.

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Anshu Jindal
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132 views1 page

Thapar University, Patiala Department of Electronics and Communication Engineering

The document contains 5 questions about computer architecture topics such as the Von Neumann and Harvard architectures, CISC and RISC architectures, CPU cycles, clock rates, CPI, and analyzing instruction sequences. It asks the reader to differentiate between the Von Neumann and Harvard models, highlight differences between CISC and RISC, calculate CPU cycles and clock rates, compare machine performance, and analyze two instruction sequences to determine which is faster and their CPI.

Uploaded by

Anshu Jindal
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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Thapar University, Patiala

Department of Electronics and Communication Engineering

Tutorial Sheet1 (Computer Architecture, UEC-510)

1. Differentiate between Von-Neumann Model andHarvard architecture.


2. Highlight the main differences between CISC and RISC architectures and Draw the
data flow for MUL M1, M2.Where M1 and M2 are memory locations(for both the
cases).

3. A program runs in 10 seconds on computer X with 2 GHz clock. What is the number
of CPU cycles on computer X? We want to design computer Y to run same program
in 6 second. But computer Y requires 10% more cycles to execute program. What is
the clock rate for computer?
4. Suppose we have two implementations of the same ISA (instruction set architecture).
For a given program
Machine A has a clock cycle time of 250 ps and a CPI of 2.0
Machine B has a clock cycle time of 500 ps and a CPI of 1.2
Which machine is faster for this program, and by how much?
5. A compiler designer is trying to decide between two code sequences for a particular
machine. Based on the hardware implementation, there are three different classes of
instructions: class A, class B, and class C, and they require one, two, and three cycles
per instruction, respectively. The first code sequence has 5 instructions: 2 of A, 1 of
B, and 2 of C The second sequence has 6 instructions: 4 of A, 1 of B, and 1 of C
Compute the CPU cycles for each sequence. Which sequence is faster? What is the
CPI for each sequence?

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