Battery Management System Reference Design

2016.04.02

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The Altera® Battery Management System (BMS) Reference Design demonstrates battery state of charge
(SOC) estimation in an FPGA-based real-time control platform that you can extend to include other BMS
functionality such as battery state-of-health monitoring and charge equalization (cell balancing). It uses a
dual extended Kalman filter (DEKF) algorithm to estimate SOC values for 96 cells, using a MAX® 10
development kit. The reference design’s system-in-the-loop simulation runs on the MATLAB Simulink
software.
A BMS is a critical component in high-value battery powered applications such as electric vehicles or
energy storage. A BMS maintains the health of all the cells in the battery pack to deliver the power needed
by the application. It also protects the cells from damage and maintains all the cells within the manufac‐
turer-recommended operating conditions to prolong the life of the battery pack.
You can use an FPGA as a flexible and powerful platform for a BMS, using its high I/O count for parallel
connections to many battery modules. An FPGA can accelerate processor-intensive calculations such as
state-of-charge estimation.

Related Information
Improving Battery Management System Performance and Cost with Altera FPGAs

BMS Reference Design Features

• DEKF algorithm for SOC estimation and parameter identification.
• SOC value estimation for 96 cells.
• Alternative hardware implementations of SOC calculations:
• Nios II processor with floating-point acceleration
• Nios II with floating-point acceleration and floating-point matrix processor
• Nios II processor and DEKF algorithm implemented in dedicated floating-point IP
• System-in-the-loop simulation runs a MATLAB Simulink model that communicates with FPGA
hardware using Altera system console API.
• Compares the results from the FPGA in real-time with the results from the Simulink calculations
• Nios II processor for scheduling and communicating with MATLAB through System Console.
• Nios II software runs on μC/OS-II real-time operating system.

BMS Reference Design Getting Started

BMS Reference Design Software Requirements on page 2

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 AN-762
2 BMS Reference Design Software Requirements 2016.04.02

BMS Reference Design Hardware Requirements on page 2

The reference design requires Altera MAX 10 FPGA development kit (rev C).
Downloading and Installing the BMS Reference Design on page 2
Setting Up the MAX 10 Development Board on page 5
Compiling the FPGA Hardware Design for the BMS Reference Design on page 5
You can compile your design or use the Altera-provided pre-compiled .sof and .pof from the /master_
image directory of your reference design
Compiling the Nios Software for the BMS Reference Design on page 6
You can either compile your design or use the Altera-provided pre-compiled .elf from the software/ bms_
soc_microc directory of your reference design.
Programming the BMS Reference Design Hardware onto the Device on page 6
Downloading the BMS Reference Design Nios II Software to the Device on page 7
MATLAB Simulink Top-Level Design for the BMS Reference Design on page 7
The reference design uses the Simulink model demo_top.slx, which calls setup_demo_top.m file to
initialize all parameters.
Running the BMS Reference Design in a System-in-the-Loop Simulation on page 12

BMS Reference Design Software Requirements

• The Altera Complete Design Suite version 15.0, which includes:
• The Quartus II software v15.0
• DSP Builder v15.0
• The Altera Nios II Embedded Design Suite (EDS) v15.0
• MATLAB R2015a

BMS Reference Design Hardware Requirements

The reference design requires Altera MAX 10 FPGA development kit (rev C).
Note: The reference design does not support the rev A or rev B board under default project settings,
because the pinout of the rev C board is different from the other two.

Downloading and Installing the BMS Reference Design

1. In the Altera Design Store, download the relevant reference design bms_soc_max10m50.par file for
the MAX10 development kit:
a. Select Design Examples, select 15.0 for the Quartus II version, then search for BMS.
To obtain further support on the reference design, contact your local Altera sales representative.
2. In the Quartus II software, click File > New Project Wizard .
3. Click Next.
4. Enter the path for project working directory and enter bms_soc_max10m50 for the project name.
5. Click Next.
6. Select Project Template.
7. Click Next.
8. Click Install the design templates.

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2016.04.02 Downloading and Installing the BMS Reference Design 3

9. Browse to select the bms_soc_max10m50.par file for the reference design and browse to the destina‐
tion directory where you want to install it.
Figure 1: Design Template Installation

10.Click OK on the design template installation message.

11.Select the BMS Reference design design example.

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4 Downloading and Installing the BMS Reference Design 2016.04.02

Figure 2: Design Template

12.Click Next.
13.Click Finish.
The Quartus II software expands the archive and sets up the project, which may take some time.

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2016.04.02 Setting Up the MAX 10 Development Board 5

Figure 3: Directory Structure

<path> - Installation directory

bms_soc_subsystem - Contains Qysy-generated IP files

ip - Contains source files for IP components
ekf_core - Kalman filter DSP IP core
matrix_processor - Matrix processor IP core

master_image - Contains pre-compiled FPGA image

matlab - Contains reference design Simulink top-level
software - Contains the Nios II software project
bms_soc_microc - Nios II software project and source code

bms_soc_max10m50.qpf - Quartus II project file

bms_soc_max10m50.qsf - Quartus II Project Settings File
bms_soc_max10m50.v - FPGA top-level Verilog HDL file
bms_soc_max10m50.qsys - Qsys system file

Related Information
Altera Design Store

Setting Up the MAX 10 Development Board

1. Connect the USB-Blaster II connector (J12) on the development board to your computer using a
USB cable.
2. Apply power to the development board.

Related Information
MAX 10 FPGA Development Kit User Guide
The FPGA development board provides a hardware platform for evaluating the performance and features
of the Altera MAX 10 device.

Compiling the FPGA Hardware Design for the BMS Reference Design
You can compile your design or use the Altera-provided pre-compiled .sof and .pof from the /master_
image directory of your reference design
1. Launch Quartus II software.
2. Open project bms_soc_max10m50.qpf.
3. Click Processing > Start Compilation.
Note: You may edit the reference design project in Qsys.

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6 Compiling the Nios Software for the BMS Reference Design 2016.04.02

Compiling the Nios Software for the BMS Reference Design

You can either compile your design or use the Altera-provided pre-compiled .elf from the software/ bms_
soc_microc directory of your reference design.
1. Start Nios II EDS by clickingStart > Altera > Nios II EDS > Nios II Software Build Tools
2. Specify the \software folder as the workspace by browsing to the reference design /software directory.
3. Click OK to create the workspace.
4. Import application and board support package (BSP) projects:
a. Click File > Import.
b. Expand General and click Existing Projects into Workspace.
c. Click Next.
d. Browse to \software\bms_soc_microc and click OK.
e. Click Finish.
f. Repeat steps a step 4.a. to e step 4.a. for bms_soc_microc_bsp.
5. Rebuild the BSP project:
a. Right click bms_soc_microc_bsp project
b. Point to Nios II
c. Click Generate BSP
6. Build the application project:
a. Right-click bms_soc_microc project
b. Click Build Project.
Note: On Windows operating systems, the first time you build, the project might take up to one hour.
7. Note: build and rebuild the project if you make any changes to the Qsys project.

Programming the BMS Reference Design Hardware onto the Device

1. In the Quartus II software, click Tools > Programmer.
2. In the Programmer pane, select USB-Blaster II under Hardware Setup and JTAG under Mode.
3. Click Auto Detect to detect devices.
4. Select any 10M50 device.
5. Right click 10M50 device, select Edit, and click Change file.
6. Select the output_files/<project_name>.sof or output_files/<project name>.pof and click Open.
7. Turn on Program/Configure.
8. Click Start.
Note: If you program using .sof file, reprogram the device after removing power from the board. If
you program using .pof file, on-chip flash keeps the image, and you do not need to program the
device after removing power from the board. It takes longer to program the device initially
using the .pof file.

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2016.04.02 Downloading the BMS Reference Design Nios II Software to the Device 7

Downloading the BMS Reference Design Nios II Software to the Device

1. Start Nios II EDS, by clicking Start > Altera > Nios II EDS > Nios II Command Shell
2. In the command shell, go to the software project folder by entering:cd <reference_design_path>/
software/bms_soc_microc
3. In the command shell, download the software by entering: nios2-download -r –g
bms_soc_microc.elf
When the downloadis successful, you see the following message in the terminal:

Using cable “USB-BlasterII on <computername> [USB-1]”, device 1, instance 0x00

Resetting and pausing target processor: OK
Initializing CPU cache <if present>
OK
Downloaded 65KB in 0.0s
Verified OK
Starting Processor at address 0x00000190

4. In the Nios II EDS, click Run > Run configurations... .

5. Double click Nios II Hardware to generate a new run configuration.
6. Click New_configuration.
7. On the Project tab select the bms_soc_microc project in Project name.
8. Turn on Enable browse for file system ELF file.
9. Browse to the software\ bms_soc_microc and select bms_soc_microc.elf.
10.On the Target Connection tab, click Refresh Connections.
The software finds the USB-Blaster cable.
11.Click Apply to save changes, optionally specifying a name for the new configuration.
12.Click Run to start the software.
13.Check that the terminal console display shows the message:

Start hardware interaction

MATLAB Simulink Top-Level Design for the BMS Reference Design

The reference design uses the Simulink model demo_top.slx, which calls setup_demo_top.m file to
initialize all parameters.

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8 MATLAB Simulink Top-Level Design for the BMS Reference Design 2016.04.02

Figure 4: Simulink Top-Level Design

The driving cycle block allows you to select the speed profile.
Figure 5: Driving Cycle

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2016.04.02 MATLAB Simulink Top-Level Design for the BMS Reference Design 9

The car model block allows you to select the car model parameters.
Figure 6: Car Model

The battery pack contains the battery model block, which allows you to select the battery parameters.

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10 MATLAB Simulink Top-Level Design for the BMS Reference Design 2016.04.02

Figure 7: Battery Model

The DEKF-FPGA block communicates with the FPGA. It sends input, including initial values, voltage and
current data, to the FPGA, and receives SOC estimation, and updated battery model parameters from the
FPGA. Three scope windows, including cell 1 and 2 information, and SOC value for the first 12 cells,
appear by default when you open the Simulink top level design. You can add more scopes in the floating
scope block.

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2016.04.02 MATLAB Simulink Top-Level Design for the BMS Reference Design 11

Figure 8: Cell Information

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12 Running the BMS Reference Design in a System-in-the-Loop Simulation 2016.04.02

Figure 9: SOC values for 12 Cells

Running the BMS Reference Design in a System-in-the-Loop Simulation

1. Start DSP Builder in MATLAB (see related links).
2. In MATLAB, change the working directory to <reference_design_path>\matlab\bms_soc_application
3. Open demo_top.slx
4. Check that you configured, programmed, and started to run the software on the MAX 10 FPGA.
5. In Simulink, click Play.

Related Information
Starting DSP Builder in MATLAB

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2016.04.02 BMS Reference Design Functional Description 13

BMS Reference Design Functional Description

Figure 10: Block Diagram

Note: The design only uses DDR3 SDRAM for Nios II processor storage. You can replace it with external
flash or another memory block.

MATLAB Simulink FPGA

Driving cycle Matrix Processor

Onchip memory
Car model (control registers,
measured current
and voltage,
estimated voltage
and SOC)

Battery model
System JTAG Avalon-
console Avalon DEKF IP MM Nios II
MATLAB bridge Interface processor
API
Equivalent algortihm Custom instruction
running in MATLAB floating-point core

Performance counter

Scope DDR3 controller

DDR3 SDRAM

BMS Reference Design Car Model

The car model computes the electric power at the battery’s terminals, so that the vehicle speed follows a
driving cycle. You can select from 11 standard driving cycles.
The Urban Dynamometer Driving Schedule (UDDS), the Highway Fuel Economy Test (HWFET) and the
Federal Test Procedure (FTP) are defined by the U.S. Environmental Protection Agency. The New
European Driving Cycle (NEDC), the Extra-Urban Driving Cycle (EUDC) and the Economic
Commission for Europe urban driving cycle (ECE R15) are maintained by the United Nations Economic
Commission for Europe (UNECE). The Common Artemis Driving Cycles consists of the Urban cycle
(ArtUrban), the Rural road cycle (ArtRoad) and the Motorway cycles (ArtMw130 and ArtMw150, with a
maximum speed of 130 and 150 km/h, respectively). The Worldwide harmonized Light vehicles Test
Procedures (WLTP) Class 3 is developed the following the guidelines of UNECE World Forum for

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14 BMS Reference Design Car Model 2016.04.02

Harmonization of Vehicle Regulations. The various cycles differ in the average speed and electric power
required from the traction battery.

Table 1: Driving Cycle Details

The duration, Distance and average speed of each cycle

Driving Cycle Duration (min) Distance (km) Average speed (km/h)
UDDS 23 12.0 31.5
HWFET 13 16.5 77.5
FTP 31 17.8 34.1
EUDC 7 6.5 58.6
NEDC 20 8.3 25.4
ECE R15 3 0.9 16.5
WLTP class 3 30 23.2 46.5
ArtUrban 17 4.9 17.6
ArtRoad 18 17.3 57.4
ArtMw130 18 28.7 96.8
ArtMw150 18 29.5 99.5

The reference design implements a dynamic model to simulate the behaviour of a car. You calculate the
mechanical power Pm as the sum of three contributions: one linked to the acceleration, one because of the
air resistance and another because of the rolling resistance:
Figure 11: Car Model Equation

1
P = Fv = ( Mv + ρ SC v2 + α Mg )v
m 2 air x R

where:
• M is the kerb weight
• S is the frontal area
• CX is the drag coefficient
• R is the rolling resistance
• ρair is the air density
• g is the gravity acceleration
• v is the speed.
You obtain the electric power Pe from Pm where:
• ηwheel is the efficiency from the battery to the wheels
• ηreg is the efficiency in the opposite direction, i.e., during the regenerative breaking.

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2016.04.02 BMS Reference Design Battery Model 15

To obtain the battery current, divide the electric power by the sum of the cell voltages calculated by the
battery model.

BMS Reference Design Battery Model

The battery model can simulate a number of series-connected cells.
The only input is the battery current, which is the same for all the series-connected cells. For the output, at
each time step, the model generates the arrays of the cell voltages Vi, SOC, and the current values of the
model parameters.
Figure 12: Battery cell equivalent circuit model

R0 Ri iL
Ci +
VRC
i

+
iL Qn SOC + Voc VM
- -
-

The left hand side models the cell capacity Qn and evaluates the SOC as the voltage across a linear
capacitor with a capacity equal to Qn (expressed in Coulomb) divided by 1V. The cell voltage vM is the
sum of the open-circuit voltage VOC and a dynamic term, which accounts for the internal Ohmic
resistance R0 and the double layer effect (VRC1 ) and diffusion (VRC2 ) of the Li-ion during charging and
discharging (two RC branches). The model parameters change with manufacturing variations, ageing and
operating conditions, such as temperature and state of charge. To model the temperature and SOC
dependences, the reference design stores the parameter values in two-dimensional LUTs. You see the
variability of the cell behaviour by setting the model parameters, temperature, and capacity of each cell
individually

BMS Reference Design DEKF Technique

In the DEKF technique, the reference design simultaneously executes two cooperating Kalman filters for
nonlinear systems: one for the state and the other for the parameters estimation.
Dual estimation, rather than joint estimation, with only one Kalman filter reduces the state matrix
dimensions and may improve the estimation robustness. Equation 2 describes the parameter evolution
that with the measurement equation 4 builds the first EKF. Equation 3 represents the state evolution that
combines to the measurement equation to form the second EKF.
Figure 13: Equation 2

p( k + 1) = p( k ) + χ ( k )

Figure 14: Equation 3

x(k + 1) = F ( x(k), i L (k), p(k)) + ξ (k)

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16 BMS Reference Design DEKF Technique 2016.04.02

Figure 15: Equation 4

vT (k) = G ( x(k ), i L (k), p (k)) + ψ (k )

Figure 16: Measurement Equation

vT (k) = G ( x(k ), i L (k), p (k)) + ψ (k )

The measurement equation is the same for both filters. In the above equations:
• k is the discrete time
• p is parameters vector
• x = [SOC; VRC1] is the battery state vector
• χ, ξ and ψ are the parameters, the state and measurement noise, with zero mean and covariance matrix
Σχ, Σξ and Σψ, respectively.
Figure 17: Circuit Equations

 T 
 SoCk   SoCk −1 − iLk 
xk = f ( SoCk , vRCk , iLk ) =  = Q
 r 
 vRCk  
T T
τ + R(1 − e τ )i 
− −
 RCk −1
v e 
Lk 

vTk = g ( SoCk , vRCk , iLk ) = OCV ( SoCk ) − R0iLk − vRCk

OCV ( SoC) = P1 SoC 7 + P2 SoC 6 + P3 SoC 5 + P4 SoC 4 + P5 SoC 3 + P6 SoC 2 + P7 SoC1 + P8

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2016.04.02 BMS Reference Design DEKF Technique 17

Figure 18: DEFK Matrix Equations

 SoCk 
xk = v 
 RCk 
 

 R0k 
 1 
qk =  
 τ 
 Rk 

1 0 
Ak =  − 
T
0 e τ 

 dOCV ( SoC) 
C xk =  − 1
 dSoC 

dxk−
Cqk = [− iLk 0 0] + C xk
dq

dxk− 1 0  dx+ 0
k−1 + 
0 0 
= −T  −T −T 
dq 0 e τ  dq 0 Te τ ( Ri − v ) (1 − e τ )i 
 Lk RCk−1 LK 

dxk+−1 dxk−
= − Lxk −1C qk −1
dq dq

Figure 19: Initialization Equation

x0 , P0 , q0 , Pq 0

Figure 20: Prediction Equations

q k− = q k+−1
Pq−k = Pq+k −1 + Q q
(
xk− = f xk+−1 , u k −1 , q k+−1 )
− +
Pk = Ak P k −1 AkT +Q

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18 BMS Reference Design Hardware Implementation 2016.04.02

Figure 21: Correction Equation

(
Lxk = Pk−C xTk C xk Pk−C xTk + R )
−1

( (
x+k = xk− + Lxk yk − g xk− , uk , qk+−1 ))
+ −
Pk = ( I − Lxk C xk ) Pk
(
Lq k = Pq−k CqTk Cq k Pq−k CqTk + R )−1

( (
q +k = qk− + Lq k yk − g xk− , uk , qk+−1 ))
Pq+k = ( I − Lq k Cq k ) Pq−k

Related Information
R. Morello et al., "Comparison of state and parameter estimators for electric vehicle batteries,"
Industrial Electronics Society, IECON 2015 - 41st Annual Conference of the IEEE, Yokohama, 2015,
pp. 005433-005438

BMS Reference Design Hardware Implementation

The reference design includes three different designs to implement the DEKF algorithm:
• Design A,which has a Nios II processor with floating-point acceleration
• Design B, which has a Nios II processor with floating-point acceleration and floating-point matrix
processor
• Design C, which has a Nios II processor and DEKF algorithm implemented in dedicated floating-point
IP
The reference design creates the dedicated floating-point IP using Altera’s DSP Builder advanced blockset.
In each design, every functional component takes charge of different tasks, including system-in-the-loop
communication with MATLAB Simulink, cell link list management, DEKF calculation. In the three
designs, the Nios processor II controls the system-in-the-loop and cell link tasks. In design B, both the
Nios II processor and matrix processor perform the DEKF calculation, and the matrix processor processes
most of the matrix calculations. Finally, in design C, DSP Builder IP processes all DEKF calculations.
To switch between different implementation methods, modify this line in source file

\software
\bms_soc_microc
\soc_kalman.h:
// 0 - Nios2 only
// 1 - Matrix processor
// 2 - DSP Builder IP
#define ACC 1

BMS Reference Design Matrix Processor

The matrix processor is a generic matrix processor that Altera developed using the DSP Builder advanced
blockset. It can perform sequences of different matrix operations.
You can select the maximum size of matrices to use to scale the usage of internal memory to fit the desired
application. The matrix processor includes two data processing cores: Faddeev and matrix multiply cores.

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2016.04.02 BMS Reference Design uCode Controller Interface 19

The Faddeev core can calculate the operation: D + C * A-1 * B. The matrix multiply core can calculate the
(A * B) and (A * B + C) matrix expressions.
Figure 22: Matrix Processor Block Diagram

Faddeev
Processor core
interface User
memory
Matrix
Multiply
Core

uCode
controller

The matrix processor interface is the main interface between the matrix processor and the external
environment. It programs the matrix processor for certain uCode, provides input matrix argumentss and
reads-back results.

BMS Reference Design uCode Controller Interface

The uCode controller interface configures and controls the matrix processor.
The reference design maps it to an address region in the processor interface. The address map may change
based on certain sizes and user -defined parameters of the design.

Table 2: Matrix Processor Control Registers Map

Name Address Bits Description

MAT_PROC_OPCODES‐ 0x320 [4:0] Line of opCode at which the matrix
TART processor starts uCode execution.
MAT_PROC_ 0x321 [4:0] Line of opCode at which the matrix
OPCODESTOP processor stops uCode execution.

MAT_PROC_READY 0x3B3 [0:0] Bit that indicates status of the matrix

processor. The host has to test this bit
before starting new uCode sequence or to
poll for current sequence completion
MAT_PROC_GO 0x3B4 [0:0] Bit asserted by host to initiate a uCode
sequence execution. Processor has to assert
the bit each time to start new execution.

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20 BMS Reference Design uCode Controller Interface 2016.04.02

Name Address Bits Description

MAT_PROC_ 0x3B5 [0:0] Use this bit to select the user memory
HOSTACCESS multiplex to obtain and release user
memory. Assert to obtain access from
processor. Deassert to release control to
matrix processor.

In addition, to control registers, the uCode interface has a page with a uCode program stored in internal
memory. To configure the matrix pProcessor with your uCode program, fill values into the uCode
memory. The depth of the uCode memory is a compile-time parameter.

Table 3: uCode Program Memory Map

Name Address Line 0 Bits Description

MAT_PROC_OPCODE 0x323 [3:0] opCode to execute.
MAT_PROC_N 0x333 [3:0] N size parameter of the opCode.
MAT_PROC_M 0x343 [3:0] M size parameter of the opCode.
MAT_PROC_W 0x353 [3:0] W size parameter of the opCode.
MAT_PROC_ARG1 0x363 [31:0] Arg1 parameter of the opCode
Bits [8:0] Argument1 offset
Bits[31:28] Argument 1 extension

MAT_PROC_ARG2 0x373 [31:0] Arg2 parameter of the opCode

Bits [8:0] Argument2 offset
Bits[31:28] Argument 4 extension

MAT_PROC_ARG3 0x383 [31:0] Arg3 parameter of the opCode

Bits [8:0] Argument3 offset
Bits[31:28] Argument 4 extension

MAT_PROC_ARG4 0x393 [31:0] Arg4 parameter of the opCode

Bits [8:0] Argument4 offset
Bits[31:28] Argument 4 extension

MAT_PROC_ARG5 0x3A3 [31:0] Arg5 parameter of the opCode

Bits [8:0] Argument5 offset

To configure the matrix processor to execute an algorithm, the CPU host must program it. To program,
fill data into the uCode program area and provide run-time configuration parameters.

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Table 4: Matrix Processor opCode Arguments

The uCode program structure has these fields that you must supply to the uCode controller. The fields are opCode
dependent. The matrix processor has three operation modes. .
Name Valid Entries Description
MAT_PROC_OPCODE 1, 3, 4 Operation mode:
1 – D + C * A-1 * B
3–A*B
4–A*B+C

MAT_PROC_N 2-MAX N size parameter of the opCode

MAX is compile time parameter

MAT_PROC_M 1-MAX M size parameter of the opCode

MAX is compile time parameter

MAT_PROC_W 1-MAX W size parameter of the opCode

MAX is compile time parameter

MAT_PROC_ARG1 – Matrix A XXX Arg1 to Arg4 parameter of the opCode

MAT_PROC_ARG2 – Matrix B Bits [8:0] Argument offset
MAT_PROC_ARG3 – Matrix C Bits[31:28] Argument extension
MAT_PROC_ARG4 – Matrix D [30:28] Valid when opCode = 1
0 – Normal (no data manipulation)
1 – Negate elements
2 – Zero elements Matrix
3 – Identity matrix
4 – Negative identity matrix
[31]
0 – Do not transpose matrix
1 – Transpose matrix

MAT_PROC_ARG5 XXX Result matrix

Arg5 parameter of the opCode
Bits [8:0] Argument5 offset

In the matrix processor solution, the reference design accelerates part of the matrix operation using the
matrix processor. Meanwhile, the Nios II processor can also be doing calculations.

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22 BMS Reference Design DEKF IP (Design C) 2016.04.02

Figure 23: Task Scheduling

The Nios II processor calculates the steps in the blue box. Then the matrix processor starts calculating the
equations in the red box. Meanwhile, the Nios II processor can process the steps in the green box. Finally,
the Nios II processor finishes the calculation in the yellow box.

BMS Reference Design DEKF IP (Design C)

The DEKF IP includes all calculations in the DEKF.
The Nios II processor only communicates with the host, sends inputs, and receives results. The reference
design includes the model file Ekf_Core.slx. A DSP Builder-generated direct implementation of the
algorithm in the FPGA fabric executes quickly but uses too many FPGA resources for a low-cost FPGA
device. However, the DSP Builder ALU folding automatically generates a design which reuses FPGA
logic.The ALU folder saves around 90% of the FPGA resources in this design.

BMS Reference Design FPGA Resource Usage

Use the resource usage to estimate the size of your design.

Table 5: Resource Usage

Component LE M9K DSP

DEKF IP (design C 20,610 30 29
only)

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2016.04.02 BMS Reference Design Benchmarking 23

Component LE M9K DSP

Matrix processor 6,304 35 24
(design B only)
Nios II processor 2,916 32 6
Nios II floating-point 2,204 3 9
custom instruction
core
DDR controller 4,785 12 0
Avalon-MM intercon‐ 5,897 0 0
nect
JTAG-Avalon-MM 799 1 0
bridge
Miscellaneous 1,292 23 0
Design A total ~14,000 57 15
Design B total ~24,000 92 39
Design C total ~33,000 84 35
Total ~45,000/50,000 136/182 68

BMS Reference Design Benchmarking

Table 6: Execution Time for Updating One Cell

Implementation Method Time to Update One Cell (μs)

Design A 44.9
Design B 33.8
Design C 16.5

Acknowledgements for the BMS Reference Design

Altera wants to acknowledge the help of Federico Baronti of the University of Pisa with the models and
algorithms used in this reference design.

Battery Management System Reference Design Altera Corporation

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