CHAPTER 5 APPENDIX

5.1 DESCRIPTION OF AT89c2051

TheAT89C2051 is low-voltage; high-performance CMOS 8-bit microcomputer
with2K bytes of Flash programmable and erasable read only memory (PEROM).
The device is manufactured using Atmel’s high-density nonvolatile memory
technology and is compatible with the industry- standard MCS-51 instruction set.
By combining versatile 8-bit CPU with Flash on a monolithic chip, the Atmel
AT89C2051 is a powerful microcomputer, which provides a highly flexible and cost-
effective solution to many embedded control applications.
The AT89C2051 provides the following standard features: 2K bytes of Flash,
128bytes of RAM, 15 I/O lines, two 16-bit timer/counters, a five vector two-level
interrupt architecture, a full duplex serial port, a precision analog comparator, on-
chip oscillator and clock circuitry. In addition, the AT89C2051 is designed with
static logic for operation down to zero frequency and supports two software
selectable power saving modes. The Idle Mode stops the CPU while allowing the
RAM, timer/counters, serial port and interrupt system to continue functioning. The
power-down mode saves the RAM contents but freezes the oscillator disabling all
other chip functions until the next hardware reset.

FIG :5.1 Pin Configuration of microcontroller AT89c2051

5.2 PIN DESCRIPTION:
VCC: Supply voltage

GND: Ground
pull-ups. P1.0 and P1.1 also serve as the positive input (AIN0) and the negative
input (AIN1)

Port 1:

Port 1 is an 8-bit bi-directional I/O port. Port pins P1.2 toP1.7 provides internal
pull-ups. P1.0 and P1.1 require external put (AIN1), respectively, of the on-chip
precision analog comparator. The Port 1 output buffers can sink 20 m A and can
drive LED displays directly. When 1s are written to Port 1 pins, they can be used as
inputs. When pins P1.2 to P1.7 are used as inputs and are externally pulled low, they
will source current (IIL) because of the internal pull-ups. Port 1 also receives code
data during Flash programming and verification.

Port 3:

Port 3 pins P3.0 to P3.5, P3.7 are seven bi-directional I/O pins with internal pull-
ups. P3.6 is hard-wired as an input to the output of the on-chip comparator and is
not accessible as a general purpose I/O pin. The Port 3 output buffers can sink 20
MA. When 1s are written to Port 3 pins they are pulled high by the internal pull-ups
and can be used as inputs. As inputs, Port 3 pins that are externally being pulled low
will source current (IIL) because of the pull-ups.
Port 3 also serves the functions of various special features of theAT89C2051 as listed
below: Port 3 also receives some control signals for Flash programming and
verification.
 RST:

Reset input. All I/O pins are reset to 1s as soon as RST goes high. Holding the RST
pin high for two machine cycles while the oscillator is running resets the device.
Each machine cycle takes 12 oscillator or clock cycles.

XTAL1:

Input to the inverting oscillator amplifier and input to the internal clock operating
circuit.

XTAL2:

Output from the inverting oscillator amplifier.

 5.3 OSCILLATOR CHARACTERSTICS
XTAL1 and XTAL2 are the input and output, respectively, of an inverting amplifier
which can be configured for use as an on-chip oscillator, as shown in Figure 1.
Either a quartz crystal or ceramic resonator may be used. To drive the device from
an external clock source, XTAL2 should be left Un connected while XTAL1 is driven
as shown in Figure 2.
There are no requirements on the duty cycle of the external clock signal, since the
input to the internal clocking circuitry is through a divide-by-two flip-flop, but
minimum and maximum voltage high and low time specifications must be observed.

Figure 5.3: Oscillator Connections

Note: C1, C2 = 30 PF ｱ 10 PF for Crystals and 40 PF ｱ 10 PF for Ceramic Resonators

Figure 5.4:External Clock Drive Configuration

AT89C2051 4

Special Function Registers

A map of the on-chip memory area called the Special Function Register SFR) pace is
shown in the table below.
Note that not all of the addresses are occupied, and unoccupied addresses ay not be
implemented on the chip. Read accesses to these addresses will in general return random
data, and write accesses will have an indeterminate
effect. User software should not write 1s to these unlisted locations, since they may be used
in future products to invoke new features. In that case, the reset or inactive values of the
new bits will always be 0.

Table 5.1:AT89C2051 SFR Map and Reset Values

 Programming of Land Mine Robot

INCLUDE 89c2051.mc

buzzer EQU p3.7 p3.1

mainloop:
CLRp3.0

JNBp1.4,la1 SETB p3.0

SETB main:

CLR p3.1
CLR buzzer
l :
a
1
:

l
a
2
:

l
a
3
 NBp1.6,la3 SETB p3.0 CLR p3.1
J CLR buzzer
N
B CLR p3.0
p CLR p3.1
1 SETB buzzer JMPmainloop
.
5
,
l
a
2

C
L
R

p
3
.
0

S
E
T
B

p
3
.
1
C
L
R

b
u
z
z
e
r

J
5.3 PROGRAMMING THE FLASH

The AT89C2051 is shipped with the 2K bytes of on-chip PEROM code memory
array in the erased state (i.e., contents= FFH) and ready to be programmed. The
code Memory array is programmed one byte at a time. Once the array is
programmed, to re-program any non-blank byte the entire memory array needs to
be erased electrically.

Internal Address Counter: The AT89C2051 contains an internal PEROM address

counter, which is always reset to000H on the rising edge of RST and is advanced by
applying a positive going pulse to pin XTAL1.

Programming Algorithm: To program the AT89C2051,the following sequence is

recommended.
1.Power-up sequence: Apply power between VCC and GND pins Set RST and
XTAL1 to GND
2.Set pin RST to “H” Set pin P3.2 to “H”
3.Apply the appropriate combination of “H” or “L” logic levels to pins P3.3, P3.4,
P3.5, P3.7 to select one of the programming operations shown in the PEROM
Programming Modes table.
To Program and Verify the Array:
1. Apply data for Code byte at location 000H to P1.0 to P1.7.
2. Raise RST to 12V to enable programming.
3. Pulse P3.2 once to program a byte in the PEROM array or the lock bits. The byte-
write cycle is self-timed and typically takes 1.2 ms.

4. To verify the programmed data, lower RST from 12V to logic “H” level and set
pins P3.3 to P3.7 to the appropriate levels. Output data can be read at the port P1
pin.

5. To program a byte at the next address location, pulseXTAL1 pin once to advance
the internal address
6. Repeat steps 5 through 8, changing data and advancing the counter. Apply new
data to the port P1 pins. Address counter for the entire 2K bytes array or until
the end of the object file is reached.
7. Power-off sequence: Set XTAL1 to “L”
Set RST to “L”
Turn VCC power off

DATA POLLING : The AT89C2051 features Data Polling to indicate the end of a
write cycle. During a write cycle, an attempted read of the last byte written will
result in the complement of the written data on P1.7. Once the write cycle has been
completed, true data is valid on all outputs, and the next cycle may begin. Data
Polling may begin any time after a write cycle has been initiated.

READ/BUSY : The Progress of byte programming can also be monitored by the

RDY/BSY output signal. Pin P3.1 is pulled low after P3.2 goes High during
programming to indicate BUSY. P3.1 is pulled High again when programming is
done to indicate READY.

PROGRAM VERIFY : If lock bits LB1 and LB2 have not been programmed code
data can be read back via the data lines for verification:
1. Reset the internal address counter to 000H by bringing RST from “L” to “H”.
2. Apply the appropriate control signals for Read Code data and read the
output data at the port P1 pins.
3. Pulse pin XTAL1 once to advance the internal address counter.
4. Read the next code data byte at the port P1 pins.
5. Repeat steps 3 and 4 until the entire array is read .The lock bits cannot be
verified directly. Verification of the lock bits is achieved by observing that their
features are enabled.
 CHIP ERASE : The entire PEROM array (2K bytes) and the two Lock Bits are
erased electrically by using the proper combination of control signals and by
holding P3.2 low for 10 ms. The code array is written with all “1”s in the Chip.
Erase operation and must be executed before any nonblank memory byte can be re-
programmed.

READING THE SIGNATURE BYTES : The signature bytes are read by the same
procedure as a normal verification of locations 000H, 001H, and 002H, except that
P3.5 and P3.7 must be pulled to logic low. The values returned are as follows.
(000H) = 1EH indicates manufactured by Atmel (001H) = 21H indicates 89C2051

Programming Interface:
Every code byte in the Flash array can be written and using the appropriate
combination of control signals can erase the entire array. The write operation cycle is
self timed and once initiated, will automatically time itself to completion.
All major programming vendors offer worldwide support for the Atmel micro
controller series. Please contact your local programming vendor for the appropriate
software revision.
FLASH PROGRAMMING MODES

Notes:

1. The internal PEROM address counter is reset to 000H on the rising edge of RST
and is advanced by a positive pulse at XTAL 1 pin.
2.Chip Erase requires a 10 ms PROG pulse.
3.P3.1 is pulled Low during programming to indicate RDY/BS
Figure 3. Programming the Flash Memory

Figure 4. Verifying the Flash Memory

Flash Programming and Verification Characteristics

Baud Rate Generator

Timer 2 is selected as the baud rate generator by setting TCLK and/or RCLK in
T2CON (Table 2). Note that the baud rates for transmit and receive can be different
if Timer 2 is used for the receiver or transmitter and Timer 1 is used for the other
function. Setting RCLK and/or TCLK puts Timer 2 into its baud rate generator
mode, as shown in Figure4. The baud rate generator mode is similar to the auto-
reload mode, in that a rollover in TH2 causes the Timer 2 registers to be reloaded
with the 16-bit value in registers RCAP2H and RCAP2L, which are preset by
software.
The baud rates in Modes 1 and 3 are determined by Timer2’s overflow rate
according to the following equation.
The Timer can be configured for either timer or counter operation. In most
applications, it is configured for timer operation (CP/T2 = 0). The timer operation is
different for Timer 2 when it is used as a baud rate generator. Normally, as a timer,
it increments every machine cycle (at 1/12 the oscillator frequency). As the baud
rate generator, however, it increments every state time (at 1/2 the oscillator
frequency). The baud rate formula is given below.

where (RCAP2H, RCAP2L) is the content of RCAP2H and RCAP2L taken as a 16-
bit unsigned integer. Timer 2 as a baud rate generator is shown in Figure 4. This
figure is valid only if RCLK or TCLK = 1 in T2CON. Note that a rollover in TH2
does not set TF2 and will not generate an interrupt. Note too, that if EXEN2 is set, a
1-to-0 transition in T2EX will set EXF2 but will not cause a reload from (RCAP2H,
RCAP2L) to (TH2, TL2). Thus when Timer 2 is in use as a baud rate generator,
T2EX can be used as an extra external interrupt.

Note that when Timer 2 is running (TR2 = 1) as a timer in the baud rate generator
mode, TH2 or TL2 should not be read from or written to. Under these conditions,
the Timer is incremented every state time, and the results of a read or write may not
be accurate. The RCAP2 registers may be read but should not be written to,
because a write might overlap a reload and cause write and/or reload errors. The
timer should be turned off (clear TR2) before accessing the Timer 2 or RCAP2
registers.
 Figure 5.5 :Timer 2 in Clock-out Mode

Programmable Clock Out

A 50% duty cycle clock can be programmed to come out on P1.0, as shown in Figure
5. This pin, besides being a regular I/O pin, has two alternate functions. It can be
programmed to input the external clock for Timer/Counter 2 or to output a 50%
duty cycle clock ranging from 61 Hz to 4 MHz at a 16 MHz operating frequency. To
configure the Timer/Counter 2 as a clock generator, bit C/T2 (T2CON.1) must be
cleared and bit T2OE (T2MOD.1) must be set. Bit TR2 (T2CON.2) starts and stops
the timer. The clock-out frequency depends on the oscillator frequency and the
reload value of Timer 2 capture registers (RCAP2H, RCAP2L), as shown in the
following equation.
In the clock-out mode, Timer 2 roll-overs will not generate an interrupt. This
behavior is similar to when Timer 2 is used as a baud-rate generator. It is possible to
use Timer 2 as a baud-rate generator and a clock generator simultaneously. Note,
however, that the baud-rate and clock-out Frequencies cannot be determined
independently from one another since they both use RCAP2H and RCAP2L.

UART

The UART in the AT89C52 operates the same way as the UART in the AT89C51.