e-ISSN : 2348-4470

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International Journal of Advance Engineering and Research

Development
Volume 3,Issue 4,April -2016

Design and Analysis of an Efficient 16-Bit Multiplier

Kajal Agrawal1
1
Electronics and Communication, VGEC, [email protected]

Abstract— In the era of digitalization, it is required to increase the speed of digital circuits while
reducing area and power consumption. In any digital system, multiplication is a key element. One of
the important parameter which affects the performance of entire system is performance of multiplier
unit. Therefore, it is required to design efficient multiplier unit. To improve the efficiency of
multiplier unit, we need to optimize various parameters such as speed and area. It is a great challenge
to design an efficient and high speed multiplier unit with lower area and power consumption. In this
work, FPGA based efficient 16-bit multiplier with low area consumption is designed by hybrid
multiplier of Vedic and Array multiplier by using Kogge Stone Adder. Area is reduced by 50% in
terms of reducing Number of Adders.

Keywords— Vedic multiplier, Array multiplier, Kogge Stone Adder

I. INTRODUCTION

Multipliers play an important role in today’s digital signal processing and various other applications.
With advances in technology, many researchers have tried and are trying to design multipliers which
offer either of the following design targets – high speed, low power consumption, regularity of layout
and hence less area or even combination of them in one multiplier thus making them suitable for
various high speed, low power and compact VLSI implementation.
To reduce the number of partial products to be added, Modified Booth algorithm is one of the most
popular algorithms. To achieve speed improvements Wallace Tree algorithm can be used to reduce
the number of sequential adding stages. Further by combining both Modified Booth algorithm and
Wallace Tree technique we can see advantage of both algorithms in one multiplier. However with
increasing parallelism, the amount of shifts between the partial products and intermediate sums to be
added will increase which may result in reduced speed, increase in silicon area due to irregularity of
structure and also increased power consumption due to increase in interconnect resulting from
complex routing.
The common multiplication method is “add and shift” algorithm. In parallel multipliers number of
partial products to be added is the main parameter that determines the performance of the multiplier.
Serial-parallel multipliers compromise speed to achieve better performance for area and power
consumption. The selection of a parallel or serial multiplier actually depends on the nature of
application. In this lecture we introduce the multiplication algorithms and architecture and compare
them in terms of speed, area, power and combination of these metrics.
There are so many types of multiplication algorithm such as Array multiplier, Wallace tree multiplier,
Dadda multiplier, Booth algorithm, Karatsuba algorithm, Vedic multiplier, etc.
In electronics, an adder is a digital circuit that performs addition of binary numbers. In many
computers and other kinds of processors adders are used in the arithmetic logic units or ALU. They
are also utilized in other parts of the processor, where they are used to calculate addresses, table
indices, increment and decrement operators, and similar operations.
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 International Journal of Advance Engineering and Research Development (IJAERD)
Volume 3,Issue 4,April 2016,e-ISSN: 2348 - 4470 , print-ISSN:2348-6406

A typical adder circuit generates sum and carry as the output. The main purpose of these addresses is
used to add the different formats like Excess-3, binary coded decimal (BCD) and gray code. When
the one’s or two’s compliment are being used to specify negative numbers, it is small to alter adder to
subtractor. A more complex adder is used to represent other signed numbers. Adder circuits are not
only used to add binary numbers, but also used in digital applications such as address, table index,
decoding and calculation etc.

II. THEORATICAL BACKGROUND

Kogge Stone Adder:

The Kogge Stone has low logic depth, high node count, and minimal fan out. While a high node
count implies a larger area, the low logic depth and minimal fan-out allow faster performance.

Kogge Stone Adder[17]

There are mainly three computational stages in Kogge Stone Adder:

1. Preprocessing
2. Carry generation network
3. Post processing

Preprocessing Stage:
Preprocessing is the first stage where the generate and propagate signals of all the input pairs of
signals A and B are generated separately for each bit. The logical equations of the propogate and
generate signals are given by the following equations:
Pi = Ai xor Bi
Gi = Ai . Bi

Carry Generation Stage:

Carry generation is the second stage. At this stage the carries of all the bits are generated separately
for each bit. They are divided into smaller pieces and this overall process is carried out in parallel for
all the bits. Carry generate and Carry propagate bits are used as intermediate signals and their logical
equations are given as follows:
CPi:j = Pi:k+1 . Pk:j
CGi:j = Gi:k+1 + (Pi:k+1 . Gk:j)
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 International Journal of Advance Engineering and Research Development (IJAERD)
Volume 3,Issue 4,April 2016,e-ISSN: 2348 - 4470 , print-ISSN:2348-6406

Post Processing Stage:

This is the final step or stage of the KSA which is common for all types of adders,
Ci-1 = (Pi.Cin) + Gi
Si = Pi xor Ci-1

Array Multiplier:

The traditional method for multiplication is done by using array multiplier. Array multiplier is
popular due to its regular structure. It is based on add and shift algorithm. In parallel multiplication
operation, number of partial products to be added is the main parameter that determines the
performance of the multiplier. Each partial product is generated by the multiplication of the
multiplicand with one multiplier bit. The partial products are then shifted according to their bit order
and then added. Addition can be performed with normal carry propagate adder[3].

Structure of array multiplier

For n x n array multiplier, number of adders and gates needed are:

1. n(n-2) full adders
2. n half adders
3. n2 AND gates
The advantage of array multiplier is that it has minimum complexity and regular structure. And
Disadvantages are large number of logic gates, so more chip area. It has high power consumption
and it is limited to 16-bits.

Vedic Multiplier:
Vedic Mathematics is a book written by the Indian monk Swami Bharati Krishna Tirtha and first
published in 1965. It contains a list of mental calculation techniques claimed to be based on
the Vedas. The mental calculation system mentioned in the book is also known by the same name or
as "Vedic Maths". Its characterization as "Vedic" mathematics has been criticized by academics, who
have also opposed its inclusion in the Indian school curriculum. Ancient mathematics has 16
different sutras, which are taken from Atharva Ved [3]. For multiplication, there are two sutras. First
is Urdhva Tiryakbhyam sutra. Urdhva-Tiryagbhyam is one of the sutra from 16-Vedic sutras which
performs the multiplication operation of two decimal numbers. Urdhva-Tiryagbhyam is the general
formula applicable to all cases of multiplication of a large number by another large number.
“Urdhva” means vertically and “Tiryagbhyam” means crosswise therefore it is also called as
vertically and Crosswise Algorithm [3, 5]. It means “Vertical & Cross-wise”.

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 International Journal of Advance Engineering and Research Development (IJAERD)
Volume 3,Issue 4,April 2016,e-ISSN: 2348 - 4470 , print-ISSN:2348-6406

Example of Vedic multiplier [5]

The other one is Nikhilam Navatashcaramam Dashatah sutra. It means “All from 9 and last from
10”.The sutra basically means start from the left most digit and begin subtracting 9 from each of the
digits; but subtract 10 from the last digit [1].
Its advantage is that it has Minimum Delay. And its Disadvantage is that as number of bits increases,
multiplication process becomes tedious.

III. ANALYSIS

Any Multiplier Circuit contains small multiplication units and adder circuits. Uptill now, Simple half
adder and multi-bit Full adder circuits are used for partial product addition. But the time taken for
this addition has to be decreased for increased speed and decreased area of multiplier circuits. For
example, 16-bit Vedic multiplier is implemented by four 8-bit Vedic multipliers and 16-bit and 24-bit
adders. From total time taken by 16-bit multiplier, almost 40% time and 50% of area consumed by
adder circuits. This can be reduced by using other adders such as, Carry Save adder, Carry bypass
adder, Carry look-ahead adder, Carry select adder, other parallel prefix adders which are called fast
adders like Kogge Stone Adder and Brent Kung Adder. Parallel Prefix Adders are used to increase
speed and to decrease area. Here, Vedic multiplier and hybrid of vedic and array 16-bit multiplier are
implemented with carry select adder, carry bypass adder, Brent Kung adder and Kogge Stone adder.

From the Literature Survey, Vedic multiplier is efficient in terms of delay but has large number of
adders. Because of which Area is increasing. So the Hybrid of Vedic multiplier, Array multiplier and
Karatsuba multiplier are implemented. But still the area is lower in Karatsuba algorithm with Highest
Delay. The hybrid of Vedic multiplier and Array multiplier has smaller delay and to decrease area
different adder units are used.
From Analysis and Results, the Hybrid multiplier of Vedic multiplier and Array multiplier by using
Kogge Stone Adder is consuming Lesser Area. This Proposed Algorithm has delay of 31.304 ns,
which is slightly more (about 1.5 ns) than Vedic multiplier. But the Area is decreased by about 50%.
So this Algorithm is Efficient in terms of Area.

IV. SIMULATIONS

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 International Journal of Advance Engineering and Research Development (IJAERD)
Volume 3,Issue 4,April 2016,e-ISSN: 2348 - 4470 , print-ISSN:2348-6406

Figure 1. RTL Schamatic

Figure 2. Resources used

Figure 3. Simulation Graph

Figure 4. Synthesis Report

V. CONCLUSION AND FUTURE SCOPE

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 International Journal of Advance Engineering and Research Development (IJAERD)
Volume 3,Issue 4,April 2016,e-ISSN: 2348 - 4470 , print-ISSN:2348-6406

It is found that the Hybrid of Vedic multiplier and Array multiplier is efficient in terms of Speed and
Area. Further to increase efficiency, Adders are replaced by Different Adders. The Performance of
Hybrid of Vedic multiplier and Array multiplier with Kogge Stone Adder is found efficient. Area is
decreasing by about 50%.
The algorithm can be further optimized in terms of delay by using pipelining methods and precision
of the result can be increased by adding efficient truncation and rounding methods. This algorithm
can also be implemented for Floating point multiplications.

References
[1] Vinod Buddhe, Prasanna Palsodkar. “Design and Verification of Dadda Algorithm Based Binary Floating Point
Multiplier” IEEE International Conference on Communication and Signal Processing, April 3-5, 2014.
[2] G.Challa Ram, D.Sudha Rani, R.Balasaikesava, K.Bala Sindhuri. “Design of Delay Efficient Modified 16 bit
Wallace Multiplier” IEEE International Conference On Recent Trends In Electronics Information Communication
Technology, May 20-21, 2016, India.
[3] Sushma Wadar, Y. V. Chavan, Sr. IEEE-Member, Avinash Patil. “Improved Algorithm for Floating Point
Multiplication” IEEE International conference on Signal Processing, Communication, Power and Embedded System
(SCOPES)-2016.
[4] Hemangi P.Patil, S.D.Sawant. “FPGA Implementation of Conventional and Vedic Algorithm for Energy Efficient
Multiplier” IEEE International Conference on Energy Systems and Applications (ICESA) Dr. D. Y. Patil Institute of
Engineering and Technology, Pune, India 30 Oct - 01 Nov, 2015.
[5] Yogita Bansal, Charu Madhu, Pardeep Kaur. “HIGH SPEED VEDIC MULTIPLIER DESIGNS” IEEE Proceedings
of 2014 RAECS UIET Panjab University Chandigarh, 06 – 08 March, 2014.
[6] Paras Gulati, Harsh Yadav and Manoj Kumar Taleja. ”Implementation of an Efficient Multiplier Using the Vedic
Multiplication Algorithm” International Conference on Computing, Communication and Automation (ICCCA2016) .
[7] S.P.Pohokar, R.S.Sisal, K.M.Gaikwad, M.M.Patil, Rushikesh Borse. “Design and Implementation of 16 x 16
Multiplier using Vedic Mathematics” International Conference on Industrial Instrumentation and Control (ICIC)
College of Engineering Pune, India. May 28-30, 2015.
[8] Anand Mehta, C. B. Bidhul, Sajeevan Joseph, Jayakrishnan. P. “Implementation of Single Precision Floating Point
Multiplier using Karatsuba Algorithm” IEEE International conference on Green computing, communication and
Conservation of energy, 12-14 Dec. 2013.
[9] Arish S, R.K.Sharma. “An efficient floating point multiplier design for high speed applications using Karatsuba
algorithm and Urdhva-Tiryagbhyam algorithm” IEEE International Conference on Signal Processing and
Communication, March 16-18, 2015.
[10] Shinji Nakamura. “Algorithms for Iterative Array Multiplication” IEEE TRANSACTIONS ON COMPUTERS,
VOL. C-35, NO. 8, AUGUST 1986.
[11] Rajendra Katti. “A Modified booth algorithm for high Radix Fixed-point Multiplication” IEEE TRANSACTIONS
ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 2, NO. 4, DECEMBER 1994.
[12] Taewhan Kim, William Jao, and Steve Tjiang. “Circuit Optimization Using Carry–Save–Adder Cells” IEEE
TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 17,
NO. 10, OCTOBER 1998.
[13] Fu-Chiung Cheng, Stephen H. Unger. “Self-Timed Carry-Lookahead Adders” IEEE TRANSACTIONS ON
COMPUTERS, VOL. 49, NO. 7, JULY, 2000.
Websites:
[14] FPGA Design
https://www.xilinx.com/support/documentation/sw_manuals/xilinx10/isehelp/ise_c_fpga_design_flow_overview
[15] http://www.fpgacentral.com/docs/fpga-tutorial/fpga-design-flow-overview
Books:
[16] Verilog HDL: A Guide to Digital Design and Synthesis, Second Edition. By Samir Palnitkar. Publisher: Prentice Hall
PTR. Pub Date: February 21, 2003. ISBN: 0-13-044911-3
[17] DIGITAL INTEGRATED CIRCUITS - A Design Perspective, Second Edition. By JAN M. RABAEY.
Publisher: Prentice Hall Electronics and VLSI Series.

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