Transistors 71

CHAPTER 3 Transistors
COURSE OUTLINE:
3.1 BJT configuration and biasing,small and large signal model.
3.2 T and π model.
3.4 Concept of differential amplifer using BJT.
3.5 BJT as switch and logic circuit.
3.6 Construction and working principle of MOSFET and CMOS.
3.7 MOSFET as logic circuit.
Introduction:
After having studied the junction diode which is two terminal non linear device we are now about to
study the three terminal non linear semiconductor device.Three terminal semiconductor device are
far more useful than two terminal one because they can be used for multitude of operation.
Transistors are basically of two types namely Bipolar Junction Transistor and Field Effect
Transistor.In Bipolar Junction Transistor both holes and electrons take part in the conduction and
hence, the name Bipolar.Where as Field Effect Transistor conducts either with holes or electrons.
So,Field Effect Transistors are also called unipolar transistors.It should be noted that when we say
transistor only we automatically mean bipolar junction transistor.Field effect transistors are of two
types namely Junction Field Effect Transistor(JFET) and Metal oxide Semiconductor Field Effect
Transistor(MOSFET).JFET and MOSFET will be studied latter in this chapter.
In transistor the basic principle is to apply the voltage between to terminal to control the flow of
current through the third terminal. Thus, transistor acts as a controlled source.
Transistor:
When a third doped material is suitably connected to a PN junction diode,the resulting device is
known as transistor.Or the semiconductor device which is formed by sandwitching either p-type
material by n-type material or n-type material by p-type material is called as transistor.Thus,
transistors are of two types viz npn transistor and pnp transistor.
i)npn transistor
when a third doped material is suitably connected to a PN junction diode or crystal diode in such a
way that p-type material is sandwitched by n-type material then npn transistor is formed.
n p n

ii)pnp transistor:
When a third doped material is suitably connected to a pn junction diode or crystal diode in such a
way that n-type material is sandwitched by p-type materials then pnp transistor is formed.

p n p

In a transistor there are three basic parts.They are:

1.Emitter(E):The heavily doped region of a transistor which supply charge carriers is known as
emitter.For npn transistor the emitter is of n-type and for pnp transistor emitter is of p-
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72 Transistors

type.Thus,for npn transistor majority charge carriers are electrons and for pnp transistor majority
charge carriers are holes.
2.Base(B):The lightly doped region or the middle region of the transistor is known as base.For npn
transistor ,the base is of p-type and for pnp transistor the base is of n-type.
3.Collector(C):The moderately doped region of the transistor is called as collector.It lies on the other
side of the emitter.For npn transistor collector is of n-type and for pnp transistor the collector is of
p-type.The function of collector is to collect the charge carriers supplied by the emitter.
It is to be noted that transistor is unsymmetrical device.The size of the collector is more than the
the size of the emitter and the size of the base is the smallest one.
n p n

E C

p n p

E C

B
Transistor works in the following modes:

i.Active mode:when the emitter base junction is forward biased and the collector base junction is
reversed biased the transistor is said to be in the active mode.In this mode the transistor works as an
amplifier.

ii.Saturation mode:When the emitter base junction and the collector base junction are both forward
biased the transistor is said to be in saturation mode.

iii.cutoff mode:When emitter base junction and collector base junction are both reversed biased
the transistor is said to be in cutoff mode.
The saturation and cutoff modes of transistor are used to make the transistor work as a switch.

iv.Inverse active mode:When emitter base junction is reversed biased and the collector base
junction is forward biased the transistor is said to be in inverse active mode.Though there are very
few application s of this mode of operation,it is very important.In this mode the transistor operate
with the role of emitter and collector interchanged.One important use of this mode can be found in
the TTL circuit where the advantage of this transistor action is taken to remove the excess base
charge from another transistor which ultimately increases switching speed.

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 Transistors 73

Working of npn transistor:

n p n

E C

IE IC

B IB

VBE VCB
Fig:Working of npn transistor

The figure shows the working of npn transistor.When emitter base junction and collector base
junction are biased for active mode,the npn transistor starts to operate.
The electrons in n-type material are repelled by the negative terminal of the battery.These
electrons diffuse in the base region where electron and hole recombine.After recombination there
are few holes left in p-type matetial(ie base). So hole is shown as minority charge carrier .The excess
of the majority charge carriers reach to the collector.Hence,the conduction in npn transistor is due
to the electrons.The emitter current IE,base current IB, and collector current IC are shown in the
conventional direction .
Applying KCL we get,
= +
Thus,the emitter current is the sum of the base current and the collector current.
Note:
For the sake of simplicity,the depletion region and the bound charge carriers are not shown here.
Working of pnp transistor:
p n p

E C

IE IC

B IB

VBE VCB
Fig:Working of pnp transistor

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74 Transistors

We can easily explain the working of pnp transistor awith the similar approach that we made for npn
transistor.For pnp transistor conduction is done by holes. So holes are the majority charge carriers.
(Note:However,the conduction inside the pnp transistor is done by holes but in the external circuit
the conduction is still by the electrons.)
The direction for the emitter current,base current and the collector current is shown in the figure.
Applying KCL,we get
= +
Symbols for pnp and npn transistor:
While making transistor circuits it is a tedious job to draw the actual structure of the
transistor.so,we use the symbols to represent the pnp and npn transistor.

IC IE IE IC
C E E C

IB IB

B B

Fig:Symbol of pnp transistor Fig:Symbol of npn transistor

(Pointing in point) (not pointing in)

Note that the arrow in the symbol suggests the direction of the emitter current.The transistor
curents are labelled as per convention.

Transistor configuration:
Transistor is a three terminal nonlinear device and it has three terminals to connect to the external
circuit. To perform a specific function a device should have input and output. To give input to the
device we need at least two terminals and to take output from the device we need at least two
terminals. So, in total we need four terminals for a circuit to perform a specific function. But the
problem is that transistor has only three terminals. This problem is solved by making one terminal
common to both the input and output circuit.This is how the transistor can be operated in the active
mode.In active mode transistor can be configured in three ways.Accorodingly there are three types
of transistor configuration. They are
1.Commom Base Configuration
2.Common Emitter Configuration
3.Common Collector Configuraiton

1.Commom Base Configuration:

When the base terminal is common to both input and output circuit then the transistor is said to be
in common base configuration.

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 Transistors 75

IE IC IE IC

+ - + -
VBE VCB
VBE VCB
Signal RC
+ +
Signal - -
IB IB

VBB VCC VBB VCC

Fig: CB configuration for npn and pnp transistors

Here,input current is emitter current IE and output current is collector current(IC).
Here,input voltage is VBE and output voltage is VCB.
Current amplification factor( ):
Current amplification factor ( ) for common base configuration is defined as the ratio of change in
output current(ΔIC) to change in input current (ΔIE) at constant collector base voltage VCB.
i.e = at constant VCB.
Leakage current ICBO:

No signal RC
ICBO

VBB VCC

So,practically when signal is applied,

No signal
RC
IC+ICBO

VCC
VBB

Let us use open the emitter terminal.Then when we look at collector base junction it is reverse
biased.In the reverse biased conditon we assumed ideal diode doesnot conducts .But in reality a few
leakage current flows in the direction of the applied v0.Similarly,due to the practical reason there
exist leakage current in base collector junction of the above common base configuration.It is
denoted by ICBO which means leakage current at collector base junction with emitter open.

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76 Transistors

∴ = +
∴ = +
Characterstics of Common Base configuration:
a.Input Characterstics:
The plot of input current IE and input voltage VBE at constant output voltage VCB is known as input
characterstics in common base configuration.
IE(mA)

VBE(Volts)

0.7V

( )=

b.Output characterstics:
The plot of output current(IC) versue output voltage(VCB) at constant input current IE is known as
output characterstics in the common base configuration.

Fig:Output Characterstics for common base configuration

( )=

2.Common Emitter Configuration:

The transistor configuration in which the emitter terminal is common to both input and output
circuit is known as common emitter configuration.Following circuit diagram shows the common
emitter configuration for npn and pnp transistor:

By Bikal Adhikari and Pramil Paudel

 Transistors 77
IC
IC
IB
IB

RC RC
Signal IE
Signal IE

VBB VCC VCC

VBB
Fig:CE configuration for npn and pnp transistors
Here the input current is Base current(IB )and the output current is Collector current(IC).
Similarly,input voltage is VBE and output voltage is VCE.
Base Current amplification factor(β):
Base current amplification factor for common emitter configuration is defined as the ratio of change
in the output current ΔIC to the change in the input current ΔIB at constant vCE.

. =

Leakage current ICEO:

No Signal
ICEO

VCC
VBB
Due to the reverse bias leakage current ICEO flow from collector to emitter when the base is made
open in CE configuration .The current ICEO is called as leakage current and it is read as collector to
emitter current with base kept open.
So,in practical case,small amount of ICEO appears in the circuit even when the signal is applied.

IB

RC

Signal IE

VBB VCC

∴ = +
, = + +
, = + +
For approximate study,
=0
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78 Transistors

∴ = ( + 1)
Characterstics of the Common emitter configuration:
1.Input Characterstics:
The graphical relationship between input current IB and input Voltage VBE at constant output voltage
VCE is called as input characterstics for CE configuration.

Fig:Input Characterstics of Common Emitter Configuration

∴ ( )=

2.Output Characterstics:
The graphical relationship between output voltageVCE and output current IC at constant input
current IB is called as output characterstics in common emitter configuration.

Fig:Output characterstics of Common Emitter Configuration

∴ ( )=
3.Common Collector Configuration:
The transistor configuration in which collector terminal is common to both the input and output
circuit is known as common collector configuration.Common collector configuration for pnp and
npn transistor is shown below:

By Bikal Adhikari and Pramil Paudel

 Transistors 79
IE

IB

RE
IC
Signal

VBB VCC
Fig:CC configuration for pnp transistor

IE

IB

RE
IC
Signal

VBB VCC

Fig:CC configuration for npn transistor

Here input current is base current IB and output current is emitter current IE.
Similarly,input voltage is VCB and output voltage is VCE.
Current amplification factor( ) for Common Collector configuration:
It is defined as the ratio of change in output current ΔI E to the change in input current ΔIB of
common collector configuration.
∴ =

Relationship between , β and :

We know that,
= = =
And ,
= + ……( )
Dividing both sides of this equation by ΔIC.We get
= +
1 1
, = +1
1 +1
, =

∴ = …..( )

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80 Transistors

, = −1

, =
∴ = ….( )
Again,
=
−
1
, =
−

∴ = …..( )
∴ = … . . ( )(∵ )

∴ = + 1 … . ( )
Transistor Load Line analysis:
In the transistor circuit analysis ,it is generally required to determine the collector current and
collector emitter voltage.One of the method used is to plot the output characterstics and find the
collector current at any desired collector emitter voltage.However, a more convenient method can
be used to solve such problems.This method is quiet easy and is frequently used in the transistor
circuit analysis.This,method is called as load line analysis.By using this method we can easily
determine the operating point and maximum current- voltage rating for transistor.
Let us consider npn transistor in CE mode when no signal is applied as shown in the
figure.So,DC conditions prevails in the circuit.It is therefore the current flowing through the circuit is
called as zero signal currents which is nothing but DC current.
IC

IB

IE RC
No Signal

VBB VCC

Fig:CE configuration for npn transistor when no signal applied.

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 Transistors 81
Applyling KVL in the output loop.We get,
= ∗ +
∴ = − ∗
The above equation is a first degree equation of the form = −
Since VCC and IC are fixed.The different values of VCE can be obtained for the different values of Load
or resistance RC.So,this line is called as load line.
When IC=0 then,
VCE=VCC
When VCE=0 then
=

Thus,the two points ( , 0) and 0, are the end points of the load line.By joining these two
points load line is constructed.Also these points represent the maximum output voltage and
maximum output current.The Q-point is the point of intersection of load line and output
characterstics curve.

IC

Q-point( operating point or quiescent point)

0,
(VCEQ,ICQ)

VCE

( , 0)

Operating Point (VCEQ,ICQ):

The zero signal value of the collector current and and collector emitter voltage is called as operating
point.It is called operating point because the variation of IC and VCE take place about this point
when the signal is applied.It is also called as quiescent point(or silent )point or Q-point because it is
the point on IC - VCE characterstic when the transistor is silent i.e. there is the absence of the
signal.It is after this point transistor starts to operate in the active region.It is represented as
(VCEQ,ICQ).

Faithful Amplification:
The process of raising the strength of weak signal without changing its general shape is called as
faithful amplification.The key factors for achieving the faithful amplification are:
a.proper flow of the zero signal collector current.
b.minimum proper base emitter voltage VBE.
c.minimum proper collector emitter voltage.

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82 Transistors

VO

Vin

t
t
RC
Signal

Fig:Unfaithful amplification

VO

Vin

t
t
RC
Signal

Fig:Faithful amplification

Transistor Biasing:
The proper flow of zero signal collector current and the maintenance of proper collector emitter
voltage during the passage of the signal is known as transistor biasing.The purpose of transistor
biasing is to keep the emitter base junction forward biased and the collector base junction reversed
biased during the passage of the signal.This can be achieved by using the bias battery or by using
biasing circuit.For the purpose of simplicity and the economy we use biasing circuit for the proper
biasing of the transistor. The circuit which provides biasing is known as biasing circuit.There are four
types of the biasing circuit.They are:
a.Base Bias(or fixed biasing)
b.Emitter Bias
c.Biasing with collector feedback resistor(collector biasing)
d.Voltage divider biasing
a.Base Bias(or fixed biasing):
In this method a base resistor is connected between the power supply and base of the transistor.

By Bikal Adhikari and Pramil Paudel

 Transistors 83

VCC
Here the function of capacitors is to
IB isolate one stage of amplification
from another stage of
RC amplification.Though the terminals
for signal input and output signal
RB IC
are shown our discussion is
Vout
restricted to dc analysis only.For dc
Vin Cout
analysis capacitor acts as open
Cin circuit.And we are now going to
determine zero signal collector
current and collector emitter
voltage.

Fig:Base biasing

Applying KVL at input loop,

− − =0
∴ =
∴ =

Applying KVL at output loop,

− − =0
∴ = −
b.Emitter Biasing:In this method a resistance is connected to the emitter terminal.Also present is a
base resistor between base and power supply.

VCC
IB

Applying KVL at input loop,

RC − − − =0
RB IC Vout , − = +
, − = + ( + 1)
∴ =
( )
Vin Cout
∴ =
Cin Applying KVL at output loop,
IE
− − − =0
RE ∴ = − ( + ) (∵ ≈ )

Fig:Emitter Biasing

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84 Transistors

c.Biasing With collector feedback resistor(Collector Biasing):

In this method a resistor forms the feedback path from collector to base.The emitter resistance is
not used.

VCC

RC

RB IB+IC Applying KVL in input loop,

−( + ) − − =0
IC , − − − = 0(∵ + = )
IB Vout , − = +
, − = ( + 1) + (∵ = ( + 1) )
Vin
Cout ∴ =( )
∴ =
Cin Applying KVL at output loop,
−( + ) − =0
∴ = − (∵ ( + ) ≈ )
Fig:Collector Biasing

d.Voltage Divider Biasing:

Voltage divider biasing is most widely used biasing method.In this method four resistors are
required.And this biasing enable the operation of transistor independent with parameter β.This
means the operation of transistor does not get affected despite the variation in temperature.The
circuit for the voltage divider biasing is given below:

VCC

RC
R1 IC
Vout
Cout
Vin
Cin
Loop I IE
R2
RE

Fig:Voltage Divider Biasing

By Bikal Adhikari and Pramil Paudel

 Transistors 85
For the voltage divider biasing we can find the zero signal collector current and collector emitter
voltage using two methods namely approximate method and actual method(Thevenin’s
method).One can apply any of these two method.Here we shall discuss both these methods.
Approximate method:
The voltage across resistor R2 is given by:
∗
=( )
Applying KVL in the loop I
− − =0
∴ =

∴ = (∵ ≈ )
Applying KVL in output loop,
− − − =0
∴ = − ( + ) (∵ ≈ )

Thevenin’s method:
The above circuit can be drawn as:
VCC

RC

R1 a

IE
VCC R2
RE

b Rth

Note that we are in zero signal analysis.So,we should omit ac things.

To thevenize the left portion of circuit looking from terminals a and b ,we have to calculate Rth and
Vth.
In order to find Rth we look from terminal a and b and short voltage source.Here resistors R1 and R2
appear parallel.
∴ = //
In order to find thevenin voltage Vth,we have to find open circuit voltage.Here the voltage drop
across R2 is Vth.
∗
∴ =
Replacing the left portion with thevenin equivalent circuit.i.e. Vth in series with Rth.

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86 Transistors

VCC

RC

IB IC
Rth

IE
Vth
RE

Applying KVL in base emitter loop.We get,

= + +
∴ =
( )
∴ =

Applying KVL in output loop,

− − − =0
∴ = − ( + ) (∵ ≈ )
BJT transistor modeling:
We discussed modeling of diode in the previous chapter.Similarly,transistor can be modelled to
obtain the linearity.There are two kind of models for transistor namely large signal model or DC
model and small signal model or ac model.We performed dc analysis in biasing of transistor.So,we
hereby skip the large signal modeling.The small signal modeling is concerned with the application of
small signal to transistor.In our course there are two small signal models to study namely Hybrid-π
model and T-model.
a.Hybrid-π model:
In this model a transistor is replaced by one of the following circuit:

B
ib ic C B ib ic C

gmVπ
βib

rπ rO rπ rO

ie ie
E
E
Fig:Two versions of Hybrid-π model with output resistance ro included.

By Bikal Adhikari and Pramil Paudel

 Transistors 87
Transconductance g = ,IC is obtained by dc analysis.

= = =

∴ =
T-model:
In this model a transistor is replaced by one of the following circuits

C C

gmvbe
ie
ib ib
B B

re re
ic
ic
E E

Fig:Two versions of T-model

Where,
=

gm can be obtained as that in hybrid π model .

Example:For the circuit given below find the input impedance,output impedance,current gain,and
voltage gain using:
i.Hybrid-π model
ii.T-model
VCC=20V
Solution:The DC equivalent model is:
2.2K
470K VCC=20V

Cout
2.2K
470K
Vin
β=120
Cin
0.56K +
VCE
+
-
VBE - 0.56K

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88 Transistors

Applying KVL at input loop,

− − − =0
, − = +
, − = + ( + 1)
.
∴ = = = 0.0359
( ) ∗ .
∴ = = 120 ∗ 0.0359 = 4.3
= 25 25℃
.
∴ = = = 0.172℧

∴ = = = 697.6Ω = 0.697
.

= = = 0.99
.
= = = 5.76Ω
.

AC equivalent circuit is:

RC

RB
RE

i.Hybrid-π model:
The circuit with transistor replaced by hybrid equivalent model is:

iin ib ic
+ +
+
rπ Vπ
gmvπ
- RC
Vin RB Vout

iout
RE

- -

Zin Zb
Zout

Input impedance(Zin)=RB//Zb
∗ ∗
= =
( ( )∗ )
=
, = + ( + 1) ∗
By Bikal Adhikari and Pramil Paudel
 Transistors 89
, = 0.697 + 121 ∗ 0.56
, = 68.46
∴ = //
∴ = 470//68.46
∴ = 59.75
= = 2.2
=−
, =−
, =−
, =− ∵ =
, =−
∗
, = − (∵ )

= = −
∗
=− = −104.72
.
=−
, =−
, =−
, =−
, =−
∗ .
∴ = =− =− = −3.85
.
ii.The circuit with transistor replaced by T-model is:

ic
+

ie

+
ib Vout
RC
re

Vin RB
RE iout
ie
- -

Zin Zb Zout
We have,

=
∗ +
=
( ) ( )
=

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90 Transistors

= ( + 1)( + )
= 121 ∗ (5.76Ω + 0.56 )
= 121 ∗ 0.5657
= 68.46
Again,
= //
, = 470//68.46
∴ = 59.75
= = 2.2
=−
= −( + 1)
∗
= −( + 1)
( ) ∗
=− =− = −105.6
.
=−
, = −( + 1)
, = −( + 1)
.
, = −121 ∗ = −3.88
.
Here we see that the result obtained by using hybrid-π model and T model is nearly same.But it must
be noted that when emitter resistance is present T model proves to be more convenient.But this
doesnot mean hybrid-π model can’t be used.
Relation between rπ and re:
We have the hybrid-π model and T-model are:

ib ic C
C
B
gmVπ
gmvbe
rπ rO
ib

B re

ie
ie
E
E
Fig:Hybrid-π model and T-model for BJT

Accoroding to hybrid-π model the base emitter voltage drop is the drop across resistance rπ
∴ = = ∗
∴ = ∗ ……..( )
Similarly,accoroding to T-model the base emitter voltage drop is the drop across the resistor re
∴ = ∗ ……..( )
Since the base emitter voltage for a given transistor is constant.Therefore,equation (i) and (ii) must
be identical.
∗ = ∗
, ∗ = ( + 1) ∗
∴ = ( + 1)
Which is the required relation.
By Bikal Adhikari and Pramil Paudel
 Transistors 91
Phase Reversal:
VCC

One of the important property of transistor in

RC CE configuration is to produce the output with
phase reversal or phase inversion.
Vin Let us consider a transistor in CE
Vout
configuration as shown in the figure:

Assuming Zero signal condition for instant.Let’s apply KVL at the output circuit.We get,
= +
, = −
Since VCE is output voltage and VCC is constant.The differentiation of the above relation with respect
to RC yields

=−

The negative sign indicates that the output is 180° out of phase with the input signal.
Similarly,when signal is applied the amplified inverted output will appear in the output terminal.
So when input waveform is

Vin Vout
The output waveform will be:

t
t

BJT as a switch and logic gates:

As we already mentioned that switch is a basis for building digital circuits.Here it should not be
misunderstood that switch is NOT gate only.Even other logic gates are also called switch in broad
sense because in order to produce required output each transistor in the combination must act as a
switch. So,we shall study about few logic gates.
a.BJT as Switch or NOT gate:

VCC Truth Table:

RC Vin Vout
Vout 0 1
1 0
Vin Q
Fig:BJT as NOT gate and its Truth Table

When input is high the emitter base junction and collector base junction will be forward biased.As a
result, the transistor goes to saturation.In this condition maximum collector current flows through
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92 Transistors

the collector and emitter terminal.Here the transistor acts as a very low impedance path(short
circuit) and seem to conduct the current from supply to the ground.Hence the output is terminal is
shorted to ground and output becomes low.
When the input is low the emitter base junction and collector base junction are both reversed
biased.As a result,the transistor goes to cutoff.In this case the transistor does not conduct any
current and acts as an open circuit.The connection from supply to ground is broken and connection
between supply and output is established.Hence output is high.
As we know,
= −
From the above expression we can see that when the collector current increase ,the output voltage
decreases.So,when collector current is maximum the output voltage should be zero.But practically
due to the existance of leakage current the output can’t be zero and a small voltage drops across
collector emitter terminal.For the saturated BJT,
= 0.2
b.BJT as AND gate:
VCC Truth table:
RC
RA Inputs Outputs
A Q1 A B Y
RB 0 0 0
B Q2 0 1 0
1 0 0
Y=A.B 1 1 1
Fig:BJT as AND gate and its truth table
When A=0, B=0 the transistors Q1 and Q2 both will be in cutoff mode and act as an open circuit.The
supply will be disconnected from output terminal and output will become low.
When A=0,B=1 and A=1,B=0 one of two transistors will be in cutoff and act as an open circuit.Again
the supply will be disconnected from output terminal and output will become low.
When A=1,B=1 both of the transistors will be in saturation mode.The supply will be shorted to
output terminal and output will become high.
c.BJT as OR gate:
VCC
Truth Table:
RC
Inputs Outputs
A B Y
RA
0 0 0
A Q1 B Q2 0 1 1
RB 1 0 1
1 1 1

Y=A+B

When A=0, B=0 the transistors Q1 and Q2 both will be in cutoff mode.Both transistor act as an open
circuit.As a result supply will not be connected to output terminal and output becomes low.

By Bikal Adhikari and Pramil Paudel

 Transistors 93
When A=0,B=1 and A=1,B=0 one of two transistors will be in saturation and act as a short circuit.As
the result supply will be connected to output terminal and output becomes high.
When A=1,B=1 both of the transistors will be in saturation mode and act as short circuit. As the
result supply will be connected to output terminal and output becomes high.
d.BJT as NOR gate:
VCC

Y=A + B
RC
Truth Table:

RA RB Inputs Outputs
A Q1 B Q2 A B Y
0 0 1
0 1 0
1 0 0
1 1 0

Fig:BJT as NOR gate and its truth table

e.BJT as NAND gate:

VCC

RC Truth Table:
Y=A. B
RA Inputs Outputs
A
Q1 A B Y
0 0 1
RB 0 1 1
Q2 1 0 1
B 1 1 0

Fig:BJT as NAND gate and its truth table

Readers are encouraged to understand the operation of NOR gate and NAND gate themselves.
Differential Amplifier:
An amplifier circuit which is designed to amplify the difference of two input signal is known as
differential amplifier.

V1 Differential Vo=A(V2- V1)

V2 Amplifier

Fig:Block diagram for Differential amplifier

Here V1 and V2 are input signals,A is the differential amplifier gain and Vo is the output voltage.
By Pramil Paudel and Bikal Adhikari
94 Transistors

Concept of Differential amplifier using BJT:

VCC

RC RC
VO
v1 Q1 Q2 v2

iE1 iE2

-VEE

The figure shows a circuit for the differential amplifier using BJT.Two matched transistor(i.e. having
identical properties) are connected as shown in the figure.The inputs are applied to the base of both
transistors while the output is taken between the collector of both transistors.The differential
amplifier is a very high speed current switch which is the basis for one of the important logic family
in the digital circuits namely Emitter Coupled Logic(ECL),the fastest logic known so far with the
operating speed below one nano second.The digital circuits using this configuration fall under
Emitter Coupled Logic because as we can see the emitter of the transistors are coupled together.The
current source is placed in the emitter terminal so as to ensure constant total emitter current .let v1
and v2 be the input voltage,A be the gain of each transistor.There are two modes of operation of
differential amplifier.Thet are
a.Double ended operation:
In this mode of operation the input is applied to both the transistors.As an common emitter
amplifier the collector voltage for the transistor Q1 is given as
vC1=-Av1………..(i)
Here the negative sign indicates phase reversal.
Similarly,the collector voltage for transistor Q2 is given as
vC2=-Av2………(ii)
Since the output is taken between the collector of the transistor Q1 and Q2,the output voltage Is
given by:
Vo=vC1-vC2…….(iii)
From the equations (i),(ii) and (iii),we get
Vo=-Av1-(-Av2)
∴vo=A(v2-v1)=A*Voltage diffrence at input
b.Single ended operation:
In this mode of operation input is applied to one input terminal and another input terminal is
grounded.Suppose the input v1 is applied and v2 is grounded.
Then,
vC1=-Av1
vC2=0
Vo= vC1-vC2=- Av1

By Bikal Adhikari and Pramil Paudel

 Transistors 95
Operation of Differential Amplifier as a switch:

VCC

RC RC
A

v1 Q1 Q2 vR

iE1 iE2

-VEE

Let vR be reference voltage and v1 be the input voltage.Let iE1 and iE2 be the emitter current of the
transistors Q1 and Q2 .Since total emitter current is I.
∴ = + …..( )
Also considering base emitter junctions of two transistors as forward biased diode.

= → = ………( )

= → = ………( )
Dividing equation (ii) by equation(iii),we get,

Taking ln on both sides .we get,

−
ln =

∴ = + ln

Generally,η=1 and VT=25mV

∴ = + 25 ln

Let iE1=95% of I then,

95
= + 25 ln
5
, = + 25 ln(19)
≈ + 75
∴ = + 75 ……( )
This means if the input voltage exceeds the reference voltage by just 75 mV almost whole
current(95% of total emitter current) is switched to the emitter(as well as collector) of the transistor
Q1.
Similarly,if iE2=5% of I then,
5
= + 25 ln
95
= − 75 …….( )

By Pramil Paudel and Bikal Adhikari

96 Transistors

This means if the input volatge fall from reference voltage vR by just 75mV then whole current
(95%of total emitter current) is switched to emitter (as well as collector )of transistor Q2.
The voltage at A is given by:
= − ∗ …..( )

When input voltage v1 is high ,almost all current is switched in the collector of the transistor Q1.As
the collector current iC1 increases,the drop across the resistor RC causes the voltage at A to drop
rapidly and it is almost zero when collector current is maximum.As a result the output is low.
When v1 is low ,almost all the current is switched to transistor Q2 .As a result the current through the
collector of transistor Q1 decreases and voltage at collector ie at A starts rising.When collector
current is almost zero,the voltage at collector Q1 is maximum and is said to be high.
Thus,when output is taken across the terminal A we get logical NOT
function.Thus,differential amplifier acts as a switch.Due to this property,differential amplifier has
found its application in the design of digital integrated circuits.The speed of operation is very high
because non of the transistors enter the saturation and there is no problem of delay associated with
removal of excess stored base charge when transistor goes from saturation to cutoff thereby
providing the fastest possible switching speed.Another reason for the fast operation is that the
logical swing is made relatively small as very small voltage is required to switch current from one
branch to another branch.At the end ,the transfer characterstics of the differential amplifier can be
expressed in terms of tanh(ie tan hyperbolic) function.

Field Effect Transistor:

Field effect transistors are another types of three terminal non-linear device which can perform the
functions like amplification,switching etc as done by BJT .Though,the terminal characterstics are
similar,the working mechanism and construction of FET and BJT is completely different.Unlike
BJT,the field effect transistors are unipolar device which means the conduction is done by only one
kind of charge carriers ie either by holes or by electrons.In field effect transistor the output current is
controlled by the field or voltage applied to the input terminals.So,they are called field effect
transistor as field effects the output.There are two types of FET namely JFET and MOSFET.

Junction Field Effect Transistor(JFET)

Junction Field Effect transistor is the simplest type of field effect transistor.In this type of FET a PN
junction is formed between the p-type and n-type material so it is called Junction field effect
transistor.There are two types of JFET.They are p-channel JFET and n-channel JFET.The construction
of p-channel and n-channel JFET are shown in the figure.

In p-channel JFET the p-type silicon bar is doped with n-type material in same way as belt surrounds
our waist.Here,the p-type material forms the channel for for conduction and hence the name p-
channel JFET.Similarly,in n-channel JFET the n-type silicon bar is doped with p-type material in same
way as belt surrounds our waist.Here,n-type material forms the channel for conduction and hence
the name n-channel JFET.As shown in figure there are three terminals namely gate,drain and
source.It is to be noted that JFET is symmetrical device.When connected to external circuit,the drain
and source connection can be interchanged without affecting the overall performance of the circuit.

By Bikal Adhikari and Pramil Paudel

 Transistors 97
Drain(D) Drain(D)

P n
Gate(G) Gate(G)

n n p p

P
n

Source(S) Source(S)

Fig:p-channel JFET Fig:n-channel JFET

D D

G G

S S
Fig:Symbol of p-channel JFET Fig:Symbol of n-channel JFET
Working of JFET:
For proper operation of JFET,the gate is always reversed biased with respect to source and drain
source terminals are so biased that the flow of charge carriers is from source to drain.
Drain(D)

Depletion
P Region
Gate(G)

n n

P
VGS VDS

Source(S)

Fig:Working of p-channel JFET

By Pramil Paudel and Bikal Adhikari

98 Transistors

Drain(D)

Depletion
n Region
Gate(G)

P P

n
VGS VDS

Source(S)

Fig:Working of n-channel JFET

The current flowing through the channel depends upon the voltage applied between the gate and
source terminals.When VGS=0 normal drain current flows through the circuit.When VGS is increased
,depletion layer is increased and the channel width is decreased.As a result,the drain current is
decreased.When VGS is decreased ,depletion layer is also decreased and the channel width is
increased.As a result,the drain current is increased.
Static Characterstics of JFET
a.Drain Characterstics:
The graphical relationship between drain current ID and drain to source voltage VDS at constant gate
to source voltage VGS is called as drain characterstics.
ID(mA
) Ohmic Active Region

Region

IDSS
VGS=0
Breakdown
Region

VDS

Fig:Drain Characterstics VDS(max)

VP

By Bikal Adhikari and Pramil Paudel

 Transistors 99

Here,
VP=Pinch off voltage(Voltage after which JFET conducts)
IDSS=Shorted gate drain current
b.Transfer Characterstics:
The graphical relationship between the drain current ID and gate to source voltage VGS is known as
transfer characterstics.

ID(mA)

IDSS

-VGS VGS

VGS(off) VP
Fig:Transfer Characterstics

The transfer characterstics curve of JFET is governed by the equation:

= 1− = 1−
( )
Where the symbols have their usual meaning.
Metal Oxide Semiconductor Field Effect Transistor(MOSFET):
Metal oxide semiconductor field effect transistor (MOSFET) is another type of field effect transistor
.In this type of FET the oxide layer insulates the gate electrode from the device body and hence it is
called metal oxide semiconductor field effect transistor.
MOSFET has very high input impedance than JFET and BJT.Due to the advent of
MOSFET ,JFET has become virtually obsolete.This is because MOSFET can perform all the functions
performed by JFET with much more improvement.But the question is why BJTs are still used.The
answer is because during the process of designing circuit there arises the conditions where the use
of BJT along with MOSFET results best circuit for particular application.As compared to BJT,MOSFET
can be made in small silicon area,their manufacturing process is relatively simple,cheap and they
require low power to operate.MOSFET has specially dominated BJT in the design of analog and
digital integrated circuits.This is because the scale of integration of MOSFET is more than BJT for
same area of silicon chip.Semiconductor manufacturers belive that in the near future MOSFET will
completely replace BJT for all kind of applications.

Types of MOSFET:
a.On the basis of type of channel present:
i.n-channel MOSFET
In this type of MOSFET the channel present is of n-type material which connects source and drain
region for conduction.Channel is developed in substrate or body region and it is of opposite type.
ii.p-channel MOSFET
In this type of MOSFET the channel present if of p-type material which connects source and drain
region for conduction. Channel is developed in substrate or body region and it is of opposite type.

By Pramil Paudel and Bikal Adhikari

100 Transistors

b.On the basis of presence or absence of channel

i.Enhancement MOSFET(E-MOSFET):
In this type of MOSFET the channel is initially absent.It has to be created by applying gate voltage.
This kind of MOSFET operate in Enhancement mode only.Again E-MOSFET can be of two type
namely n-channel E-MOSFET and p-channel E-MOSFET.

ii.Depletion MOSFET(D-MOSFET):
In this type of MOSFET the channel is already present.This type of MOSFET can operate in both
enhancement mode and depletion mode.This is because channel can be enhanced and depleted by
applying proper gate voltage.D-MOSFET are also of two types namely n-channel D-MOSFET and p-
channel D-MOSFET.
Construction of n-channel enhancement MOSFET(E-MOSFET):

Fig:Physical structure of n-channel E-MOSFET

Figure shows n-channel E-MOSFET.Whole transistor is fabricatrd on p-type substrate .It is on this
substrate other structures are developed.Two heavily doped n+ and n+ regions are developed on the
surface of substrate and are called source and drain respectively.Like JFET MOSFET is also a
symmetrical device.A thin layer of silicon dioxide is developed on the surface of the substrate.Here
oxide layer acts as an excellent insulator and separates the gate electrode from substrate (or body).
Thus four terminals arise from source,drain,gate and body respectively.These terminals
are marked as S,D,G and B.

By Bikal Adhikari and Pramil Paudel

 Transistors 101
Working:

When VGS=0 i.e when no gate voltage is applied ,two back to back pn junction diodes exist in series
between drain and source.One diode is formed by the p-type substrate with n+ source region and
other diode is formed by p-type substrate with n+ drain region.These two back to back diodes will
prevent the flow of current between source and drain.Infact,the region between source and drain
has very high resistance which is of the order of 1012 KΩ.
When VGS is positive ,at first instance ,the holes in the substrate near the gate electrode are repelled
and are pushed downward in the substrate leaving behind a carrier depletion region.The depletion
region is populated by bound negative charge associated with acceptor atoms .These charge are
uncovered because the neutralizing holes are pushed downwards in the substrate region.The
positive gate voltage attracts the electrons from drain and source as well.Thus under gate electrode
n-region is formed which connects the source and drain.This region is called channel .Due to positive
voltage,a channel is enhanced and hence the name.The value of VGS at which the channel is induced
is called Threshold Voltage and it is designated as Vt.Once when the channel is created the current
can flow through channel which is controlled by drain to source voltage VDS.Thus by varying the
voltage VDS the drain current ID flowing through the channel can be varied.Being symmetrical
device,the source current of MOSFET IS is equal to drain current ID.

D D

G G

S S

Fig:Symbols for p-channel and n-channel E-MOSFET

Characterstics of E-MOSFET:
For the proper operation of enhancement n channel MOSFET gate is always positive with respect to
source and drain source voltage is such that the flow of charge carriers is from source to drain.

By Pramil Paudel and Bikal Adhikari

102 Transistors

D ID
IG=0

G
S VDS
VGS IS=ID

Fig: n-channel E-MOSFET biased for operation

a.Transfer characterstics of E-MOSFET:

The graphical relationship between gate to source voltage VGS and drain current ID is known as
transfer characterstics.

ID

ID(ON)

VGS

Vt VGS(ON)

Fig:Transfer charactrerstics of n-channel E-MOSFET

The transfer characterstics curve is modelled by the equation,
= ( − )
Where,
( )
=
( ) −
The value of ID(ON) and VGS(ON),Vt are provided in the data sheet of E-MOSFET.

b.Drain characterstics of n-channel E-MOSFET:

The graphical relationship between the drain current ID and drain to source voltage VDS at constant
gate to source voltage VGS is called as drain characterstics.

By Bikal Adhikari and Pramil Paudel

 Transistors 103

Fig:Drain characterstics of n-channel E-MOSFET

P-channel E-MOSFET:
The construction of p-channel E-MOSFET is similar to that of n-channel E-MOSFET except that the
transistor is fabricatd on n-type substrate with p+ regions for source and drain.Thus,the channel
induced is of p-type.The device operates in the same manner as the n-channel device except VGS and
VDS are negative and threshold voltage Vt is also negative.

D ID
IG=0
+
G VDS
+ S
VGS IS=ID -
-

Depletion type MOSFET(D-MOSFET):

The structure of the depletion type MOSFET ie D-MOSFET(DMOS) is similar to that of E-MOSFET
with one major difference and that is D-MOSFET has physically implanted channel whice means the
channel is already present.D-MOSFET can be of two types ie n-channel D-MOSFET and p-channel D-
MOSFET.Thus,a n-channel depletion type MOSFET has the n-type silicon region connecting the n+
source region and n+ drain regions on the top of the p-type substrate. Thus if a voltage VDS (drain to
source voltage) is applied the current ID will flow for VGS (gate to source voltage)=0.In other words,
there is no need to induce a channel unlike n-channel E-MOSFET.Depletion type MOSFET can
operate in two modes:
i)Enhancement mode:
In this mode VGS is positive for n channel DMOSand -ve for p channel DMOS.As a result the channel
width is increased and more current can flow through the channel.Thus, channel is said to be
enhanced and this mode of operation is called as a enhancement mode.
ii)Depletion mode:

By Pramil Paudel and Bikal Adhikari

104 Transistors

In this mode VGS is negative(+ve for P channel device).As a result the channel width is decreased
because the electrons from channel are repelled to p-type substrate region and less current can flow
through the channel . Here, the channel is said to be depleted and this mode of operation is called as
depletion mode.

Symbols for D-MOSFET:

D D

G G

S S

Fig:Symbols for p-channel and n-channel D-MOSFET

Characterstics of D-MOSFET:
The characterstics of D-MOSFET is similar to that of JFET except that D-MOSFET can operate in both
the enhancement mode and depletion mode.

D ID
IG=0

G
S VDS
VGS IS=ID

a)Transfer characterstics :
It is the graph of ID vs VGS.

depletion mode Enhancement mode

IDSS

= 1−
( )
-VGS(V)
VGS(V)
-VGS(off)

By Bikal Adhikari and Pramil Paudel

 Transistors 105

b)Drain characterstics:
It is the graph of ID Vs VDS

Fig:Drain characterstics for n-channel D-MOSFET

Complementary Metal Oxide Semiconductor(CMOS):
Complementary Metal Oxide Semiconductor(CMOS) is a semiconductor device which employs MOS
transistors of complementary type i.e. PMOS and NMOS for the circuit design.In CMOS,PMOS and
NMOS transistors are developed in the same substrate.Though CMOS are difficult to fabricate as
compared to that of PMOS and NMOS,the availability of CMOS makes the design of powerful circuits
possible.At present CMOS technology is most widely used technology for designing digital circuits
and has taken over many applications which were possible only with bipolar transistors in the past.

The figure shows the cross section of CMOS device to show how both PMOS and NMOS transistors
are utilized to form CMOS.One can easily observe that NMOS transistor is implemented directly in
the p-type substrate whereas the PMOS transistor is fabricated in specially created n region known
as n-well.Two devices are insulated from each other by a thick region of oxide layer.

By Pramil Paudel and Bikal Adhikari

106 Transistors

MOSFET as logic circuits:

a.NMOS as NOT gate:
VDD

Truth Table:

Vin =
Q
0 1
1 0
Y

vin Q1

Due to positive gate voltage transistor Q is always on.

When Vin is high the gate voltage of transistor Q1 is positive.As a result transistor Q1 conducts and
acts as a short circuit and connect output terminal to ground.Thus,output becomes low.
When Vin is low the gate voltage of transistor Q1 is zero.As a result transistor Q1 does not conduct
and acts as an open circuit .The connection between supply and ground is broken and output
terminal comes in connection with supply voltage.Thus,output becomes high.
b.NMOS as AND gate:
VDD Truth Table:

Inputs Outputs
Q
A B Y=A.B
0 0 0
0 1 0
A Q1 1 0 0
1 1 1

B Q2

Y=A.B

Due to positive gate voltage transistor Q is always on.

When A=0,B=0 the gate voltage for both transistors is zero and both transistors will not conduct and
act as an open circuit.The supply voltage cannot come in contact with output terminal.Thus output
will be low.
When A=0,B=1 and A=1,B=0 Still one of the transitor will not conduct due to zero gate voltage and
act as an open cirucit .Again supply voltage cannot come in contact with output terminal .Thus
output will be low.
When A=1,B=1 the gate voltage for both transistors is positive and both transistors will act as a short
circuit.As a result supply voltage comes in contact with output terminal.Thus,output will be high.

By Bikal Adhikari and Pramil Paudel

 Transistors 107
c.NMOS as OR gate:

VDD Truth Table:

Inputs Outputs
Q
A B Y=A+B
0 0 0
0 1 1
1 0 1
1 1 1
A Q1 B Q2

Y=A+B

Due to positive gate voltage transistor Q is always on.

When A=0,B=0 the gate voltage for both transistors is zero and both transistors will not conduct and
act as an open circuit.The supply voltage cannot come in contact with output terminal.Thus output
will be low.
When A=0,B=1 and A=1,B=0 one of the transitor will conduct due to positive gate voltage and act as
short circuit.The supply voltage comes in contact with output terminal and output becomes high.
When A=1,B=1 the gate voltage for both transistors is positive and both transistors will conduct and
act as a short circuit.The supply voltage comes in contact with output terminal and output becomes
high.

d.NMOS as NAND gate:

VDD

Truth Table:

Q Inputs Outputs
A B = .
Y=A. B 0 0 1
0 1 1
A Q1
1 0 1
1 1 0

B Q2

By Pramil Paudel and Bikal Adhikari

108 Transistors

e.NMOS as NOR gate:

VDD

Q
Truth Table:

Y=A + B Inputs Outputs

A B Y=A + B
0 0 1
A Q1 B Q2
0 1 0
1 0 0
1 1 0

As said in BJT logic circuit discussion readers are requested to understand the operation of NAND
gate and NOR gate using NMOS themselves.

CMOS as logic circuits:

CMOS is a device which employs MOS transistors of both types(complementary types) i.e both
PMOS and NMOS in the circuit design.The question may arise that why CMOS uitilizing both PMOS
and NMOS is preferred when NMOS is sufficient to implement any logic circuits.This is because
practically it is found that performance of circuits using CMOS is very good as compared to those
implemented utilizing MOS transistors and BJTs.

a.CMOS as an invertor or NOT gate:

VDD Truth Table:

A =

Q1 0 1
1 0
A Y=A

Q2

When A=0,PMOS transistor will conduct but NMOS transistor doesnot.In this case PMOS transistor
will conduct and supply violtage VDD appears at output terminal and thus output becomes high.
When A=1,NMOS transistor will conduct and act as short circuit connecting output terminal and
ground.Thus the output will be low.

By Bikal Adhikari and Pramil Paudel

 Transistors 109

b.CMOS as NOR gate:

Truth Table:
VDD
Inputs Outputs
A Q1
A B = + ⃑
0 0 1
0 1 0
1 0 0
B Q2 1 1 0

Y= + ⃑

Q3 Q4

The NOR gate using CMOS can be constructed using configuration as shown above.In the above
circuit,two PMOS transistors are connected in series whereas two NMOS transistors are connected
in parallel.The input at PMOS transistor is also connected to the input of corresponding NMOS
transistor.
When A=0,B=0 both NMOS transistors will be off and both PMOS transistor will be on.Two PMOS
transistors will conduct and the supply voltage VDD will appear across the output terminal.As a
result,output will be high.
When A=0,B=1 and A=1,B=0 one of two NMOS transistors will be on and will act as a short circuit.As
a result output terminal connects to ground.Thus output will be low.
When A=1,B=1 both NMOS transistors will be on and act as a short circuit.As a result output terminal
connects to ground.Thus output will be low.
c.CMOS as NAND gate:
VDD

Truth Table:

Inputs Outputs
Q4
A Q1 B A B = . ⃑
0 0 1
0 1 1
1 0 1
1 1 0
Q2
Y= . ⃑

Q3

By Pramil Paudel and Bikal Adhikari

110 Transistors

The NAND gate using CMOS can be constructed using configuration as shown above.In the above
circuit,two PMOS transistors are connected in parallel whereas two NMOS transistors are connected
in series.The input at PMOS transistor is also connected to the input of corresponding NMOS
transistor.
When A=0,B=0 both NMOS transistors will be off and both PMOS transistors will be on.Two PMOS
transistors will conduct and act as a short circuit.As a result supply will be connected to output
terminal.Thus output will be high.
When A=0,B=1 and A=1,B=0 one of the two PMOS transistors will be on and will act as a short circuit
connecting supply to output terminal.Thus output will be high.
When A=1,B=1 both PMOS transistor will be off and act as an open circuit and both NMOS
transistors will be on and act as a short circuit.The connection between supply and output terminal
is broken and the connection between output terminal and ground is established.Thus the output
will be low.
Numericals:
Common Base Configuration:
1.In Common Base connection IE=1mA IC=0.95mA.Calculate the value of IB.
Solution:
= +
∴ = − = 1 − 0.95 = 0.05
2.In common Base connection current amplification factor is 0.9.If the emitter current is 1
mA,determine the value of base current.
Solution:
=0.9
IE=1mA
In CB connection,
IC= IE
= −
∴ = − = (1 − ) = (0 − 0.9) ∗ 1 = 0.1

3.In a common Base connection IC=0.95mA and IB=0.05mA.Find the value of .

Solution:
= + = 0.05 + 0.95 = 1
.
∴ = = = 0.95
4.In a common base connection,the emitter current is 1 mA.If the emitter circuit is open collector
current is 50µA.Find the total collector current.Given that =0.92
Solution:
IE=1mA
ICBO=50µA
=0.92
We know,
= +
∴ = 0.92 ∗ 1 + 50 ∗ 10 = 0.97

5.In a common Base connection =0.95 . The voltage drop across 2K resistance which is connected
in the collector is 2V.Find the base current.
Solution:

By Bikal Adhikari and Pramil Paudel

 Transistors 111
IE IC

IB
RC=2K

VBB VCB

= =1
∴ = = = 1.053
.
∴ = − = 1.053 − 1 = 0.053
6.For the common base circuit shown in figure,determine IC and VCB.Assume the transistor to be of
silicon.

Solution:
RE=1.5K IE IC Since transistor is made from silicon,VBE=0.7V
Applying KVL in the emitter base loop.We
get.
= +
IB RC=1.2K
− 8 − 0.7
= = = 4.86
1.5
∴ ≈ = 4.86
VCC=18V Applying KVL in collector base loop
VEE=8V
= +
∴ = − = 18 − 4.86 ∗ 1.2
= 12.16

Common Emitter Configuration:

7.Find the value of β if =0.9
Solution:
We know,
=
.
∴ = = =9
.
8.Calculate IE in the transistor for which β=50 and IB=20µA
Solution:
= 20μ
∴ = = 50 ∗ 20 = 1000μ
We know,
= +
∴ = 20 + 1000 = 1020μ = 1.02
9.Find the rating of the transistor shown in the figure.Hence determine the value of IC using both
and β.

By Pramil Paudel and Bikal Adhikari

112 Transistors

IC
IB=240µA

β=49

IE=12mA

Solution:
= = = 0.98
The value of IC can be found by using either or β rating as
= = 0.98 ∗ 12 = 11.76
OR
= = 49 ∗ 240μ = 11.76
10.For a transistor β=45 and voltage drop across 1K which is connected in the collector circuit is 1
volt.Find the base current for common emitter configuration.
Solution:
β=45
RC=1K

IC
1
= =1
1
Now,
IB
RC=1K 1V =
1
∴ = = = 0.022
45
IE

VBB VCC

11.A transistor is connected in common emitter configuration in which collector supply is 8V and
voltage drop across resistance RC is 0.5V.Find the
i.Collector emitter voltage
ii.base current
if the value of RC=800Ω and =0.96
Solution:

By Bikal Adhikari and Pramil Paudel

 Transistors 113
IC
Solution:
i. = − 0.5 =8-0.5=7.5V
.
ii. = = = 0.625
IB
RC=800Ω 0.5V Now,
0.625 0.625 ∗ (1 − 0.96)
∴ = = =
0.96
IE 1−
= 0.026

VBB VCC=8V

12.For a certain transistor IB=20µA,IC=2mA,β=80.Calculate ICBO.

Solution:
= +
, 2 = 80 ∗ 0.02 +
∴ = 2 − 80 ∗ 0.02 = 0.4
Now,
= = = 0.988
Again,
∴ = (1 − ) = (1 − 0.988) ∗ 0.4 = 0.0048
13.Determine VCB in the transistor circuit shown in the figure.The transistor is of silicon and has
β=150.
IC
Solution:
Applying KVL in base emitter
loop.We get,
− − =0
IB RB=10K RC=100Ω − 5 − 0.7
β=150 ∴ = =
10
= 0.43
IE ∴ = = 150 ∗ 0.43
= 64.5

VBB=5V VCC=10V
Now,applying KVL in collector emitter loop.We get,
= +
64.5
∴ = − = 10 − ∗ 100 = 3.55
1000
Also,
= +
3.55 = + 0.7
∴ = 2.85

By Pramil Paudel and Bikal Adhikari

114 Transistors

Load Line Analysis,operating point and Biasing:

14.For the figure shown below draw the DC load line.
IC

IB

RC=2.5K
IE
No Signal

VBB VCC=12.5V

Solution:The collector emitter voltage is given by:

= −
When IC=0
VCE=VCC=12.5V
When VCE=0
.
= = =5
.
Thus DC load line can be obtained by joining the points (0,5) and (12.5,0) on the graph VCE Vs IC.
IC(mA)

5mA

VCE(Volts)
12.5V
15.In the circuit diagram shown below if VCC=12V and RC=6K,draw the dc load line.What will be Q
point if zero signal base current is 20µA and β=50.

IC

IB

RC=6K

No Signal IE

VBB VCC=12V

Solution:
Collector emitter voltage VCE is given by:
= −
When IC=0
By Bikal Adhikari and Pramil Paudel
 Transistors 115
VCE=VCC=12V
When VCE=0
= = =2
Thus DC load line can be obtained by joining the points (0,2) and (12,0) on the graph VCE Vs IC.
When input signal is zero.
IB=20µA=0.02mA
β=50
= =1
∴ = − = 12 − ∗ 6 ∗ 1000 = 6
∴operating point(VCEQ,ICQ)=(6V,1mA)
IC(mA)

2mA

Q(6V,1mA)
1mA

VCE(Volts)

6V 12V

16.For the figure shown below β=100,draw the DC load line and determine operating point.
VCC=6V
We have ,
IB = −
When IC=0
VCE=VCC=6V
RC=2K When VCE=0

RB=530K IC = = =3
Vout Applying KVL at input loop,
Vin − − =0
Cout .
∴ = = = 0.01
Cin ∴ = = 100 ∗ 0.01 = 1
Applying KVL at output loop,
− − =0
∴ = − =6−1∗2=4

By Pramil Paudel and Bikal Adhikari

116 Transistors

IC
3mA

Q(4V,1mA)
1mA

VCE

4V 6V

17.Design a base resistor bias circuit for a CE amplifier such that the operating point is VCE=8V and
IC=2mA with supply voltage of 15V and β=100.Calculate the value of load resistance that could be
employed.
Solution:
VCC=15V IC=2mA
VCE=8V
IB Applying KVL at output circuit,
= +
, = = = 3.5
RC=3.5K
Again,
RB=715K
IC=2mA = = = mA
Vout
Cout Applying KVL for input loop,
Vin = +
β=100 .
Cin = = = 715

18.For the circuit shown below β=75,draw load line and determine Q-point.
VCC=16V Solution:
For load line,
IB = − ( + )
When IC=0
VCE=VCC=16V
RC=2K
RB=430K When VCE=0
IC
Vout = = = 5.33
Cout Applying KVL at input loop,
Vin
− − − =0
Cin , − = +

RE=1k , − = + ( + 1)
.
IE ∴ = = =
( ) ∗
0.030
∴ = = 75 ∗ 0.030 = 2.25

By Bikal Adhikari and Pramil Paudel

 Transistors 117
Applying KVL at output loop,
− − − =0
, = − ( + ) (∵ ≈ )
∴ = 16 − 2.25 ∗ 3 = 9.25

IC

5.33mA

Q(9.25V,2.25mA

2.25mA
mA
VCE

9.25V 16V
19.For the given circuit if β=120,draw load line and determine Q-point.

VCC=20V Solution:
For load line,
= −( + )
= − (∵ + ≈ )
RC=4.7 When IC=0
RB=680K VCE=VCC=20V
IB+IC
When VCE=0
IB IC = = = 4.26
.

Vout Applying KVL in input loop,

Vin −( + ) − − =0
Cout
, − − − = 0(∵ +
= )
Cin , − = +
, − = ( + 1) + (∵ =
( + 1) )
.
∴ =( )
= = 15.45μ
∗ .
∴ = = 120 ∗ 15.45μ = 1.854
Applying KVL at output loop,
−( + ) − =0
∴ = − (∵ ( + ) ≈
= 20 − 1.854 ∗ 4.7 = 11.29

By Pramil Paudel and Bikal Adhikari

118 Transistors

IC

4.26mA

Q(11.29V,1.854mA)

1.854mA

VCE

11.29V 20V

20.Draw the DC load line and determine the operating point for the circuit given below.Given β=75.
Use approximate method.

Solution:
VCC=15V For load line,
= − ( + )
When IC=0
VCE=VCC=15V
When VCE=0
RC=1K
IC Vout = = =5
R1=10K
The voltage across resistor R2 is given by:
Vin ∗ ∗
Cout =( )
= =5
Applying KVL in the loop I
Cin IE − − =0
R2=5K Loop I ∴ =
RE=2K
∴ = (∵ ≈ )
.
∴ = = 2.15
Applying KVL in output loop,
− − − =0
∴ = − ( + ) (∵ ≈ )
= 15 − 2.15 ∗ 3 = 8.55

By Bikal Adhikari and Pramil Paudel

 Transistors 119
IC
5mA

Q(8.55V,2.15mA)

2.15mA

VCE

8.55V 15V
21.Draw the DC load line and determine the operating point for the circuit given below.Given that
β=75.Use actual method(Thevenin’s method)

VCC=15V

RC=1K Solution:
R1=10K For load line,
IC Vout
= − ( + )
When IC=0
Cout VCE=VCC=15V
Vin
When VCE=0
Cin
IE = = =5
R2=5K
RE=2K

For operating point,

The above circuit can be drawn as
VCC

R1 RC
∴ = //
a ∴ = 10//5 =3.33K
∗ 15 ∗ 5
∴ = = =5
VCC IE + 10 + 5
R2
RE

b
Rth

Replacing the left portion with thevenin equivalent circuit.i.e. Vth in series with Rth.

By Pramil Paudel and Bikal Adhikari

120 Transistors

VCC

Applying KVL in base emitter loop.We get,

RC = + +
.
IB IC ∴ = = = 0.02768
Rth ( ) . ∗
∴ = = 75 ∗ 0.02768 = 2.1
Applying KVL in output loop,
IE − − − =0
Vth ∴ = − ( + )
RE = 15 − 2.1 ∗ 3 = 8.7

IC

5mA

Q(8.7V,2.15mA)

2.15mA

VCE

8.7V 15V

By Bikal Adhikari and Pramil Paudel