Scribd
Upload
455 views2 pages

Scan Insertion Lab Observations

The document describes observations from a scan insertion lab experiment on a design with 1 clock domain containing DFFs and latches. Two scan chains were inserted. Key observations include: the design had 2 clock domains and 1 reset, 54 scanable flops and 2 non-scan latches, the chains were of length 26 and 28 cells each, and scan insertion required adding 5 new pins but no inverters or muxes.

Uploaded by

senthilkumar
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
455 views2 pages

Scan Insertion Lab Observations

The document describes observations from a scan insertion lab experiment on a design with 1 clock domain containing DFFs and latches. Two scan chains were inserted. Key observations include: the design had 2 clock domains and 1 reset, 54 scanable flops and 2 non-scan latches, the chains were of length 26 and 28 cells each, and scan insertion required adding 5 new pins but no inverters or muxes.

Uploaded by

senthilkumar
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 2

VLSIGURU DFT TRAINING SCAN INSERTION LAB OBSERVATIONS

SCAN INSERTION LAB OBSERVATIONS


Test Case 5: -
Problem Definition: - Design has 1 clock domain with DFFs and latches and insert 2 scan
chains
Inputs: -

 Synthesis Netlist
 Library Model
 Dofile commands
Outputs: -

 Scan inserted Netlist


 ATPG Dofile
 ATPG Testproc
 Scan Def
What is issue? We have to insert two scan chains
How resolved? insert test logic -number 2
Observations: -
1) Write block diagram with all DFT inputs?

FastClk

ProcClk
Reset
Top Design: IdmaRd
Input Scan channel Output Scan channel
Scan_En
Scan_chain Input1 chainout1
Scan_chain Input2 chainout2

2) How many clock domains? ProcClk, FastClk


3) How many resets? Reset
4) Number of scan chains 2 scan chains

Vlsiguru Confidential 1
VLSIGURU DFT TRAINING SCAN INSERTION LAB OBSERVATIONS

5) Clock mixing or not clock mixing? Not clock mixing


6) How many Lockup-latches are added during scan insertion? zero
7) Is it top-down or bottom up approach? Top-down approach
8) How many terminal lockup latches are added? zero
9) Number of scan flops and non-scan flops in the design? 54 scanable flops and 2 non-
scan elements as latch
10) Chain length? 2(total 54 memory elements)
domain[0] #cells:26, #chains:1
domain[1] #cells:28, #chains:2
11)Number of DRC violations? C8,C9,D5

12) Log file: - please note your observations from the log file
Top module is IdmaRd
Number of shift registers =0
Number of INV inserted =0
Number of MUX inserted =0
No of no scan memory element =56
No of non scan memory element converted to scanable =54
Number of new Pins inserted= 5 (2 scan inputs, 2 scan outputs, scan_en )

Vlsiguru Confidential 2

You might also like