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L5: Simple Sequential Circuits and Verilog

The document discusses sequential circuits and Verilog. It covers: 1) The differences between latches, registers, and flip-flops and their usage. Registers are built using latches but latches are not used directly in designs. 2) Key aspects of sequential circuit timing like clock edges and hold times. 3) How to describe edge-triggered circuits using always blocks with sensitivity lists and how this determines synchronous vs asynchronous behavior. 4) The differences between blocking and non-blocking assignments and why non-blocking should be used for sequential logic.

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Kadal Chaitra
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0% found this document useful (0 votes)
76 views25 pages

L5: Simple Sequential Circuits and Verilog

The document discusses sequential circuits and Verilog. It covers: 1) The differences between latches, registers, and flip-flops and their usage. Registers are built using latches but latches are not used directly in designs. 2) Key aspects of sequential circuit timing like clock edges and hold times. 3) How to describe edge-triggered circuits using always blocks with sensitivity lists and how this determines synchronous vs asynchronous behavior. 4) The differences between blocking and non-blocking assignments and why non-blocking should be used for sequential logic.

Uploaded by

Kadal Chaitra
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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L5: Simple Sequential Circuits and Verilog

Acknowledgements: Nathan Ickes and Rex Min

L5: 6.111 Spring 2004 Introductory Digital Systems Laboratory 1


Key Points from L4 (Sequential Blocks)
Classification:
„ Latch: level sensitive (positive latch passes input to output on high phase, hold
value on low phase)
„ Register: edge-triggered (positive register samples input on rising edge)
„ Flip-Flop: any element that has two stable states. Quite often Flip-flop also used
denote an (edge-triggered) register

D Q D Q Positive
Positive D Q D Q
Latch Register

Clk Clk

„ Latches are used to build Registers (using the Master-Slave Configuration), but
are almost NEVER used by itself in a standard digital design flow.
„ Quite often, latches are inserted in the design by mistake (e.g., an error in your
Verilog code). Make sure you understand the difference between the two.
„ Several types of memory elements (SR, JK, T, D). We will most commonly use
the D-Register, though you should understand how the different types are built
and their functionality.

L5: 6.111 Spring 2004 Introductory Digital Systems Laboratory 2


Key Points from L4 : System Timing
CLout

In
D Q
Combinational D Q
Logic

Clk Clk

CLK
Th Th
IN
Tsu Tsu
Tcq Tcq
FF1
Tlogic
Tcq,cd Tcq,cd
CLout
Tl,cd Tsu

T > Tcq + Tlogic + Tsu Tcq,cd + Tlogic,cd > Thold


L5: 6.111 Spring 2004 Introductory Digital Systems Laboratory 3
The Sequential always Block

„ Edge-triggered circuits are described using a sequential


always block
Combinational Sequential
module combinational(a, b, sel, module sequential(a, b, sel,
out); clk, out);
input a, b; input a, b;
input sel; input sel, clk;
output out; output out;
reg out; reg out;
always @ (a or b or sel) always @ (posedge clk)
begin begin
if (sel) out = a; if (sel) out <= a;
else out = b; else out <= b;
end end
endmodule endmodule

a 1 a 1
out D Q out
b 0 b 0

sel sel clk

L5: 6.111 Spring 2004 Introductory Digital Systems Laboratory 4


Importance of the Sensitivity List
„ The use of posedge and negedge makes an always block sequential
(edge-triggered)
„ Unlike a combinational always block, the sensitivity list does
determine behavior for synthesis!
D Flip-flop with synchronous clear D Flip-flop with asynchronous clear
module dff_sync_clear(d, clearb,
module dff_async_clear(d, clearb, clock, q);
clock, q);
input d, clearb, clock;
input d, clearb, clock; output q;
output q; reg q;
reg q;
always @ (posedge clock) always @ (negedge clearb or posedge clock)
begin begin
if (!clearb) q <= 1'b0; if (!clearb) q <= 1’b0;
else q <= d; else q <= d;
end end
endmodule
endmodule
always block entered only at always block entered immediately
each positive clock edge when (active-low) clearb is asserted
Note: The following is incorrect syntax: always @ (clear or negedge clock)
If one signal in the sensitivity list uses posedge/negedge, then all signals must.

ƒ Assign any signal or variable from only one always block, Be


wary of race conditions: always blocks execute in parallel
L5: 6.111 Spring 2004 Introductory Digital Systems Laboratory 5
Simulation

ƒ DFF with Synchronous Clear

tc-q
Clear on Clock Edge
ƒ DFF with Asynchronous Clear

Clear happens on falling edge of clearb

L5: 6.111 Spring 2004 Introductory Digital Systems Laboratory 6


Blocking vs. Nonblocking Assignments
„ Verilog supports two types of assignments within always blocks, with
subtly different behaviors.
„ Blocking assignment: evaluation and assignment are immediate
always @ (a or b or c)
begin
x = a | b; 1. Evaluate a | b, assign result to x
y = a ^ b ^ c; 2. Evaluate a^b^c, assign result to y
z = b & ~c; 3. Evaluate b&(~c), assign result to z
end

„ Nonblocking assignment: all assignments deferred until all right-hand


sides have been evaluated (end of simulation timestep)
always @ (a or b or c)
begin
x <= a | b; 1. Evaluate a | b but defer assignment of x
y <= a ^ b ^ c; 2. Evaluate a^b^c but defer assignment of y
z <= b & ~c; 3. Evaluate b&(~c) but defer assignment of z
end 4. Assign x, y, and z with their new values

„ Sometimes, as above, both produce the same result. Sometimes, not!

L5: 6.111 Spring 2004 Introductory Digital Systems Laboratory 7


Assignment Styles for Sequential Logic

Flip-Flop Based q1 q2
in D Q D Q D Q out
Digital Delay
Line
clk

„ Will nonblocking and blocking assignments both produce


the desired result?
module nonblocking(in, clk, out); module blocking(in, clk, out);
input in, clk; input in, clk;
output out; output out;
reg q1, q2, out; reg q1, q2, out;
always @ (posedge clk) always @ (posedge clk)
begin begin
q1 <= in; q1 = in;
q2 <= q1; q2 = q1;
out <= q2; out = q2;
end end
endmodule endmodule

L5: 6.111 Spring 2004 Introductory Digital Systems Laboratory 8


Use Nonblocking for Sequential Logic

always @ (posedge clk) always @ (posedge clk)


begin begin
q1 <= in; q1 = in;
q2 <= q1; q2 = q1;
out <= q2; out = q2;
end end

“At each rising clock edge, q1, q2, and out “At each rising clock edge, q1 = in.
simultaneously receive the old values of in, After that, q2 = q1 = in.
q1, and q2.” After that, out = q2 = q1 = in.
Therefore out = in.”

q1 q2 q1 q2
in D Q D Q D Q out in D Q out

clk clk

„ Blocking assignments do not reflect the intrinsic behavior of multi-stage


sequential logic
„ Guideline: use nonblocking assignments for sequential
always blocks
L5: 6.111 Spring 2004 Introductory Digital Systems Laboratory 9
Simulation

ƒNon-blocking Simulation

ƒBlocking Simulation

L5: 6.111 Spring 2004 Introductory Digital Systems Laboratory 10


Use Blocking for Combinational Logic
module blocking(a,b,c,x,y);
Blocking Behavior abc xy input a,b,c;
output x,y;
(Given) Initial Condition 110 11 a x reg x,y;
a changes;
b
always @ (a or b or c)
always block triggered 010 11 y begin
c x = a & b;
x = a & b; 010 01 y = x | c;
y = x | c; end
010 00
endmodule

Nonblocking Behavior abc xy Deferred module nonblocking(a,b,c,x,y);


input a,b,c;
(Given) Initial Condition 110 11 output x,y;
reg x,y;
a changes;
always block triggered 010 11 always @ (a or b or c)
begin
x <= a & b; 010 11 x<=0 x <= a & b;
y <= x | c;
y <= x | c; 010 11 x<=0, y<=1 end
Assignment completion 010 01 endmodule

„ Nonblocking and blocking assignments will synthesize correctly. Will both


styles simulate correctly?
„ Nonblocking assignments do not reflect the intrinsic behavior of multi-stage
combinational logic
„ While nonblocking assignments can be hacked to simulate correctly (expand
the sensitivity list), it’s not elegant
„ Guideline: use blocking assignments for combinational always blocks
L5: 6.111 Spring 2004 Introductory Digital Systems Laboratory 11
The Asynchronous Ripple Counter
Count [3:0]
A simple counter architecture Count[0] Count[1] Count[2] Count[3]
† uses only registers
(e.g., 74HC393 uses T-register and D Q D Q D Q D Q
negative edge-clocking) Q Q Q Q
† Toggle rate fastest for the LSB
…but ripple architecture leads to
large skew between outputs Clock
D register set up to
always toggle: i.e., T
Register with T=1
Skew

Count [3]
Count [2]
Count [1]
Count [0]
Clock

L5: 6.111 Spring 2004 Introductory Digital Systems Laboratory 12


The Ripple Counter in Verilog
Single D Register with Asynchronous Clear:
module dreg_async_reset (clk, clear, d, q, qbar);
input d, clk, clear;
Count [3:0]
output q, qbar; Count[0] Count[1] Count[2] Count[3]
reg q;
D Q D Q D Q D Q
always @ (posedge clk or negedge clear)
begin Q Q Q Q
if (!clear) Countbar[3]
q <= 1'b0;
else q <= d; Countbar[0] Countbar[1] Countbar[2]
end Clock
assign qbar = ~q;
endmodule
Structural Description of Four-bit Ripple Counter:

module ripple_counter (clk, count, clear);


input clk, clear;
output [3:0] count;
wire [3:0] count, countbar;

dreg_async_reset bit0(.clk(clk), .clear(clear), .d(countbar[0]),


.q(count[0]), .qbar(countbar[0]));
dreg_async_reset bit1(.clk(countbar[0]), .clear(clear), .d(countbar[1]),
.q(count[1]), .qbar(countbar[1]));
dreg_async_reset bit2(.clk(countbar[1]), .clear(clear), .d(countbar[2]),
.q(count[2]), .qbar(countbar[2]));
dreg_async_reset bit3(.clk(countbar[2]), .clear(clear), .d(countbar[3]),
.q(count[3]), .qbar(countbar[3]));

endmodule

L5: 6.111 Spring 2004 Introductory Digital Systems Laboratory 13


Simulation of Ripple Effect

L5: 6.111 Spring 2004 Introductory Digital Systems Laboratory 14


Logic for a Synchronous Counter
„ Count (C) will retained by a D Register
„ Next value of counter (N) computed by combinational logic

C3 C2 C1 N3 N2 N1 C3 C3
0 0 0 0 0 1 N1 1 1 1 1 N2 0 1 1 0
0 0 1 0 1 0
C1 0 0 0 0
C1 1 0 0 1
0 1 0 0 1 1
0 1 1 1 0 0 C2 C2
C3
1 0 0 1 0 1 N3 0 0 1 1
1 0 1 1 1 0
1 1 0 1 1 1 C1 0 1 0 1

1 1 1 0 0 0 C2

C1 C2 C3

N1 := C1 D Q D Q D Q

N2 := C1 C2 + C1 C2 CLK
:= C1 xor C2

N3 := C1 C2 C3 + C1 C3 + C2 C3
:= C1 C2 C3 + (C1 + C2 ) C3
:= (C1 C2) xor C3
From [Katz93], See Chapter 7 for different counters
L5: 6.111 Spring 2004 Introductory Digital Systems Laboratory 15
The 74163 Catalog Counter

„ Synchronous Load and Clear Inputs 7 P


10 T 163
„ Positive Edge Triggered FFs 15
2 CLK RCO
„ Parallel Load Data from D, C, B, A 6 11
D QD
5 C QC 12
„ P, T Enable Inputs: both must be asserted 4 13
B QB
to enable counting 3 A QA 14
„ Ripple Carry Output (RCO): asserted when 9 LOAD
counter value is 1111 (conditioned by T); 1 CLR
used for cascading counters

74163 Synchronous
4-Bit Upcounter
Synchronous CLR and LOAD
If CLRb = 0 then Q <= 0
Else if LOADb=0 then Q <= D
Else if P * T = 1 then Q <= Q + 1
Else Q <= Q

L5: 6.111 Spring 2004 Introductory Digital Systems Laboratory 16


Inside the 74163 (Courtesy TI) -
Operating Modes
CLR = 0, LOAD = 0: CLR = 1, LOAD = 0:
Clear takes precedence Parallel load from DATA

0 0
0 1
0 0
0 1
0 DA DA

0 DB DB

0 DC DC

0 DD
DD
0

L5: 6.111 Spring 2004 Introductory Digital Systems Laboratory 17


‘163 Operating Modes - II

CLR = 1, LOAD = 1, P T = 0: CLR = 1, LOAD = 1, P T = 1:


Counting inhibited Count enabled

1 1
0 0
1 1 1
1
0 0
0 QA NA

0 0
QB NB
0

0 0
QC NC
0

0 0
QD ND

0 1

L5: 6.111 Spring 2004 Introductory Digital Systems Laboratory 18


Verilog Code for ‘163

„ Behavioral description of the ‘163 counter:


7 P
module counter(LDbar, CLRbar, P, T, CLK, D, 10 T 163
count, RCO); 15
2 CLK RCO
input LDbar, CLRbar, P, T, CLK;
6 D QD 11
input [3:0] D; 5 12
C QC
output [3:0] count; 4 B QB 13
output RCO; 3 A QA 14
reg [3:0] Q; 9 LOAD
1 CLR
always @ (posedge CLK) begin
if (!CLRbar) Q <= 4'b0000;
priority logic for
else if (!LDbar) Q <= D;
else if (P && T) Q <= Q + 1;
control signals
end

assign count = Q;
RCO gated
assign RCO = Q[3] & Q[2] & Q[1] & Q[0] & T;
by T input
endmodule

L5: 6.111 Spring 2004 Introductory Digital Systems Laboratory 19


Simulation

Notice the glitches on RCO!

L5: 6.111 Spring 2004 Introductory Digital Systems Laboratory 20


Output Transitions

„ Any time multiple bits change, the counter output needs time to
settle.
„ Even though all flip-flops share the same clock, individual bits
will change at different times.
† Clock skew, propagation time variations
„ Can cause glitches in combinational logic driven by the counter
„ The RCO can also have a glitch.

Care is required of the 111 101


Ripple Carry Output:
It can have glitches:
011 010 110 100
Any of these transition
paths are possible!
001 000

L5: 6.111 Spring 2004 Introductory Digital Systems Laboratory 21


Cascading the 74163: Will this Work?

VDD bits 0-3 bits 4-7 bits 8-11

T QA QB QC QD T QA QB QC QD T QA QB QC QD

P ‘163 RCO P ‘163 RCO P ‘163 RCO


CL LD DA DB DC DD CL LD DA DB DC DD CL LD DA DB DC DD

VDD
CLK

„ ‘163 is enabled only if P and T are high


„ When first counter reaches Q = 4’b1111, its RCO goes high
for one cycle
„ When RCO goes high, next counter is enabled (P T = 1)

So far, so good...then what’s wrong?

L5: 6.111 Spring 2004 Introductory Digital Systems Laboratory 22


Incorrect Cascade for 74163

Everything is fine up to 8’b11101111:


VDD 0 0 0 0
1 1 1 1 0 1 1 1
T QA QB QC QD T QA QB QC QD T QA QB QC QD
1 0
P ‘163 RCO P ‘163 RCO P ‘163 RCO
CL LD DA DB DC DD CL LD DA DB DC DD CL LD DA DB DC DD

VDD
CLK

Problem at 8’b11110000: one of the RCOs is now stuck high for 16 cycles!
VDD 0 0 0 0
0 0 0 0 1 1 1 1
T QA QB QC QD T QA QB QC QD T QA QB QC QD
1
0
P ‘163 RCO P ‘163 RCO P ‘163 RCO
CL LD DA DB DC DD CL LD DA DB DC DD CL LD DA DB DC DD

VDD
CLK

L5: 6.111 Spring 2004 Introductory Digital Systems Laboratory 23


Correct Cascade for 74163

Master enable
P QA QB QC QD P QA QB QC QD

T RCO T RCO
CL LD DA DB DC DD CL LD DA DB DC DD

„ P input takes the master enable


„ T input takes the ripple carry

assign RCO = Q[3] & Q[2] & Q[1] & Q[0] & T;

L5: 6.111 Spring 2004 Introductory Digital Systems Laboratory 24


Summary

„ Use blocking assignments for combinational


always blocks
„ Use non-blocking assignments for sequential
always blocks
„ Synchronous design methodology usually used in
digital circuits
† Single global clocks to all sequential elements
† Sequential elements almost always of edge-triggered
flavor (design with latches can be tricky)
„ Today we saw simple examples of sequential
circuits (counters)

L5: 6.111 Spring 2004 Introductory Digital Systems Laboratory 25

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