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TLC555-Q1
SLFS078B – OCTOBER 2006 – REVISED OCTOBER 2015

TLC555-Q1 LinCMOS™ TIMER

1 Features 3 Description
•
1 Qualified for Automotive Applications The TLC555-Q1 is a monolithic timing circuit
fabricated using the TI LinCMOS™ process. The
• Very Low Power Consumption timer is fully compatible with CMOS, TTL, and MOS
– 1 mW (Typical) at VDD = 5 V logic and operates at frequencies up to 2 MHz.
• Capable of Operation in Astable Mode Because of its high input impedance, this device uses
smaller timing capacitors than those used by the
• CMOS Output Capable of Swinging Rail to Rail
NE555. As a result, more accurate time delays and
• High-Output-Current Capability oscillations are possible. Power consumption is low
– Sink 100 mA (Typical) across the full range of power-supply voltage.
– Source 10 mA (Typical) Like the NE555, the TLC555-Q1 has a trigger level
• Output Fully Compatible With CMOS, TTL, and equal to approximately one-third of the supply voltage
MOS and a threshold level equal to approximately two-
thirds of the supply voltage. These levels can be
• Low Supply Current Reduces Spikes During
altered by use of the control voltage terminal (CONT).
Output Transitions
• Single-Supply Operation From 2 V to 15 V When the trigger input (TRIG) falling below the trigger
level sets the flip-flop, and the output goes high.
• Functionally Interchangeable With the NE555; Having TRIG above the trigger level and the
Has Same Pinout threshold input (THRES) above the threshold level
resets the flip-flop, and the output is low. The reset
2 Applications input (RESET) can override all other inputs, and a
• Precision Timing possible use is to initiate a new timing cycle. RESET
going low resets the flip-flop, and the output is low.
• Pulse Generation Whenever the output is low, a low-impedance path
• Sequential Timing exists between the discharge terminal (DISCH) and
• Time Delay Generation GND. Tie all unused inputs to an appropriate logic
level to prevent false triggering.
• Pulse Width Modulation
• Pulse Position Modulation Device Information(1)
• Linear Ramp Generators PART NUMBER PACKAGE BODY SIZE (NOM)
• Automotive Lamp/LED Lighting TLC555-Q1 SOIC (8) 4.90 mm × 3.91 mm
• Telematics (1) For all available packages, see the orderable addendum at
the end of the data sheet.
Pulse Width Modulator
Pulse Width Modulator Waveform:
Top Waveform - Modulation
GND VCC VS
Bottom Waveform - Output Voltage
0.1 µF RA
TRIG
TRIG DISCH

OUT
OUT THRES
C
tH
TLC555-Q1

RESET RESET CONT Modulation Input

(VS)

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
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SLFS078B – OCTOBER 2006 – REVISED OCTOBER 2015 www.ti.com

Table of Contents
1 Features .................................................................. 1 8.1 Overview ................................................................... 8
2 Applications ........................................................... 1 8.2 Functional Block Diagram ......................................... 8
3 Description ............................................................. 1 8.3 Feature Description................................................... 8
8.4 Device Functional Modes........................................ 11
4 Revision History..................................................... 2
5 Description (continued)......................................... 3 9 Application and Implementation ........................ 13
9.1 Application Information............................................ 13
6 Pin Configuration and Functions ......................... 3
9.2 Typical Applications ................................................ 13
7 Specifications......................................................... 4
10 Power Supply Recommendations ..................... 18
7.1 Absolute Maximum Ratings ...................................... 4
7.2 ESD Ratings.............................................................. 4 11 Layout................................................................... 18
11.1 Layout Guidelines ................................................. 18
7.3 Recommended Operating Conditions....................... 4
11.2 Layout Example .................................................... 19
7.4 Thermal Information .................................................. 4
7.5 Electrical Characteristics: VDD = 5 V......................... 5 12 Device and Documentation Support ................. 20
7.6 Electrical Characteristics: VDD = 15 V....................... 6 12.1 Community Resource............................................ 20
7.7 Operating Characteristics.......................................... 6 12.2 Trademarks ........................................................... 20
7.8 Dissipation Ratings ................................................... 7 12.3 Electrostatic Discharge Caution ............................ 20
7.9 Typical Characteristics .............................................. 7 12.4 Glossary ................................................................ 20
8 Detailed Description .............................................. 8 13 Mechanical, Packaging, and Orderable
Information ........................................................... 20

4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision A (October 2012) to Revision B Page

• Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section ................................................................................................. 1

Changes from Original (October 2006) to Revision A Page

• Changed next-to-last paragraph in Description and Ordering Information section ................................................................ 1

• In the 5-V and 15-V Electrical Characteristics tables, changed all "MAX" entries in the TA column to "Full range" ............. 5
• Deleted the last Electrical Characteristics table, which contained only redundant data ........................................................ 6

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5 Description (continued)
The advantage of the TLC555-Q1 is that it exhibits greatly reduced supply-current spikes during output
transitions. Although the CMOS output is capable of sinking over 100 mA and sourcing over 10 mA, the main
reason the TLC555-Q1 is able to have low current spikes is due to its edge rates. This minimizes the need for
the large decoupling capacitors required by the NE555.
The TLC555-Q1 is characterized for operation over the full automotive temperature range of –40°C to 125°C.

6 Pin Configuration and Functions

D Package
8-Pin SOIC
Top View

GND 1 8 VDD
TRIG 2 7 DISCH
OUT 3 6 THRES
RESET 4 5 CONT

Pin Functions
PIN
I/O DESCRIPTION
NAME NO.
CONT 5 I/O Controls comparator thresholds, Outputs 2/3 VDD, allows bypass capacitor connection
DISCH 7 O Open collector output to discharge timing capacitor
GND 1 — Ground
OUT 3 O High current timer output signal
RESET 4 I Active low reset input forces output and discharge low
THRES 6 I End of timing input. THRES > CONT sets output low and discharge low
TRIG 2 I Start of timing input. TRIG < ½ CONT sets output high and discharge open
VDD 8 — Input supply voltage, 2 V to 15 V

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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN MAX UNIT
VDD Supply voltage (2) 18 V
VI Input voltage Any input –0.3 VDD V
Sink current, discharge or output 150 mA
IO Source current, output 15 mA
See Dissipation
Continuous total power dissipation
Ratings
TA Operating free-air temperature –40 125 °C
Tstg Storage temperature –65 150 °C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to network GND.

7.2 ESD Ratings

VALUE UNIT
(1)
Human-body model (HBM), per AEC Q100-002 ±1000
All pins ±500
V(ESD) Electrostatic discharge Charged-device model (CDM), per AEC V
Q100-011 Corner pins (1, 4, 5, and
±750
8)

(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

7.3 Recommended Operating Conditions

MIN MAX UNIT
VDD Supply voltage 2 15 V
TA Operating free-air temperature –40 125 °C

7.4 Thermal Information

TLC555-Q1
(1)
THERMAL METRIC D (SOIC) UNIT
8 PINS
RθJA Junction-to-ambient thermal resistance 113.7 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 58 °C/W
RθJB Junction-to-board thermal resistance 54.5 °C/W
ψJT Junction-to-top characterization parameter 11.1 °C/W
ψJB Junction-to-board characterization parameter 53.9 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance N/A °C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.

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7.5 Electrical Characteristics: VDD = 5 V

VDD = 5 V, at specified free-air temperature (unless otherwise noted)
TEST (1)
PARAMETER TA MIN TYP MAX UNIT
CONDITIONS
25°C 2.8 3.3 3.8
VIT Threshold voltage V
Full range 2.7 3.9
25°C 10
IIT Threshold current pA
Full range 5000
25°C 1.36 1.66 1.96
VI(TRIG) Trigger voltage V
Full range 1.26 2.06
25°C 10
II(TRIG) Trigger current pA
Full range 5000
25°C 0.4 1.1 1.5
VI(RESET) Reset voltage V
Full range 0.3 1.8
25°C 10
II(RESET) Reset current pA
Full range 5000
Control voltage (open-circuit)
as a percentage of supply Full range 66.7%
voltage
Discharge-switch on-state 25°C 0.14 0.5
IOL = 10 mA V
voltage Full range 0.6
Discharge-switch off-state 25°C 0.1
nA
current Full range 120
25°C 4.1 4.8
VOH High-level output voltage IOH = –1 mA V
Full range 4.1
25°C 0.21 0.4
IOL = 8 mA
Full range 0.6
25°C 0.13 0.3
VOL Low-level output voltage IOL = 5 mA V
Full range 0.45
25°C 0.08 0.3
IOL = 3.2 mA
Full range 0.4
25°C 170 350
IDD Supply current (2) μA
Full range 700

(1) Full-range TA is –40°C to 125°C.

(2) These values apply for the expected operating configurations in which THRES is connected directly to DISCH or TRIG.

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7.6 Electrical Characteristics: VDD = 15 V

VDD = 15 V, at specified free-air temperature (unless otherwise noted)
TEST (1)
PARAMETER TA MIN TYP MAX UNIT
CONDITIONS
25°C 9.45 10 10.55
VIT Threshold voltage V
Full range 9.35 10.65
25°C 10
IIT Threshold current pA
Full range 5000
25°C 4.65 5 5.35
VI(TRIG) Trigger voltage V
Full range 4.55 5.45
25°C 10
II(TRIG) Trigger current pA
Full range 5000
25°C 0.4 1.1 1.5
VI(RESET) Reset voltage V
Full range 0.3 1.8
25°C 10
II(RESET) Reset current pA
Full range 5000
Control voltage (open-circuit) as
Full range 66.7%
a percentage of supply voltage
Discharge-switch on-state 25°C 0.77 1.7
IOL = 100 mA V
voltage Full range 1.8
Discharge switch off-state 25°C 0.1
nA
current Full range 120
25°C 12.5 14.2
IOH = –10 mA
Full range 12.5
25°C 13.5 14.6
VOH High-level output voltage IOH = –5 mA V
Full range 13.5
25°C 14.2 14.9
IOH = –1 mA
Full range 14.2
25°C 1.28 3.2
IOL = 100 mA
Full range 3.8
25°C 0.63 1
VOL Low-level output voltage IOL = 50 mA V
Full range 1.5
25°C 0.12 0.3
IOL = 10 mA
Full range 0.45
25°C 360 600
IDD Supply current (2) μA
Full range 1000

(1) Full-range TA is –40°C to 125°C.

(2) These values apply for the expected operating configurations in which THRES is connected directly to DISCH or TRIG.

7.7 Operating Characteristics

VDD = 5 V, TA = 25°C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
(1) VDD = 5 V to 15 V, CT = 0.1 μF,
Initial error of timing interval 1% 3%
RA = RB = 1 kΩ to 100 kΩ (2)
VDD = 5 V to 15 V, CT = 0.1 μF,
Supply voltage sensitivity of timing interval 0.1 0.5 %/V
RA = RB = 1 kΩ to 100 kΩ (2)
tr Output pulse rise time RL = 10 MΩ, CL = 10 pF 20 75 ns
tf Output pulse fall time RL = 10 MΩ, CL = 10 pF 15 60 ns
fmax Maximum frequency in astable mode RA = 470 Ω, CT = 200 pF, RB = 200 Ω (2) 1.2 2.1 MHz

(1) Timing interval error is defined as the difference between the measured value and the average value of a random sample from each
process run.
(2) RA, RB, and CT are as defined in Figure 1.

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7.8 Dissipation Ratings

TA ≤ 25°C DERATING FACTOR TA = 125°C
PACKAGE
POWER RATING ABOVE TA = 25°C POWER RATING
D 725 mW 5.8 mW/°C 145 mW

7.9 Typical Characteristics

100 600

t PHL , t PLH − Propagation Delay Times − ns

70 IO(on) ≥1 mA
VDD = 2 V, IO = 1 mA
CL ≈0
Discharge Switch On-State Resistance − W

500 TA = 25°C
40

VDD = 5 V, IO = 10 mA
20 400

VDD = 15 V, IO = 100 mA
10 300
7

200 tPHL
4

2 100
tPLH
(see Note A)
1
−75 − 50 − 25 0 25 50 75 100 125 0
0 2 4 6 8 10 12 14 16 18 20
TA − Free-Air Temperature − °C
VDD − Supply Voltage − V
The effects of the load resistance on these values must be taken into
account separately.

Figure 1. Discharge Switch ON-State Resistance vs Figure 2. Propagation Delay Times to Discharge Output
Free-Air Temperature from Trigger and Threshold Shorted Together vs Supply
Voltage

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8 Detailed Description

8.1 Overview
The TLC555-Q1 timer is used for general purpose timing applications from 476 ns to hours or from < 1 mHz to
2.1 MHz.

8.2 Functional Block Diagram

CONT RESET
5 4
VDD
8

R
6 R1
THRES 3
R 1 OUT

S
R

2
TRIG

R
7
DISCH
1
GND
RESET can override TRIG, which can override THRES.

8.3 Feature Description

8.3.1 Mono-stable Operation
For mono-stable operation, any of these timers can be connected as shown in Figure 3. If the output is low,
application of a negative-going pulse to the trigger (TRIG) sets the flip-flop (Q goes low), drives the output high,
and turns off Q1. Capacitor C then is charged through RA until the voltage across the capacitor reaches the
threshold voltage of the threshold (THRES) input. If TRIG has returned to a high level, the output of the threshold
comparator resets the flip-flop (Q goes high), drives the output low, and discharges C through Q1.
VDD
(5 V to 15 V)

RA 5 8
CONT VDD RL
4
RESET
7
DISCH
3
OUT Output
6
THRES
2
Input TRIG
GND
1

Figure 3. Circuit for Monostable Operation

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Feature Description (continued)

Monostable operation is initiated when TRIG voltage falls below the trigger threshold. Once initiated, the
sequence ends only if TRIG is high for at least 10 µs before the end of the timing interval. When the trigger is
grounded, the comparator storage time can be as long as 10 µs, which limits the minimum monostable pulse
width to 10 µs. Because of the threshold level and saturation voltage of Q1, the output pulse duration is
approximately tw = 1.1RAC. Figure 4 is a plot of the time constant for various values of RA and C. The threshold
levels and charge rates both are directly proportional to the supply voltage, VCC. The timing interval is, therefore,
independent of the supply voltage, so long as the supply voltage is constant during the time interval.
Applying a negative-going trigger pulse simultaneously to RESET and TRIG during the timing interval discharges
C and reinitiates the cycle, commencing on the positive edge of the reset pulse. The output is held low as long
as the reset pulse is low. To prevent false triggering, when RESET is not used, it should be connected to VCC.

10
RA = 9.1 kW RA = 10 MW
CL= 0.01mF
RL = 1 kW
See Figure 9 1
RA = 1 MW

tw − Output Pulse Duration − s

10−1
Input Voltage
Voltage − 2 V/div

10−2

10−3
RA = 100 kW
Output Voltage
RA = 10 kW
10−4

RA = 1 kW

Capacitor Voltage 10−5

0.001 0.01 0.1 1 10 100
Time − 0.1 ms/div C − Capacitance − mF
Figure 4. Typical Monostable Waveforms Figure 5. Output Pulse Duration vs Capacitance

8.3.2 A-stable Operation

As shown in Figure 6, adding a second resistor, RB, to the circuit of and connecting the trigger input to the
threshold input causes the timer to self-trigger and run as a multi-vibrator. The capacitor C charges through RA
and RB and then discharges through RB only. Therefore, the duty cycle is controlled by the values of RA and RB.
This astable connection results in capacitor C charging and discharging between the threshold-voltage level (≈
0.67 × VCC) and the trigger-voltage level (≈ 0.33 × VCC). As in the mono-stable circuit, charge and discharge
times (and, therefore, the frequency and duty cycle) are independent of the supply voltage.

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Feature Description (continued)

VDD
RA = 5 kW RL = 1 kW
(5 V to 15 V)
RB = 3 kW See Figure 12
C = 0.15 mF
0.01 mF
Open

Voltage − 1 V/div
(see Note A) 5 8
RA
CONT VDD
4 RL
RESET
7
DISCH 3
OUT Output
RB 6
THRES t
H
2
TRIG tL Output Voltage
GND
C 1

Capacitor Voltage
NOTE A: Decoupling CONT voltage to ground with a capacitor can
improve operation. This should be evaluated for individual
applications. Time − 0.5 ms/div
Figure 6. Circuit for A-stable Operation Figure 7. Typical A-stable Waveforms
tc(L)
tc(H)

VDD
tPHL

2/3 VDD

1/3 VDD

GND
tPLH
Figure 8. Trigger and Threshold Voltage Waveform
Figure 8 shows typical waveforms generated during astable operation. The output high-level duration tH and low-
level duration tL can be calculated as follows:
tH = 0.693 (R A + RB )C (1)
tL = 0.693 (RB )C (2)
Other useful relationships are shown below:
period = tH + tL = 0.693 (R A + 2RB )C (3)
1.44
frequency »
(R A +2RB )C (4)
tL RB
Output driver duty cycle = =
tH + tL R A + 2RB (5)
tH RB
Output waveform duty cycle = = 1-
tH + tL R A + 2RB (6)
t RB
Low-to-high ratio = L =
tH R A + RB (7)

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Feature Description (continued)

100 k
RA + 2 RB = 1 kW
RA + 2 RB = 10 kW
10 k

f − Free-Running Frequency − Hz
RA + 2 RB = 100 kW

1k

100

10

1
RA + 2 RB = 1 MW

RA + 2 RB = 10 MW
0.1
0.001 0.01 0.1 1 10 100
C − Capacitance − mF

Figure 9. Free-Running Frequency

8.3.3 Frequency Divider

By adjusting the length of the timing cycle, the basic circuit of Figure 11 can be made to operate as a frequency
divider. Figure 10 shows a divide-by-three circuit that makes use of the fact that re-triggering cannot occur during
the timing cycle.

VCC = 5 V
RA = 1250 W
C = 0.02 mF
See Figure 9
Voltage − 2 V/div

Input Voltage

Output Voltage

Capacitor Voltage

Time − 0.1 ms/div

Figure 10. Divide-by-Three Circuit Waveforms

8.4 Device Functional Modes

Table 1 shows the device functional modes.

Table 1. Function Table

RESET TRIGGER VOLTAGE (1) THRESHOLD VOLTAGE (1) OUTPUT DISCHARGE SWITCH
Low Irrelevant Irrelevant Low On
High <1/3 VCC Irrelevant High Off
High >1/3 VCC >2/3 VCC Low On
High >1/3 VCC <2/3 VCC As previously established

(1) Voltage levels shown are nominal.

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COMPONENT COUNT

THRES Transistors 39
Resistors 5

V DD

CONT

OUT

DISCH

GND
TRIG RESET

Figure 11. Equivalent Schematic

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9 Application and Implementation

NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.

9.1 Application Information

The TLC555-Q1 timer device uses resistor and capacitor charging delay to provide a programmable time delay
or operating frequency. The following section presents a simplified discussion of the design process.

9.2 Typical Applications

9.2.1 Missing-Pulse Detector
The circuit shown in Figure 12 can be used to detect a missing pulse or abnormally long spacing between
consecutive pulses in a train of pulses. The timing interval of the monostable circuit is re-triggered continuously
by the input pulse train as long as the pulse spacing is less than the timing interval. A longer pulse spacing,
missing pulse, or terminated pulse train permits the timing interval to be completed, thereby generating an output
pulse as shown in Figure 13.
VDD (5 V to 15 V)

4 8 RL RA
Input RESET VDD
3
2 OUT Output
TRIG

7
DISCH

5
CONT 6
0.01 mF THRES
GND C
1

A5T3644

Figure 12. Circuit for Missing-Pulse Detector

9.2.1.1 Design Requirements

Input fault (missing pulses) must be input high. Input stuck low will not be detected because timing capacitor (C)
remains discharged.

9.2.1.2 Detailed Design Procedure

Choose RA and C so that RA× C > [maximum normal input high time]. RL improves VOH, but it is not required for
TTL compatibility.

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Typical Applications (continued)

9.2.1.3 Application Curve
VDD = 5 V
RA = 1 kW
C = 0.1 mF
See Figure 15

Voltage − 2 V/div
Input Voltage

Output Voltage

Capacitor Voltage

Time − 0.1 ms/div

Figure 13. Completed Timing Waveforms for Missing-Pulse Detector

9.2.2 Pulse-Width Modulation

The operation of the timer can be modified by modulating the internal threshold and trigger voltages, which is
accomplished by applying an external voltage (or current) to CONT. Figure 14 shows a circuit for pulse-width
modulation. A continuous input pulse train triggers the monostable circuit, and a control signal modulates the
threshold voltage. Figure 15 shows the resulting output pulse-width modulation. While a sine-wave modulation
signal is shown, any wave shape could be used.
VDD (5 V to 15 V)

RL RA
4 8
RESET VDD
3
Clock 2 OUT Output
TRIG
Input
7
DISCH
Modulation
5
Input CONT 6
(see Note A) THRES
GND
1 C

NOTE A: The modulating signal can be direct or capacitively coupled

to CONT. For direct coupling, the effects of modulation source
voltage and impedance on the bias of the timer should be
considered.

Figure 14. Circuit for Pulse-Width Modulation

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Typical Applications (continued)

9.2.2.1 Design Requirements
Clock input must have VOL and VOH levels that are less than and greater than 1/3 VDD. Modulation input can
vary from ground to VDD. The application must be tolerant of a nonlinear transfer function; the relationship
between modulation input and pulse width is not linear because the capacitor charge is based RC on an negative
exponential curve.

9.2.2.2 Detailed Design Procedure

Choose RA and C so that RA × C = 1/4 [clock input period]. RL improves VOH, but it is not required for TTL
compatibility.

9.2.2.3 Application Curve

RA = 3 kW
C = 0.02 mF
RL = 1 kW
See Figure 18

Modulation Input Voltage

Voltage − 2 V/div

Clock Input Voltage

Output Voltage

Capacitor Voltage

Time − 0.5 ms/div

Figure 15. Pulse-Width-Modulation Waveforms

9.2.3 Pulse-Position Modulation

As shown in Figure 16, any of these timers can be used as a pulse-position modulator. This application
modulates the threshold voltage and, thereby, the time delay, of a free-running oscillator. Figure 17 shows a
triangular-wave modulation signal for such a circuit; however, any wave shape could be used.

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Typical Applications (continued)

VDD (5 V to 15 V)

4 8 RL RA
RESET VDD 3
2 OUT Output
TRIG

7
DISCH
Modulation
RB
Input 5 CONT 6
THRES
(see Note A)
GND
C

NOTE A: The modulating signal can be direct or capacitively coupled

to CONT. For direct coupling, the effects of modulation
source voltage and impedance on the bias of the timer
should be considered.

Figure 16. Circuit for Pulse-Position Modulation

9.2.3.1 Design Requirements

Both DC and AC coupled modulation input will change the upper and lower voltage thresholds for the timing
capacitor. Both frequency and duty cycle will vary with the modulation voltage.

9.2.3.2 Detailed Design Procedure

The nominal output frequency and duty cycle can be determined using formulas in A-stable Operation section. RL
improves VOH, but it is not required for TTL compatibility.

9.2.3.3 Application Curve

RA = 3 kW
RB = 500W
RL = 1 kW
See Figure 20
Voltage − 2 V/div

Modulation Input Voltage

Output Voltage

Capacitor Voltage

Time − 0.1 ms/div

Figure 17. Pulse-Position-Modulation Waveforms

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Product Folder Links: TLC555-Q1

 TLC555-Q1
www.ti.com SLFS078B – OCTOBER 2006 – REVISED OCTOBER 2015

Typical Applications (continued)

9.2.4 Sequential Timer
Many applications, such as computers, require signals for initializing conditions during start-up. Other
applications, such as test equipment, require activation of test signals in sequence. These timing circuits can be
connected to provide such sequential control. The timers can be used in various combinations of astable or
monostable circuit connections, with or without modulation, for extremely flexible waveform control. Figure 18
shows a sequencer circuit with possible applications in many systems, and Figure 19 shows the output
waveforms.
VDD

4 8 RA 33 kW 4 8 RB 33 kW 4 8 RC
RESET VDD RESET VDD RESET VDD
3 3 3
2 OUT 2 OUT 2 OUT
TRIG TRIG TRIG
0.001 0.001
7
S
DISCH
7 mF DISCH 7 mF DISCH
5 5 5
CONT 6 CONT 6 CONT 6
THRES THRES THRES
GND GND GND
0.01 1 0.01 1 0.01 1
CA CB CC
mF mF mF

CA = 10 mF CC = 14.7 mF
RA = 100 kW Output A Output B RC = 100 kW Output C
CB = 4.7mF
RB = 100 kW
NOTE A: S closes momentarily at t = 0.

Figure 18. Sequential Timer Circuit

9.2.4.1 Design Requirements

The sequential timer application chains together multiple mono-stable timers. The joining components are the 33-
kΩ resistors and 0.001-µF capacitors. The output high to low edge passes a 10-µs start pulse to the next
monostable.

9.2.4.2 Detailed Design Procedure

The timing resistors and capacitors can be chosen using this formula. tw = 1.1 × R × C.

Copyright © 2006–2015, Texas Instruments Incorporated Submit Documentation Feedback 17

Product Folder Links: TLC555-Q1
TLC555-Q1
SLFS078B – OCTOBER 2006 – REVISED OCTOBER 2015 www.ti.com

Typical Applications (continued)

9.2.4.3 Application Curve

See Figure 22

twA twA = 1.1 RACA

Output A

twB
Voltage − 5 V/div

twB = 1.1 RBCB

Output B

Output C twC twC = 1.1 RCCC

t=0

t − Time − 1 s/div

Figure 19. Sequential Timer Waveforms

10 Power Supply Recommendations

The TLC555-Q1 requires a voltage supply within 2 V to 15 V. Adequate power supply bypassing is necessary to
protect associated circuitry. Minimum recommended is 0.1 μF in parallel with 1-μF electrolytic. Place the bypass
capacitors as close as possible to the TLC555-Q1 and minimize the trace length.

11 Layout

11.1 Layout Guidelines

Standard PCB rules apply to routing the TLC555-Q1. The 0.1 μF in parallel with a 1-μF electrolytic capacitor
should be as close as possible to the TLC555-Q1. The capacitor used for the time delay should also be placed
as close to the discharge pin. A ground plane on the bottom layer can be used to provide better noise immunity
and signal integrity.

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Product Folder Links: TLC555-Q1

 TLC555-Q1
www.ti.com SLFS078B – OCTOBER 2006 – REVISED OCTOBER 2015

11.2 Layout Example

Figure 20 is the basic layout for various applications.
• C1 – based on time delay calculations
• C2 – 0.01-μF bypass capacitor for control voltage pin
• C3 – 0.1-μF bypass ceramic capacitor
• C4 – 1-μF electrolytic bypass capacitor
• R1 – based on time delay calculations
C4

C3

GND VDD
R1

TLC555-Q1
TRIG DISCH

OUT THRES
C1
RESET CONT

C2
Figure 20. Recommended Layout

Copyright © 2006–2015, Texas Instruments Incorporated Submit Documentation Feedback 19

Product Folder Links: TLC555-Q1
TLC555-Q1
SLFS078B – OCTOBER 2006 – REVISED OCTOBER 2015 www.ti.com

12 Device and Documentation Support

12.1 Community Resource

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.

12.2 Trademarks
LinCMOS, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
12.3 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.

12.4 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

20 Submit Documentation Feedback Copyright © 2006–2015, Texas Instruments Incorporated

Product Folder Links: TLC555-Q1

 PACKAGE OPTION ADDENDUM

www.ti.com 21-Aug-2015

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) (6) (3) (4/5)

TLC555QDRQ1 ACTIVE SOIC D 8 2500 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 125 TL555Q
& no Sb/Br)

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 21-Aug-2015

OTHER QUALIFIED VERSIONS OF TLC555-Q1 :

• Catalog: TLC555
• Military: TLC555M

NOTE: Qualified Version Definitions:

• Catalog - TI's standard catalog product

• Military - QML certified for Military and Defense Applications

Addendum-Page 2
 PACKAGE OUTLINE
D0008A SCALE 2.800
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT

SEATING PLANE
.228-.244 TYP
[5.80-6.19]
.004 [0.1] C
A PIN 1 ID AREA
6X .050
[1.27]
8
1

.189-.197 2X
[4.81-5.00] .150
NOTE 3 [3.81]

4X (0 -15 )

4
5
8X .012-.020
B .150-.157 [0.31-0.51]
.069 MAX
[3.81-3.98] .010 [0.25] C A B [1.75]
NOTE 4

.005-.010 TYP
[0.13-0.25]

4X (0 -15 )

SEE DETAIL A
.010
[0.25]

.004-.010
0 -8 [0.11-0.25]
.016-.050
[0.41-1.27] DETAIL A
(.041) TYPICAL
[1.04]

4214825/C 02/2019

NOTES:

1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.

www.ti.com
 EXAMPLE BOARD LAYOUT
D0008A SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT

8X (.061 )
[1.55]
SYMM SEE
DETAILS
1
8

8X (.024)
[0.6] SYMM

(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE:8X

SOLDER MASK SOLDER MASK

METAL METAL UNDER
OPENING OPENING SOLDER MASK

EXPOSED
METAL EXPOSED
METAL
.0028 MAX .0028 MIN
[0.07] [0.07]
ALL AROUND ALL AROUND

NON SOLDER MASK SOLDER MASK

DEFINED DEFINED

SOLDER MASK DETAILS

4214825/C 02/2019

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com
 EXAMPLE STENCIL DESIGN
D0008A SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT

8X (.061 )
[1.55] SYMM

1
8

8X (.024)
[0.6] SYMM

(R.002 ) TYP
5 [0.05]
4
6X (.050 )
[1.27]
(.213)
[5.4]

SOLDER PASTE EXAMPLE

BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X

4214825/C 02/2019

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.

www.ti.com
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