AMD Confidential – Advance Information

Socket AM3 Processor

Functional Data Sheet

Publication # 40778
Revision: 1.13
Issue Date: January 2009

Advanced Micro Devices

 AMD Confidential – Advance Information

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 AMD Confidential – Advance Information
PID: 40778 Rev. 1.13 – January 2009 Socket AM3 Processor Functional Data Sheet

Contents

Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1 Pins ..............................................................7
1.1 Connection Diagram (Left Half) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.2 Connection Diagram (Right Half) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
1.3 Pin Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
1.4 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
1.5 Alphabetical Pin List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
1.6 Color-Coded Connection Diagram (Left Half) . . . . . . . . . . . . . . . . . . . . . . . 18
1.7 Color-Coded Connection Diagram (Right Half) . . . . . . . . . . . . . . . . . . . . . . 19
2 Package Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.1 Mechanical Loading for Lidded Parts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.2 Package Insertions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.3 Package Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Contents 3
 AMD Confidential – Advance Information
PID: 40778 Rev. 1.13 – January 2009 Socket AM3 Processor Functional Data Sheet

List of Figures

Figure 1. Connection Diagram (Left Half) .........................................................................................7

Figure 2. Connection Diagram (Right Half) ......................................................................................8
Figure 3. Color-Coded Connection Diagram (Left Half) .................................................................18
Figure 4. Color-Coded Connection Diagram (Right Half) ...............................................................19
Figure 5. Organic Micro Pin Grid Array Package(UOF): Top, Side, and Bottom Views
(Lidded) .............................................................................................................................21

4 List of Figures
 AMD Confidential – Advance Information
PID: 40778 Rev. 1.13 – January 2009 Socket AM3 Processor Functional Data Sheet

List of Tables

Table 1. Pin Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Table 2. HyperTransport™ Technology Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 3. DDR2 SDRAM Memory Interface Pin Descriptions
(Supports DDR2 and DDR3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 4. Clock Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 5. Thermal Observation/Control Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 6. Power Supply/Voltage Regulator Interface Pin Descriptions . . . . . . . . . . . . . . . . . . . . . 11
Table 7. JTAG Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Table 8. Debug Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Table 9. Miscellaneous Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Table 10. Mechanical Loading for Lidded Parts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 11. Recommended Number of Insertions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

List of Tables 5
 AMD Confidential – Advance Information
PID: 40778 Rev. 1.13 – January 2009 Socket AM3 Processor Functional Data Sheet

Revision History

Date Revision Description

January 2009 1.13 Third NDA release.
• M_VDDIO_PWRGD changed to not supported. (See Table 3 on page 10.)
June 2008 1.11 Second NDA release.
• Added MA/B_EVENT_L pins.
• Added NP/VSS and NP/RSVD pins.
August 2007 1.07 Initial NDA release.

Revision History 6
 AMD Confidential – Advance Information
PID:40778 Rev 1.13 – January 2009 Socket AM3 Processor Functional Data Sheet

1 Pins
1.1 Connection Diagram (Left Half)

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

MB_DATA[1 MB_DATA[6 MB_DATA[2 MB_DATA[8

A VOID VOID VSS VDDNB DBREQ_L VDDNB VSS CLKIN_H VSS TEST25_H VSS VDDR A
] ] ] ]
MB_DATA[7
B VOID NP/ RSVD VDD VSS VDDNB DBRDY VDDNB CLKIN_L VSS TEST25_L VSS VDDR MB_DM[0] VSS VSS B
]
MB_DQS_L[ MB_DQS_H[ MB_DATA[3 MB_DATA[1
C SVC/ VID[3] VDD VSS VDD TEST14 VDDNB RESET_L VDDNB PWROK VDDA TEST29_H VDDR C
0] 0] ] 3]
MB_DATA[0 MB_DATA[1
D VID[4] VID[5] VDD TEST8 VDD TEST17 VDDNB LDTSTOP_L VDDNB VDDA TEST29_L VDDR VSS VSS D
] 2]
PVIEN/ VID[ VDDR_SENS MB_DATA[5 MA_DATA[1 MA_DATA[6 MA_DATA[2
E VID[0] SVD/ VID[2] VDD TEST7 VDD TEST16 VDDNB TEST18 VDDNB VSS E
1] E ] ] ] ]
M_VDDIO_P MB_DATA[4 MA_DQS_H[
F PSI_L RSVD VSS VDD TEST9 VDD TEST15 VDDNB TEST19 VDDNB M_VREF VSS VSS F
WRGD ] 0]
VDDNB_FB_ VDDNB_FB_ CORE_TYP MA_DATA[5 MA_DATA[0 MA_DQS_L[ MA_DATA[7
G VDD_FB_L VDD_FB_H VDD TEST10 VDD VSS VDDNB VSS VDDNB G
L H E ] ] 0] ]
MA_DATA[4
H VLDT_B VLDT_B VOID VOID VLDT_B VLDT_B VDD VSS TEST28_L VSS VDD VSS VSS MA_DM[0] VSS H
]
L0_CADIN_ L0_CADIN_L L0_CADIN_ L0_CADIN_
J VSS VSS VSS VDD VSS TEST28_H VSS VDD VSS VDD VSS VDD J
H[1] [0] H[0] H[8]
L0_CADIN_L L0_CADIN_ L0_CADIN_L L0_CADIN_L
K VSS VSS VDD VSS VDD VSS VDD VSS VDD VSS VDD VSS K
[1] H[9] [9] [8]
L0_CADIN_ L0_CADIN_L L0_CADIN_ L0_CADIN_
L VDD VDD VSS VDD VSS VDD VSS VDD VSS VDD VSS VDD L
H[3] [2] H[2] H[10]
L0_CADIN_L L0_CADIN_ L0_CADIN_L L0_CADIN_L
M VDD VDD VDD VSS VDD VSS VDD VSS VDD VSS VDD VSS M
[3] H[11] [11] [10]
L0_CADIN_ L0_CLKIN_L L0_CLKIN_H L0_CLKIN_H
N VSS VSS VSS VDD VSS VDD VSS VDD VSS VDD VSS VDD N
H[4] [0] [0] [1]
L0_CADIN_L L0_CADIN_ L0_CADIN_L L0_CLKIN_L
P VSS VSS VDD VSS VDD VSS VDD VSS VDD VSS VDD VSS P
[4] H[12] [12] [1]
L0_CADIN_ L0_CADIN_L L0_CADIN_ L0_CADIN_
R VDD VDD VSS VDD VSS VDD VSS VDD VSS VDD VSS VDD R
H[6] [5] H[5] H[13]
L0_CADIN_L L0_CADIN_ L0_CADIN_L L0_CADIN_L
T VDD VDD VDD VSS VDD VSS VDD VSS VDD VSS VDD VSS T
[6] H[14] [14] [13]
L0_CTLIN_H L0_CADIN_L L0_CADIN_ L0_CADIN_
U VSS VSS VSS VDD VSS VDD VSS VDD VSS VDD VSS VDD U
[0] [7] H[7] H[15]
L0_CTLIN_L L0_CTLIN_H L0_CTLIN_L L0_CADIN_L
V VSS VSS HTREF0 HTREF1 VDD VSS VDD VSS VDD VSS VDD VSS V
[0] [1] [1] [15]
L0_CADOUT L0_CTLOUT L0_CTLOUT L0_CTLOUT
W VDD VDD VSS VDD VSS VDD VSS VDD VSS VDD VSS VDD W
_L[7] _H[0] _L[0] _L[1]
L0_CADOUT L0_CADOUT L0_CADOUT L0_CTLOUT
Y VDD VDD VDD VSS VDD VSS VDD VSS VDD VSS VDD VSS Y
_H[7] _L[15] _H[15] _H[1]
L0_CADOUT L0_CADOUT L0_CADOUT L0_CADOUT
AA VSS VSS VSS VDD VSS VDD VSS VDD VSS VDD VSS VDD AA
_L[5] _H[6] _L[6] _L[14]
L0_CADOUT L0_CADOUT L0_CADOUT L0_CADOUT
AB VSS VSS VDD VSS VDD VSS VDD VSS VDD VSS VDD VSS AB
_H[5] _L[13] _H[13] _H[14]
L0_CLKOUT L0_CADOUT L0_CADOUT L0_CADOUT
AC VDD VDD VSS VDD VSS VDD VSS VDD VSS VDD VSS VDD AC
_L[0] _H[4] _L[4] _L[12]
L0_CLKOUT L0_CLKOUT L0_CLKOUT L0_CADOUT MA_DATA[5 MA_DQS_H[
AD VDD VDD VDD VSS VDD VSS VDD VSS VSS VSS AD
_H[0] _L[1] _H[1] _H[12] 9] 7]
L0_CADOUT L0_CADOUT L0_CADOUT L0_CADOUT MA_DATA[5 MA_DATA[6 MA_DQS_L[ MA_DATA[5
AE VSS VSS NP/ VSS VOID VOID VDD VSS VDD AE
_L[2] _H[3] _L[3] _L[11] 8] 3] 7] 6]
L0_CADOUT L0_CADOUT L0_CADOUT L0_CADOUT MB_DATA[5
AF VSS VSS VDD VSS VDD VSS VDD VSS VSS MA_DM[7] VSS AF
_H[2] _L[10] _H[10] _H[11] 9]
L0_CADOUT L0_CADOUT L0_CADOUT L0_CADOUT MB_DATA[5 MA_DATA[6 MA_DATA[5 MA_DATA[6
AG VDD VDD VDD THERMDA THERMDC VSS VSS VDDR AG
_L[0] _H[1] _L[1] _L[9] 8] 2] 7] 1]
L0_CADOUT L0_CADOUT L0_CADOUT L0_CADOUT MB_DATA[6 MB_DATA[5
AH VDD VDD TEST3 TEST23 TEST12 TCK M_ZN VDDR VSS VSS AH
_H[0] _L[8] _H[8] _H[9] 3] 1]
MB_DQS_L[ MB_DATA[6 MB_DATA[5
AJ VLDT_A VLDT_A VLDT_A VLDT_A TEST6 TEST2 TEST13 TEST20 TEST22 TRST_L M_ZP VDDR MB_DM[7] AJ
7] 0] 0]
THERMTRI VDDIO_FB_ MB_DQS_H[ MB_DATA[5
AK VOID VSS RSVD SA[0] TEST26 SID TEST24 TEST27 TDO VDDR VSS VSS AK
P_L H 7] 6]
CPU_PRES PROCHOT_ VDDIO_FB_ MB_DATA[6 MB_DATA[5 MB_DATA[6 MB_DATA[5
AL VOID VOID ALERT_L VSS SIC TEST21 TMS TDI VDDR AL
ENT_L L L 2] 7] 1] 5]

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

Figure 1. Connection Diagram (Left Half)

Pins 7
 AMD Confidential – Advance Information
PID:40778 Rev 1.13 – January 2009 Socket AM3 Processor Functional Data Sheet

1.2 Connection Diagram (Right Half)

17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

MB_DATA[9 MB_CLK_H[ MB_CLK_L[1 MB_DATA[1 MB_DATA[1 MB_DATA[1 MB_DATA[2 MB_DATA[2 MB_DATA[1 MB_DATA[2 MB_DATA[2 MB_DATA[2
A MB_DM[2] VOID VOID A
] 1] ] 4] 0] 6] 2] 3] 9] 8] 4] 5]
MB_RESET_ MB_DATA[1 MB_DATA[1 MB_DATA[1 MB_DATA[2
B MB_DM[1] VSS VSS VSS VSS VSS VSS MA_DM[3] VSS VOID B
L 5] 7] 8] 9]
MB_DQS_L[1 MB_CLK_H[ MB_DATA[1 MB_DATA[2 MB_DQS_L[2 MB_DQS_H[ MA_DQS_H[ MA_DATA[1 MA_DATA[2 MA_DATA[2 MA_DQS_L[3 MB_DQS_L[3
C RSVD RSVD MB_DM[3] C
] 0] 1] 1] ] 2] 2] 8] 8] 5] ] ]
MB_DQS_H[ MB_CLK_L[0 MB_DATA[2 MA_DATA[2 MA_DQS_L[2 MA_DATA[2 MA_DQS_H[ MB_DQS_H[
D VSS VSS VSS VSS VSS VSS VSS D
1] ] 0] 0] ] 9] 3] 3]
MA_DATA[8 MA_DQS_H[ MA_RESET_ MA_DATA[1 MA_DATA[1 MA_DATA[2 MA_DATA[2 MA_DATA[1 MA_DATA[2 MA_DATA[3 MA_DATA[3 MB_DATA[3 MB_DATA[3
E MA_DM[1] MA_DM[2] E
] 1] L 4] 5] 1] 2] 9] 4] 0] 1] 0] 1]
MA_DATA[1 MA_DQS_L[1 MA_DATA[1 MA_DATA[1 MA_DATA[2 MA_DATA[2 MB_DATA[2 MB_DATA[2
F VSS VSS VSS VSS VSS VSS VSS F
3] ] 0] 6] 3] 6] 7] 6]
MA_DATA[1 MA_DATA[9 MA_CLK_H[ MA_CLK_H[ MA_CLK_L[0 MA_DATA[1 MA_DATA[1 MA_DATA[2 MA_CHECK[ MA_CHECK[ MB_CHECK[ MB_CHECK[ MB_CHECK[
G RSVD RSVD G
2] ] 1] 0] ] 1] 7] 7] 4] 5] 4] 5] 0]
MA_DATA[3 MA_CLK_L[1 MA_CHECK[ MA_CHECK[ MB_CHECK[
H VSS NP/ VSS VOID VOID VDD VSS RSVD VSS VSS VSS H
] ] 0] 1] 1]
MA_CHECK[ MA_DQS_L[8 MA_DQS_H[ MB_DQS_L[8 MB_DQS_H[
J VSS VDD VSS VDD VSS VDD VSS VDD MA_DM[8] MB_DM[8] J
6] ] 8] ] 8]
MA_CHECK[ MA_CHECK[ MB_CHECK[ MB_CHECK[
K VDD VSS VDD VSS VDD VSS VDD VSS VSS VSS VSS K
7] 2] 7] 6]
MA_CHECK[ MB_CHECK[ MB_CHECK[
L VSS VDD VSS VDD VSS VDD VSS RSVD RSVD MA_CKE[1] RSVD RSVD L
3] 2] 3]

M VDD VSS VDD VSS VDD VSS VDD VDDIO MA_CKE[0] VDDIO MA_ADD[15] VDDIO MB_CKE[0] VDDIO MB_CKE[1] M

MA_BANK[2 MB_BANK[2
N VSS VDD VSS VDD VSS VDD VSS MA_ADD[14] MA_ADD[12] MA_ADD[9] MB_ADD[15] MB_ADD[14] MB_ADD[12] N
] ]

P VDD VSS VDD VSS VDD VSS VDD VDDIO MA_ADD[11] VDDIO MA_ADD[7] VDDIO MB_ADD[11] VDDIO MB_ADD[9] P

R VSS VDD VSS VDD VSS VDD VSS MA_ADD[8] MA_ADD[6] MA_ADD[5] MA_ADD[4] MB_ADD[7] MB_ADD[8] MB_ADD[5] MB_ADD[6] R

T VDD VSS VDD VSS VDD VSS VDD VDDIO MA_ADD[3] VDDIO MA_ADD[1] VDDIO MB_ADD[3] VDDIO MB_ADD[4] T

MA_CLK_H[ MA_CLK_L[5 MA_CLK_H[ MB_CLK_L[5 MB_CLK_H[

U VSS VDD VSS VDD VSS VDD VSS MA_ADD[2] MB_ADD[1] MB_ADD[2] U
2] ] 5] ] 5]
MA_CLK_L[2 MA_CLK_H[ MB_EVENT MB_CLK_H[
V VDD VSS VDD VSS VDD VSS VDD VDDIO VDDIO VDDIO VDDIO V
] 4] _L 2]
MA_CLK_L[3 MA_CLK_H[ MA_CLK_L[4 MB_CLK_L[4 MB_CLK_H[ MA_EVENT MB_CLK_L[2
W VSS VDD VSS VDD VSS VDD VSS MA_ADD[0] W
] 3] ] ] 4] _L ]
MA_BANK[1 MB_CLK_L[3 MB_CLK_H[
Y VDD VSS VDD VSS VDD VSS VDD VDDIO MA_ADD[10] VDDIO VDDIO VDDIO Y
] ] 3]
MA0_CS_L[0 MA1_CS_L[0 MA_BANK[0 MB_BANK[0 MB_BANK[1
AA VSS VDD VSS VDD VSS VDD VSS MA_RAS_L MB_ADD[10] MB_ADD[0] AA
] ] ] ] ]
MB1_CS_L[0
AB VDD VSS VDD VSS VDD VSS VDD VDDIO MA_CAS_L VDDIO MA_WE_L VDDIO MB_RAS_L VDDIO AB
]
MA0_CS_L[1 MB0_CS_L[0
AC VSS VDD VSS VDD VSS VDD VSS VDDIO MA_ADD[13] MA1_ODT[0] MA0_ODT[0] MB_CAS_L MB_WE_L AC
] ]
MA_DATA[6 MA_DATA[5 MA1_CS_L[1
AD VOID VOID VSS VSS VDD VSS RSVD VDDIO VDDIO MB0_ODT[0] VDDIO MB1_ODT[0] A D
0] 3] ]
MA_DATA[5 MA_DATA[5 MA_CLK_L[6 MA_CLK_H[ MA_DATA[4 MA_DATA[4 MA_DATA[4 MA_DATA[3 MB1_CS_L[1 MB0_CS_L[1
AE RSVD RSVD MA1_ODT[1] MA0_ODT[1] MB_ADD[13] A E
1] 4] ] 6] 8] 3] 6] 6] ] ]
MA_DATA[5 MA_DATA[4 MA_DATA[4 MA_DATA[4 MA_DATA[3 MA_DATA[3
AF VSS MA_DM[6] VSS VSS VSS VSS VSS VDDIO MB0_ODT[1] A F
0] 9] 7] 0] 2] 7]
MA_DATA[5 MA_DQS_H[ MA_DQS_L[6 MA_CLK_L[7 MA_CLK_H[ MA_DATA[5 MA_DATA[4 MA_DQS_H[ MA_DQS_L[5 MA_DATA[4 MA_DQS_H[ MA_DQS_L[4 MA_DATA[3 MB_DATA[3
AG MB1_ODT[1] A G
5] 6] ] ] 7] 2] 2] 5] ] 4] 4] ] 3] 6]
MB_DATA[4 MB_DATA[4 MB_DATA[4 MA_DATA[4 MA_DATA[3 MB_DATA[3
AH MB_DM[6] VSS VSS VSS VSS VSS VSS MA_DM[4] VSS AH
9] 2] 1] 1] 4] 7]
MB_DQS_L[6 MB_CLK_H[ MB_DATA[4 MB_DATA[4 MB_DATA[4 MA_DATA[4 MA_DATA[3 MA_DATA[3 MA_DATA[3 MB_DATA[3 MB_DATA[3
AJ RSVD RSVD MB_DM[5] MA_DM[5] AJ
] 7] 3] 7] 0] 5] 5] 9] 8] 3] 2]
MB_DQS_H[ MB_CLK_L[7 MB_DATA[5 MB_DQS_H[ MB_DATA[4 MB_DATA[3
AK VSS VSS VSS VSS VSS VSS MB_DM[4] VSS VOID AK
6] ] 3] 5] 4] 8]
MB_DATA[5 MB_CLK_L[6 MB_CLK_H[ MB_DATA[4 MB_DATA[5 MB_DATA[4 MB_DQS_L[5 MB_DATA[4 MB_DATA[3 MB_DATA[3 MB_DATA[3 MB_DQS_H[ MB_DQS_L[4
AL VOID VOID AL
4] ] 6] 8] 2] 6] ] 5] 5] 4] 9] 4] ]

17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Figure 2. Connection Diagram (Right Half)

Pins 8
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PID:40778 Rev 1.13 – January 2009 Socket AM3 Processor Functional Data Sheet

1.3 Pin Types

Table 1. Pin Types

Pin Types
I-HT-D Input, HyperTransport™ Technology, Differential
O-HT-D Output, HyperTransport Technology, Differential
B-IO-S Bidirectional, VDDIO, Single-Ended
B-IO-OD Bidirectional, VDDIO, Open Drain
B-IO-D Bidirectional, VDDIO, Differential
I-IO-S Input, VDDIO, Single-Ended
I-IO-D Input, VDDIO, Differential
O-IO-D Output, VDDIO, Differential
O-IO-S Output, VDDIO, Single-Ended
O-IO-OD Output, VDDIO, Open Drain
A Analog
S Supply Voltage
VREF Voltage Reference

1.4 Pin Descriptions

Table 2. HyperTransport™ Technology Pin Descriptions

Signal Name Type Description
L0_CLKIN_H/L[1:0] I-HT-D Link 0 Clock Input
L0_CTLIN_H/L[1:0] I-HT-D Link 0 Control Input
L0_CADIN_H/L[15:0] I-HT-D Link 0 Command/Address/Data Input
L0_CLKOUT_H/L[1:0] O-HT-D Link 0 Clock Outputs
L0_CTLOUT_H/L[1:0] O-HT-D Link 0 Control Output
L0_CADOUT_H/L[15:0] O-HT-D Link 0 Command/Address/Data Outputs
HTREF1 A Compensation Resistor to VLDT
HTREF0 A Compensation Resistor to VSS

Pins 9
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PID:40778 Rev 1.13 – January 2009 Socket AM3 Processor Functional Data Sheet

Table 3. DDR2 SDRAM Memory Interface Pin Descriptions (Supports DDR2 and DDR3)1
Signal Name Type Description
MA_CLK_H/L[7:0],
O-IO-D DRAM Differential Clock
MB_CLK_H/L[7:0]
MA0_CS_L[1:0],
MA1_CS_L[1:0],
O-IO-S DRAM Chip Selects
MB0_CS_L[1:0],
MB1_CS_L[1:0]
MA0_ODT[1:0],
MA1_ODT[1:0],
O-IO-S DRAM Enable Pin for On Die Termination
MB0_ODT[1:0],
MB1_ODT[1:0]
MA_CKE[1:0], MB_CKE[1:0] O-IO-S DRAM Clock Enable
MA_DQS_H/L[8:0],
B-IO-D DRAM Differential Data Strobe
MB_DQS_H/L[8:0]
MA_DATA[63:0],
B-IO-S DRAM Interface Data Bus
MB_DATA[63:0]
MA_DM[8:0], MB_DM[8:0] O-IO-S DRAM Data Mask Bits
MA_CHECK[7:0],
B-IO-S DRAM Interface ECC Check Bits
MB_CHECK[7:0]
MA_RAS_L, MB_RAS_L O-IO-S DRAM Row Address Strobe
MA_CAS_L, MB_CAS_L O-IO-S DRAM Column Address Strobe
MA_WE_L, MB_WE_L O-IO-S DRAM Write Enable
MA_ADD[15:0],
O-IO-S DRAM Column/Row Address
MB_ADD[15:0]
MA_BANK[2:0],
O-IO-S DRAM Bank Address
MB_BANK[2:0]
MA_RESET_L,
O-IO-S DRAM Reset Pin for Suspend-to-RAM Power Management Mode
MB_RESET_L
MA_EVENT_L,
I-IO-S DRAM Thermal Event Status
MB_EVENT_L
M_VREF VREF DRAM Interface Voltage Reference
M_ZP A Compensation Resistor to VSS
M_ZN A Compensation Resistor to VDDIO
M_VDDIO_PWRGD I-IO-S Not Supported
Note:
1. Support for DDR2 or DDR3 depends on platform implementation.

Table 4. Clock Pin Descriptions

Signal Name Type Description
CLKIN_H/L I-IO-D 200-MHz PLL Reference Clock

Pins 10
 AMD Confidential – Advance Information
PID:40778 Rev 1.13 – January 2009 Socket AM3 Processor Functional Data Sheet

Table 5. Thermal Observation/Control Pin Descriptions

Signal Name Type Description
Asserted as an input to force the processor into the HTC-active state or
PROCHOT_L B-IO-OD becomes asserted as an output to indicate when the processor has entered the
HTC-active state.
THERMDA A Anode (+) of the thermal diode
THERMDC A Cathode (–) of the thermal diode
THERMTRIP_L O-IO-OD Thermal Sensor Trip output
SIC I-IO-S Sideband-Temperature Sensor Interface Clock
SID B-IO-OD Sideband-Temperature Sensor Interface Data
Programmable pin that can indicate different events, including a Sideband-
ALERT_L O-IO-S
Temperature Sensor Interface interrupt.
SA[0] I-IO-S Sideband interface address

Table 6. Power Supply/Voltage Regulator Interface Pin Descriptions

Signal Name Type Notes Description
PSI_L O-IO-S Power Status Indicator for the VDD Power Supply regulator. This
signal may be used by the regulator to improve efficiency when the
processor is in low power states.
VDD_FB_H/L A Differential feedback for VDD power supply
VDDNB_FB_H/L A Differential feedback for VDDNB power supply
VDDIO_FB_H/L A Differential feedback for VDDIO power supply
VDDA S Filtered PLL supply voltage
VDD S Core power supply
VDDNB S Northbridge power supply
VDDIO S DDR SDRAM I/O ring power supply
VLDT_A, VLDT_B S HyperTransport™ I/O ring power supply
VDDR S VDDR power supply
VDDR_SENSE A VDDR voltage monitor pin
VSS S Ground
Prior to PWROK assertion, PVIEN/VID[1] signals to the processor
whether the platform supports PVI or SVI operation. After PWROK
PVIEN/VID[1] B-IO-OD 1 assertion, on a platform that implements the parallel VID interface, this
pin is bit 1 of the VID interface. This pin is not used after PWROK
assertion on platforms that implement the serial VID interface.
In platforms supporting SVI, this signal is the serial VID interface data.
SVD/VID[2] B-IO-OD 1 In platforms supporting PVI, this signal is bit 2 of the parallel voltage
ID to the regulator.
In platforms supporting SVI, this signal is the serial VID interface
SVC/VID[3] O-IO-S 1 clock. In platforms supporting PVI, this signal is bit 3 of the parallel
voltage ID to the regulator.
VID[5:4], VID[0] O-IO-S 1 Voltage ID pins to the regulator
Note:
1. The function of this pin is platform implementation dependant. For information on how to connect this pin, please
refer to the appropriate motherboard design guide.

Pins 11
 AMD Confidential – Advance Information
PID:40778 Rev 1.13 – January 2009 Socket AM3 Processor Functional Data Sheet

Table 7. JTAG Pin Descriptions

Signal Name Type Description
TCK I-IO-S JTAG Clock
TMS I-IO-S JTAG Mode Select
TRST_L I-IO-S JTAG Reset
TDI I-IO-S JTAG Data Input
TDO O-IO-S JTAG Data Output

Table 8. Debug Pin Descriptions

Signal Name Type Description
DBREQ_L I-IO-S Debug Request
DBRDY O-IO-S Debug Ready

Table 9. Miscellaneous Pin Descriptions

Signal Name Type Description
CPU_PRESENT_L O-IO-S Indicates a processor is present for a socket. Shorted to VSS on the package.
RESET_L I-IO-S Processor Reset
PWROK I-IO-S Indicates that voltages and input CLKIN have reached specified operation.
HyperTransport™ Technology Stop Control Input. Used for power
LDTSTOP_L I-IO-S
management and for changing HyperTransport link width and frequency.
Indicates that the processor is capable of split Northbridge and core voltage
plane operation. If open, the processor requires a unified core and Northbridge
CORE_TYPE O-IO-S
voltage plane. If shorted to VSS, split core and Northbridge voltage plan
operation is supported.
VOID Missing pins on package and socket used for mechanical keying.
RSVD Reserved pins that should remain unconnected.
NP/VSS Pin is not populated on the package but socket hole connects to ground.
Pin is not populated on the package but socket contains a hole that should remain
NP/RSVD
unconnected.
TEST* Refer to Socket AM3 Motherboard Design Guide, order #40837

Pins 12
 AMD Confidential – Advance Information
PID:40778 Rev 1.13 – January 2009 Socket AM3 Processor Functional Data Sheet

1.5 Alphabetical Pin List

Name Pin Name Pin Name Pin Name Pin
ALERT _L AL4 L0_CADOUT _H[3] AE2 MA_ADD[14] N24 MA_DAT A[18] C26
CLKIN_H A8 L0_CADOUT _H[4] AC2 MA_ADD[15] M27 MA_DAT A[19] E26
CLKIN_L B8 L0_CADOUT _H[5] AB1 MA_ADD[2] U25 MA_DAT A[2] E16
CORE_T YPE G5 L0_CADOUT _H[6] AA2 MA_ADD[3] T 25 MA_DAT A[20] D23
CPU_PRESENT _L AL3 L0_CADOUT _H[7] Y1 MA_ADD[4] R27 MA_DAT A[21] E23
DBRDY B6 L0_CADOUT _H[8] AH5 MA_ADD[5] R26 MA_DAT A[22] E25
DBREQ_L A5 L0_CADOUT _H[9] AH6 MA_ADD[6] R25 MA_DAT A[23] F25
HT REF0 V7 L0_CADOUT _L[0] AG1 MA_ADD[7] P27 MA_DAT A[24] E27
HT REF1 V8 L0_CADOUT _L[1] AG3 MA_ADD[8] R24 MA_DAT A[25] C28
L0_CADIN_H[0] J3 L0_CADOUT _L[10] AF4 MA_ADD[9] N27 MA_DAT A[26] F27
L0_CADIN_H[1] J1 L0_CADOUT _L[11] AE6 MA_BANK[0] AA27 MA_DAT A[27] G26
L0_CADIN_H[10] L6 L0_CADOUT _L[12] AC6 MA_BANK[1] Y27 MA_DAT A[28] C27
L0_CADIN_H[11] M4 L0_CADOUT _L[13] AB4 MA_BANK[2] N25 MA_DAT A[29] D27
L0_CADIN_H[12] P4 L0_CADOUT _L[14] AA6 MA_CAS_L AB25 MA_DAT A[3] H17
L0_CADIN_H[13] R6 L0_CADOUT _L[15] Y4 MA_CHECK[0] H27 MA_DAT A[30] E28
L0_CADIN_H[14] T4 L0_CADOUT _L[2] AE1 MA_CHECK[1] H29 MA_DAT A[31] E29
L0_CADIN_H[15] U6 L0_CADOUT _L[3] AE3 MA_CHECK[2] K27 MA_DAT A[32] AF27
L0_CADIN_H[2] L3 L0_CADOUT _L[4] AC3 MA_CHECK[3] L24 MA_DAT A[33] AG29
L0_CADIN_H[3] L1 L0_CADOUT _L[5] AA1 MA_CHECK[4] G27 MA_DAT A[34] AH27
L0_CADIN_H[4] N1 L0_CADOUT _L[6] AA3 MA_CHECK[5] G28 MA_DAT A[35] AJ27
L0_CADIN_H[5] R3 L0_CADOUT _L[7] W1 MA_CHECK[6] J26 MA_DAT A[36] AE26
L0_CADIN_H[6] R1 L0_CADOUT _L[8] AH4 MA_CHECK[7] K25 MA_DAT A[37] AF29
L0_CADIN_H[7] U3 L0_CADOUT _L[9] AG6 MA_CKE[0] M25 MA_DAT A[38] AJ29
L0_CADIN_H[8] J6 L0_CLKIN_H[0] N3 MA_CKE[1] L27 MA_DAT A[39] AJ28
L0_CADIN_H[9] K4 L0_CLKIN_H[1] N6 MA_CLK_H[0] G20 MA_DAT A[4] H13
L0_CADIN_L[0] J2 L0_CLKIN_L[0] N2 MA_CLK_H[1] G19 MA_DAT A[40] AF25
L0_CADIN_L[1] K1 L0_CLKIN_L[1] P6 MA_CLK_H[2] U24 MA_DAT A[41] AH25
L0_CADIN_L[10] M6 L0_CLKOUT _H[0] AD1 MA_CLK_H[3] W26 MA_DAT A[42] AG23
L0_CADIN_L[11] M5 L0_CLKOUT _H[1] AD5 MA_CLK_H[4] V27 MA_DAT A[43] AE22
L0_CADIN_L[12] P5 L0_CLKOUT _L[0] AC1 MA_CLK_H[5] U27 MA_DAT A[44] AG26
L0_CADIN_L[13] T6 L0_CLKOUT _L[1] AD4 MA_CLK_H[6] AE20 MA_DAT A[45] AJ26
L0_CADIN_L[14] T5 L0_CT LIN_H[0] U1 MA_CLK_H[7] AG21 MA_DAT A[46] AE23
L0_CADIN_L[15] V6 L0_CT LIN_H[1] V4 MA_CLK_L[0] G21 MA_DAT A[47] AF23
L0_CADIN_L[2] L2 L0_CT LIN_L[0] V1 MA_CLK_L[1] H19 MA_DAT A[48] AE21
L0_CADIN_L[3] M1 L0_CT LIN_L[1] V5 MA_CLK_L[2] V24 MA_DAT A[49] AF21
L0_CADIN_L[4] P1 L0_CT LOUT _H[0] W2 MA_CLK_L[3] W25 MA_DAT A[5] G13
L0_CADIN_L[5] R2 L0_CT LOUT _H[1] Y6 MA_CLK_L[4] W27 MA_DAT A[50] AF17
L0_CADIN_L[6] T1 L0_CT LOUT _L[0] W3 MA_CLK_L[5] U26 MA_DAT A[51] AE17
L0_CADIN_L[7] U2 L0_CT LOUT _L[1] W6 MA_CLK_L[6] AE19 MA_DAT A[52] AG22
L0_CADIN_L[8] K6 LDT ST OP_L D8 MA_CLK_L[7] AG20 MA_DAT A[53] AD21
L0_CADIN_L[9] K5 M_VDDIO_PWRGD F3 MA_DAT A[0] G14 MA_DAT A[54] AE18
L0_CADOUT _H[0] AH1 M_VREF F12 MA_DAT A[1] E14 MA_DAT A[55] AG17
L0_CADOUT _H[1] AG2 M_ZN AH11 MA_DAT A[10] F21 MA_DAT A[56] AE16
L0_CADOUT _H[10] AF5 M_ZP AJ11 MA_DAT A[11] G22 MA_DAT A[57] AG15
L0_CADOUT _H[11] AF6 MA_ADD[0] W24 MA_DAT A[12] G17 MA_DAT A[58] AE13
L0_CADOUT _H[12] AD6 MA_ADD[1] T 27 MA_DAT A[13] F17 MA_DAT A[59] AD13
L0_CADOUT _H[13] AB5 MA_ADD[10] Y25 MA_DAT A[14] E21 MA_DAT A[6] E15
L0_CADOUT _H[14] AB6 MA_ADD[11] P25 MA_DAT A[15] E22 MA_DAT A[60] AD17
L0_CADOUT _H[15] Y5 MA_ADD[12] N26 MA_DAT A[16] F23 MA_DAT A[61] AG16
L0_CADOUT _H[2] AF1 MA_ADD[13] AC26 MA_DAT A[17] G23 MA_DAT A[62] AG14

Pins 13
 AMD Confidential – Advance Information
PID:40778 Rev 1.13 – January 2009 Socket AM3 Processor Functional Data Sheet

Name Pin Name Pin Name Pin Name Pin

MA_DAT A[63] AE14 MB_ADD[15] N28 MB_DAT A[19] A26 MB_DAT A[7] B15
MA_DAT A[7] G16 MB_ADD[2] U29 MB_DAT A[2] A15 MB_DAT A[8] A16
MA_DAT A[8] E17 MB_ADD[3] T 29 MB_DAT A[20] D21 MB_DAT A[9] A17
MA_DAT A[9] G18 MB_ADD[4] T 31 MB_DAT A[21] C22 MB_DM[0] B13
MA_DM[0] H15 MB_ADD[5] R30 MB_DAT A[22] A24 MB_DM[1] B17
MA_DM[1] E18 MB_ADD[6] R31 MB_DAT A[23] A25 MB_DM[2] A23
MA_DM[2] E24 MB_ADD[7] R28 MB_DAT A[24] A28 MB_DM[3] C30
MA_DM[3] B29 MB_ADD[8] R29 MB_DAT A[25] A29 MB_DM[4] AK29
MA_DM[4] AH29 MB_ADD[9] P31 MB_DAT A[26] F31 MB_DM[5] AJ23
MA_DM[5] AJ25 MB_BANK[0] AA28 MB_DAT A[27] F29 MB_DM[6] AH17
MA_DM[6] AF19 MB_BANK[1] AA31 MB_DAT A[28] A27 MB_DM[7] AJ14
MA_DM[7] AF15 MB_BANK[2] N31 MB_DAT A[29] B27 MB_DM[8] J29
MA_DM[8] J25 MB_CAS_L AC29 MB_DAT A[3] C15 MB_DQS_H[0] C14
MA_DQS_H[0] F15 MB_CHECK[0] G31 MB_DAT A[30] E30 MB_DQS_H[1] D17
MA_DQS_H[1] E19 MB_CHECK[1] H31 MB_DAT A[31] E31 MB_DQS_H[2] C24
MA_DQS_H[2] C25 MB_CHECK[2] L28 MB_DAT A[32] AJ31 MB_DQS_H[3] D31
MA_DQS_H[3] D29 MB_CHECK[3] L29 MB_DAT A[33] AJ30 MB_DQS_H[4] AL28
MA_DQS_H[4] AG27 MB_CHECK[4] G29 MB_DAT A[34] AL26 MB_DQS_H[5] AK23
MA_DQS_H[5] AG24 MB_CHECK[5] G30 MB_DAT A[35] AL25 MB_DQS_H[6] AK17
MA_DQS_H[6] AG18 MB_CHECK[6] K31 MB_DAT A[36] AG30 MB_DQS_H[7] AK13
MA_DQS_H[7] AD15 MB_CHECK[7] K29 MB_DAT A[37] AH31 MB_DQS_H[8] J31
MA_DQS_H[8] J28 MB_CKE[0] M29 MB_DAT A[38] AK27 MB_DQS_L[0] C13
MA_DQS_L[0] G15 MB_CKE[1] M31 MB_DAT A[39] AL27 MB_DQS_L[1] C17
MA_DQS_L[1] F19 MB_CLK_H[0] C19 MB_DAT A[4] F13 MB_DQS_L[2] C23
MA_DQS_L[2] D25 MB_CLK_H[1] A18 MB_DAT A[40] AJ24 MB_DQS_L[3] C31
MA_DQS_L[3] C29 MB_CLK_H[2] V31 MB_DAT A[41] AH23 MB_DQS_L[4] AL29
MA_DQS_L[4] AG28 MB_CLK_H[3] Y31 MB_DAT A[42] AH21 MB_DQS_L[5] AL23
MA_DQS_L[5] AG25 MB_CLK_H[4] W29 MB_DAT A[43] AJ21 MB_DQS_L[6] AJ17
MA_DQS_L[6] AG19 MB_CLK_H[5] U31 MB_DAT A[44] AK25 MB_DQS_L[7] AJ13
MA_DQS_L[7] AE15 MB_CLK_H[6] AL19 MB_DAT A[45] AL24 MB_DQS_L[8] J30
MA_DQS_L[8] J27 MB_CLK_H[7] AJ19 MB_DAT A[46] AL22 MB_EVENT _L V29
MA_EVENT _L W30 MB_CLK_L[0] D19 MB_DAT A[47] AJ22 MB_RAS_L AB29
MA_RAS_L AA26 MB_CLK_L[1] A19 MB_DAT A[48] AL20 MB_RESET _L B19
MA_RESET _L E20 MB_CLK_L[2] W31 MB_DAT A[49] AH19 MB_WE_L AC30
MA_WE_L AB27 MB_CLK_L[3] Y30 MB_DAT A[5] E13 MB0_CS_L[0] AC31
MA0_CS_L[0] AA24 MB_CLK_L[4] W28 MB_DAT A[50] AJ16 MB0_CS_L[1] AE30
MA0_CS_L[1] AC25 MB_CLK_L[5] U30 MB_DAT A[51] AH15 MB0_ODT [0] AD29
MA0_ODT [0] AC28 MB_CLK_L[6] AL18 MB_DAT A[52] AL21 MB0_ODT [1] AF31
MA0_ODT [1] AE28 MB_CLK_L[7] AK19 MB_DAT A[53] AK21 MB1_CS_L[0] AB31
MA1_CS_L[0] AA25 MB_DAT A[0] D13 MB_DAT A[54] AL17 MB1_CS_L[1] AE29
MA1_CS_L[1] AD27 MB_DAT A[1] A13 MB_DAT A[55] AL16 MB1_ODT [0] AD31
MA1_ODT [0] AC27 MB_DAT A[10] A21 MB_DAT A[56] AK15 MB1_ODT [1] AG31
MA1_ODT [1] AE27 MB_DAT A[11] C21 MB_DAT A[57] AL14 NP/RSVD B2
MB_ADD[0] AA30 MB_DAT A[12] D15 MB_DAT A[58] AG13 NP/VSS AE7
MB_ADD[1] U28 MB_DAT A[13] C16 MB_DAT A[59] AF13 NP/VSS H20
MB_ADD[10] AA29 MB_DAT A[14] A20 MB_DAT A[6] A14 PROCHOT _L AL7
MB_ADD[11] P29 MB_DAT A[15] B21 MB_DAT A[60] AJ15 PSI_L F1
MB_ADD[12] N30 MB_DAT A[16] A22 MB_DAT A[61] AL15 PVIEN/VID[1] E2
MB_ADD[13] AE31 MB_DAT A[17] B23 MB_DAT A[62] AL13 PWROK C9
MB_ADD[14] N29 MB_DAT A[18] B25 MB_DAT A[63] AH13 RESET _L C7

Pins 14
 AMD Confidential – Advance Information
PID:40778 Rev 1.13 – January 2009 Socket AM3 Processor Functional Data Sheet

Name Pin Name Pin Name Pin Name Pin

RSVD AD25 T EST 8 D4 VDD B3 VDD M7
RSVD AE24 T EST 9 F6 VDD C2 VDD M9
RSVD AE25 T HERMDA AG8 VDD C4 VDD N10
RSVD AJ18 T HERMDC AG9 VDD D3 VDD N12
RSVD AJ20 T HERMT RIP_L AK7 VDD D5 VDD N14
RSVD AK3 T MS AL9 VDD E4 VDD N16
RSVD C18 T RST _L AJ10 VDD E6 VDD N18
RSVD C20 VDD AA10 VDD F5 VDD N20
RSVD F2 VDD AA12 VDD F7 VDD N22
RSVD G24 VDD AA14 VDD G6 VDD N8
RSVD G25 VDD AA16 VDD G8 VDD P11
RSVD H25 VDD AA18 VDD H11 VDD P13
RSVD L25 VDD AA20 VDD H23 VDD P15
RSVD L26 VDD AA22 VDD H7 VDD P17
RSVD L30 VDD AA8 VDD J12 VDD P19
RSVD L31 VDD AB11 VDD J14 VDD P21
SA[0] AK4 VDD AB13 VDD J16 VDD P23
SIC AL6 VDD AB15 VDD J18 VDD P7
SID AK6 VDD AB17 VDD J20 VDD P9
SVC/VID[3] C1 VDD AB19 VDD J22 VDD R10
SVD/VID[2] E3 VDD AB21 VDD J24 VDD R12
T CK AH10 VDD AB23 VDD J8 VDD R14
T DI AL10 VDD AB7 VDD K11 VDD R16
T DO AK10 VDD AB9 VDD K13 VDD R18
T EST 10 G7 VDD AC10 VDD K15 VDD R20
T EST 12 AH9 VDD AC12 VDD K17 VDD R22
T EST 13 AJ7 VDD AC14 VDD K19 VDD R4
T EST 14 C5 VDD AC16 VDD K21 VDD R5
T EST 15 F8 VDD AC18 VDD K23 VDD R8
T EST 16 E7 VDD AC20 VDD K7 VDD T 11
T EST 17 D6 VDD AC22 VDD K9 VDD T 13
T EST 18 E9 VDD AC4 VDD L10 VDD T 15
T EST 19 F10 VDD AC5 VDD L12 VDD T 17
T EST 2 AJ6 VDD AC8 VDD L14 VDD T 19
T EST 20 AJ8 VDD AD11 VDD L16 VDD T2
T EST 21 AL8 VDD AD2 VDD L18 VDD T 21
T EST 22 AJ9 VDD AD23 VDD L20 VDD T 23
T EST 23 AH8 VDD AD3 VDD L22 VDD T3
T EST 24 AK8 VDD AD7 VDD L4 VDD T7
T EST 25_H A10 VDD AD9 VDD L5 VDD T9
T EST 25_L B10 VDD AE10 VDD L8 VDD U10
T EST 26 AK5 VDD AE12 VDD M11 VDD U12
T EST 27 AK9 VDD AF11 VDD M13 VDD U14
T EST 28_H J10 VDD AF7 VDD M15 VDD U16
T EST 28_L H9 VDD AF9 VDD M17 VDD U18
T EST 29_H C11 VDD AG4 VDD M19 VDD U20
T EST 29_L D11 VDD AG5 VDD M2 VDD U22
T EST 3 AH7 VDD AG7 VDD M21 VDD U8
T EST 6 AJ5 VDD AH2 VDD M23 VDD V11
T EST 7 E5 VDD AH3 VDD M3 VDD V13

Pins 15
 AMD Confidential – Advance Information
PID:40778 Rev 1.13 – January 2009 Socket AM3 Processor Functional Data Sheet

Name Pin Name Pin Name Pin Name Pin

VDD V15 VDDIO T 28 VOID A2 VSS AC23
VDD V17 VDDIO T 30 VOID A30 VSS AC7
VDD V19 VDDIO V25 VOID A31 VSS AC9
VDD V21 VDDIO V26 VOID AD18 VSS AD10
VDD V23 VDDIO V28 VOID AD19 VSS AD12
VDD V9 VDDIO V30 VOID AE8 VSS AD14
VDD W10 VDDIO Y24 VOID AE9 VSS AD16
VDD W12 VDDIO Y26 VOID AK1 VSS AD20
VDD W14 VDDIO Y28 VOID AK31 VSS AD22
VDD W16 VDDIO Y29 VOID AL1 VSS AD24
VDD W18 VDDIO_FB_H AK11 VOID AL2 VSS AD8
VDD W20 VDDIO_FB_L AL11 VOID AL30 VSS AE11
VDD W22 VDDNB A4 VOID AL31 VSS AE4
VDD W4 VDDNB A6 VOID B1 VSS AE5
VDD W5 VDDNB B5 VOID B31 VSS AF10
VDD W8 VDDNB B7 VOID H21 VSS AF12
VDD Y11 VDDNB C6 VOID H22 VSS AF14
VDD Y13 VDDNB C8 VOID H3 VSS AF16
VDD Y15 VDDNB D7 VOID H4 VSS AF18
VDD Y17 VDDNB D9 VSS A11 VSS AF2
VDD Y19 VDDNB E10 VSS A3 VSS AF20
VDD Y2 VDDNB E8 VSS A7 VSS AF22
VDD Y21 VDDNB F11 VSS A9 VSS AF24
VDD Y23 VDDNB F9 VSS AA11 VSS AF26
VDD Y3 VDDNB G10 VSS AA13 VSS AF28
VDD Y7 VDDNB G12 VSS AA15 VSS AF3
VDD Y9 VDDNB_FB_H G4 VSS AA17 VSS AF8
VDD_FB_H G2 VDDNB_FB_L G3 VSS AA19 VSS AG10
VDD_FB_L G1 VDDR A12 VSS AA21 VSS AG11
VDDA C10 VDDR AG12 VSS AA23 VSS AH14
VDDA D10 VDDR AH12 VSS AA4 VSS AH16
VDDIO AB24 VDDR AJ12 VSS AA5 VSS AH18
VDDIO AB26 VDDR AK12 VSS AA7 VSS AH20
VDDIO AB28 VDDR AL12 VSS AA9 VSS AH22
VDDIO AB30 VDDR B12 VSS AB10 VSS AH24
VDDIO AC24 VDDR C12 VSS AB12 VSS AH26
VDDIO AD26 VDDR D12 VSS AB14 VSS AH28
VDDIO AD28 VDDR_SENSE E12 VSS AB16 VSS AH30
VDDIO AD30 VID[0] E1 VSS AB18 VSS AK14
VDDIO AF30 VID[4] D1 VSS AB2 VSS AK16
VDDIO M24 VID[5] D2 VSS AB20 VSS AK18
VDDIO M26 VLDT _A AJ1 VSS AB22 VSS AK2
VDDIO M28 VLDT _A AJ2 VSS AB3 VSS AK20
VDDIO M30 VLDT _A AJ3 VSS AB8 VSS AK22
VDDIO P24 VLDT _A AJ4 VSS AC11 VSS AK24
VDDIO P26 VLDT _B H1 VSS AC13 VSS AK26
VDDIO P28 VLDT _B H2 VSS AC15 VSS AK28
VDDIO P30 VLDT _B H5 VSS AC17 VSS AK30
VDDIO T 24 VLDT _B H6 VSS AC19 VSS AL5
VDDIO T 26 VOID A1 VSS AC21 VSS B11

Pins 16
 AMD Confidential – Advance Information
PID:40778 Rev 1.13 – January 2009 Socket AM3 Processor Functional Data Sheet

Name Pin Name Pin Name Pin Name Pin

VSS B14 VSS H28 VSS M18 VSS T8
VSS B16 VSS H30 VSS M20 VSS U11
VSS B18 VSS H8 VSS M22 VSS U13
VSS B20 VSS J11 VSS M8 VSS U15
VSS B22 VSS J13 VSS N11 VSS U17
VSS B24 VSS J15 VSS N13 VSS U19
VSS B26 VSS J17 VSS N15 VSS U21
VSS B28 VSS J19 VSS N17 VSS U23
VSS B30 VSS J21 VSS N19 VSS U4
VSS B4 VSS J23 VSS N21 VSS U5
VSS B9 VSS J4 VSS N23 VSS U7
VSS C3 VSS J5 VSS N4 VSS U9
VSS D14 VSS J7 VSS N5 VSS V10
VSS D16 VSS J9 VSS N7 VSS V12
VSS D18 VSS K10 VSS N9 VSS V14
VSS D20 VSS K12 VSS P10 VSS V16
VSS D22 VSS K14 VSS P12 VSS V18
VSS D24 VSS K16 VSS P14 VSS V2
VSS D26 VSS K18 VSS P16 VSS V20
VSS D28 VSS K2 VSS P18 VSS V22
VSS D30 VSS K20 VSS P2 VSS V3
VSS E11 VSS K22 VSS P20 VSS W11
VSS F14 VSS K24 VSS P22 VSS W13
VSS F16 VSS K26 VSS P3 VSS W15
VSS F18 VSS K28 VSS P8 VSS W17
VSS F20 VSS K3 VSS R11 VSS W19
VSS F22 VSS K30 VSS R13 VSS W21
VSS F24 VSS K8 VSS R15 VSS W23
VSS F26 VSS L11 VSS R17 VSS W7
VSS F28 VSS L13 VSS R19 VSS W9
VSS F30 VSS L15 VSS R21 VSS Y10
VSS F4 VSS L17 VSS R23 VSS Y12
VSS G11 VSS L19 VSS R7 VSS Y14
VSS G9 VSS L21 VSS R9 VSS Y16
VSS H10 VSS L23 VSS T 10 VSS Y18
VSS H12 VSS L7 VSS T 12 VSS Y20
VSS H14 VSS L9 VSS T 14 VSS Y22
VSS H16 VSS M10 VSS T 16 VSS Y8
VSS H18 VSS M12 VSS T 18
VSS H24 VSS M14 VSS T 20
VSS H26 VSS M16 VSS T 22

Pins 17
 AMD Confidential – Advance Information
PID:40778 Rev 1.13 – January 2009 Socket AM3 Processor Functional Data Sheet

1.6 Color-Coded Connection Diagram (Left Half)

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

MB_DAT A[1 MB_DAT A[6 MB_DATA[2 MB_DAT A[8

A VOID VOID VSS VDDNB DBREQ_L VDDNB VSS CLKIN_H VSS TEST 25_H VSS VDDR A
] ] ] ]
MB_DATA[7
B VOID NP/ RSVD VDD VSS VDDNB DBRDY VDDNB CLKIN_L VSS TEST25_L VSS VDDR MB_DM[0] VSS VSS B
]
MB_DQS_L[ MB_DQS_H[ MB_DATA[3 MB_DAT A[1
C SVC/ VID[3] VDD VSS VDD T EST 14 VDDNB RESET _L VDDNB PWROK VDDA T EST 29_H VDDR C
0] 0] ] 3]
MB_DAT A[0 MB_DATA[1
D VID[4] VID[5] VDD T EST 8 VDD TEST17 VDDNB LDTST OP_L VDDNB VDDA T EST 29_L VDDR VSS VSS D
] 2]
PVIEN/ VID[ VDDR_SENS MB_DAT A[5 MA_DAT A[1 MA_DATA[6 MA_DAT A[2
E VID[0] SVD/ VID[2] VDD TEST7 VDD T EST 16 VDDNB T EST18 VDDNB VSS E
1] E ] ] ] ]
M_VDDIO_P MB_DAT A[4 MA_DQS_H[
F PSI_L RSVD VSS VDD T EST 9 VDD T EST 15 VDDNB T EST 19 VDDNB M_VREF VSS VSS F
WRGD ] 0]
VDDNB_FB_ VDDNB_FB_ CORE_T YP MA_DAT A[5 MA_DAT A[0 MA_DQS_L[ MA_DAT A[7
G VDD_FB_L VDD_FB_H VDD T EST 10 VDD VSS VDDNB VSS VDDNB G
L H E ] ] 0] ]
MA_DAT A[4
H VLDT_B VLDT _B VOID VOID VLDT _B VLDT_B VDD VSS T EST 28_L VSS VDD VSS VSS MA_DM[0] VSS H
]
L0_CADIN_ L0_CADIN_L L0_CADIN_ L0_CADIN_
J VSS VSS VSS VDD VSS TEST 28_H VSS VDD VSS VDD VSS VDD J
H[1] [0] H[0] H[8]
L0_CADIN_L L0_CADIN_ L0_CADIN_L L0_CADIN_L
K VSS VSS VDD VSS VDD VSS VDD VSS VDD VSS VDD VSS K
[1] H[9] [9] [8]
L0_CADIN_ L0_CADIN_L L0_CADIN_ L0_CADIN_
L VDD VDD VSS VDD VSS VDD VSS VDD VSS VDD VSS VDD L
H[3] [2] H[2] H[10]
L0_CADIN_L L0_CADIN_ L0_CADIN_L L0_CADIN_L
M VDD VDD VDD VSS VDD VSS VDD VSS VDD VSS VDD VSS M
[3] H[11] [11] [10]
L0_CADIN_ L0_CLKIN_L L0_CLKIN_H L0_CLKIN_H
N VSS VSS VSS VDD VSS VDD VSS VDD VSS VDD VSS VDD N
H[4] [0] [0] [1]
L0_CADIN_L L0_CADIN_ L0_CADIN_L L0_CLKIN_L
P VSS VSS VDD VSS VDD VSS VDD VSS VDD VSS VDD VSS P
[4] H[12] [12] [1]
L0_CADIN_ L0_CADIN_L L0_CADIN_ L0_CADIN_
R VDD VDD VSS VDD VSS VDD VSS VDD VSS VDD VSS VDD R
H[6] [5] H[5] H[13]
L0_CADIN_L L0_CADIN_ L0_CADIN_L L0_CADIN_L
T VDD VDD VDD VSS VDD VSS VDD VSS VDD VSS VDD VSS T
[6] H[14] [14] [13]
L0_CT LIN_H L0_CADIN_L L0_CADIN_ L0_CADIN_
U VSS VSS VSS VDD VSS VDD VSS VDD VSS VDD VSS VDD U
[0] [7] H[7] H[15]
L0_CT LIN_L L0_CT LIN_H L0_CTLIN_L L0_CADIN_L
V VSS VSS HTREF0 HT REF1 VDD VSS VDD VSS VDD VSS VDD VSS V
[0] [1] [1] [15]
L0_CADOUT L0_CTLOUT L0_CT LOUT L0_CT LOUT
W VDD VDD VSS VDD VSS VDD VSS VDD VSS VDD VSS VDD W
_L[7] _H[0] _L[0] _L[1]
L0_CADOUT L0_CADOUT L0_CADOUT L0_CT LOUT
Y VDD VDD VDD VSS VDD VSS VDD VSS VDD VSS VDD VSS Y
_H[7] _L[15] _H[15] _H[1]
L0_CADOUT L0_CADOUT L0_CADOUT L0_CADOUT
AA VSS VSS VSS VDD VSS VDD VSS VDD VSS VDD VSS VDD AA
_L[5] _H[6] _L[6] _L[14]
L0_CADOUT L0_CADOUT L0_CADOUT L0_CADOUT
AB VSS VSS VDD VSS VDD VSS VDD VSS VDD VSS VDD VSS AB
_H[5] _L[13] _H[13] _H[14]
L0_CLKOUT L0_CADOUT L0_CADOUT L0_CADOUT
AC VDD VDD VSS VDD VSS VDD VSS VDD VSS VDD VSS VDD AC
_L[0] _H[4] _L[4] _L[12]
L0_CLKOUT L0_CLKOUT L0_CLKOUT L0_CADOUT MA_DAT A[5 MA_DQS_H[
AD VDD VDD VDD VSS VDD VSS VDD VSS VSS VSS AD
_H[0] _L[1] _H[1] _H[12] 9] 7]
L0_CADOUT L0_CADOUT L0_CADOUT L0_CADOUT MA_DAT A[5 MA_DAT A[6 MA_DQS_L[ MA_DAT A[5
AE VSS VSS NP/ VSS VOID VOID VDD VSS VDD AE
_L[2] _H[3] _L[3] _L[11] 8] 3] 7] 6]
L0_CADOUT L0_CADOUT L0_CADOUT L0_CADOUT MB_DAT A[5
AF VSS VSS VDD VSS VDD VSS VDD VSS VSS MA_DM[7] VSS AF
_H[2] _L[10] _H[10] _H[11] 9]
L0_CADOUT L0_CADOUT L0_CADOUT L0_CADOUT MB_DAT A[5 MA_DAT A[6 MA_DATA[5 MA_DAT A[6
AG VDD VDD VDD THERMDA T HERMDC VSS VSS VDDR AG
_L[0] _H[1] _L[1] _L[9] 8] 2] 7] 1]
L0_CADOUT L0_CADOUT L0_CADOUT L0_CADOUT MB_DAT A[6 MB_DATA[5
AH VDD VDD T EST 3 T EST 23 T EST12 T CK M_ZN VDDR VSS VSS AH
_H[0] _L[8] _H[8] _H[9] 3] 1]
MB_DQS_L[ MB_DATA[6 MB_DAT A[5
AJ VLDT_A VLDT _A VLDT _A VLDT_A TEST6 T EST 2 T EST 13 T EST 20 T EST22 T RST _L M_ZP VDDR MB_DM[7] AJ
7] 0] 0]
T HERMT RI VDDIO_FB_ MB_DQS_H[ MB_DATA[5
AK VOID VSS RSVD SA[0] T EST 26 SID T EST 24 T EST27 T DO VDDR VSS VSS AK
P_L H 7] 6]
CPU_PRES PROCHOT _ VDDIO_FB_ MB_DAT A[6 MB_DAT A[5 MB_DATA[6 MB_DAT A[5
AL VOID VOID ALERT _L VSS SIC T EST 21 TMS T DI VDDR AL
ENT _L L L 2] 7] 1] 5]

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

Figure 3. Color-Coded Connection Diagram (Left Half)

Pins 18
 AMD Confidential – Advance Information
PID:40778 Rev 1.13 – January 2009 Socket AM3 Processor Functional Data Sheet

1.7 Color-Coded Connection Diagram (Right Half)

17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

MB_DATA[9 MB_CLK_H[ MB_CLK_L[ MB_DAT A[1 MB_DATA[1 MB_DAT A[1 MB_DAT A[2 MB_DATA[2 MB_DAT A[1 MB_DATA[2 MB_DAT A[2 MB_DAT A[2
A MB_DM[2] VOID VOID A
] 1] 1] 4] 0] 6] 2] 3] 9] 8] 4] 5]
MB_RESET MB_DATA[1 MB_DATA[1 MB_DATA[1 MB_DATA[2
B MB_DM[1] VSS VSS VSS VSS VSS VSS MA_DM[3] VSS VOID B
_L 5] 7] 8] 9]
MB_DQS_L[ MB_CLK_H[ MB_DATA[1 MB_DAT A[2 MB_DQS_L[ MB_DQS_H[ MA_DQS_H[ MA_DAT A[1 MA_DATA[2 MA_DAT A[2 MA_DQS_L[ MB_DQS_L[
C RSVD RSVD MB_DM[3] C
1] 0] 1] 1] 2] 2] 2] 8] 8] 5] 3] 3]
MB_DQS_H[ MB_CLK_L[ MB_DATA[2 MA_DATA[2 MA_DQS_L[ MA_DATA[2 MA_DQS_H[ MB_DQS_H[
D VSS VSS VSS VSS VSS VSS VSS D
1] 0] 0] 0] 2] 9] 3] 3]
MA_DATA[8 MA_DQS_H[ MA_RESET MA_DATA[1 MA_DAT A[1 MA_DATA[2 MA_DATA[2 MA_DAT A[1 MA_DATA[2 MA_DAT A[3 MA_DAT A[3 MB_DAT A[3 MB_DAT A[3
E MA_DM[1] MA_DM[2] E
] 1] _L 4] 5] 1] 2] 9] 4] 0] 1] 0] 1]
MA_DATA[1 MA_DQS_L[ MA_DATA[1 MA_DATA[1 MA_DATA[2 MA_DATA[2 MB_DAT A[2 MB_DAT A[2
F VSS VSS VSS VSS VSS VSS VSS F
3] 1] 0] 6] 3] 6] 7] 6]
MA_DATA[1 MA_DAT A[9 MA_CLK_H[ MA_CLK_H[ MA_CLK_L[ MA_DAT A[1 MA_DATA[1 MA_DAT A[2 MA_CHECK MA_CHECK MB_CHECK MB_CHECK MB_CHECK
G RSVD RSVD G
2] ] 1] 0] 0] 1] 7] 7] [4] [5] [4] [5] [0]
MA_DATA[3 MA_CLK_L[ MA_CHECK MA_CHECK MB_CHECK
H VSS NP/ VSS VOID VOID VDD VSS RSVD VSS VSS VSS H
] 1] [0] [1] [1]
MA_CHECK MA_DQS_L[ MA_DQS_H[ MB_DQS_L[ MB_DQS_H[
J VSS VDD VSS VDD VSS VDD VSS VDD MA_DM[8] MB_DM[8] J
[6] 8] 8] 8] 8]
MA_CHECK MA_CHECK MB_CHECK MB_CHECK
K VDD VSS VDD VSS VDD VSS VDD VSS VSS VSS VSS K
[7] [2] [7] [6]
MA_CHECK MB_CHECK MB_CHECK
L VSS VDD VSS VDD VSS VDD VSS RSVD RSVD MA_CKE[1] RSVD RSVD L
[3] [2] [3]
MA_ADD[15
M VDD VSS VDD VSS VDD VSS VDD VDDIO MA_CKE[0] VDDIO VDDIO MB_CKE[0] VDDIO MB_CKE[1] M
]
MA_ADD[14 MA_BANK[2 MA_ADD[12 MB_ADD[15 MB_ADD[14 MB_ADD[12 MB_BANK[2
N VSS VDD VSS VDD VSS VDD VSS MA_ADD[9] N
] ] ] ] ] ] ]
MA_ADD[11 MB_ADD[11
P VDD VSS VDD VSS VDD VSS VDD VDDIO VDDIO MA_ADD[7] VDDIO VDDIO MB_ADD[9] P
] ]

R VSS VDD VSS VDD VSS VDD VSS MA_ADD[8] MA_ADD[6] MA_ADD[5] MA_ADD[4] MB_ADD[7] MB_ADD[8] MB_ADD[5] MB_ADD[6] R

T VDD VSS VDD VSS VDD VSS VDD VDDIO MA_ADD[3] VDDIO MA_ADD[1] VDDIO MB_ADD[3] VDDIO MB_ADD[4] T

MA_CLK_H[ MA_CLK_L[ MA_CLK_H[ MB_CLK_L[ MB_CLK_H[

U VSS VDD VSS VDD VSS VDD VSS MA_ADD[2] MB_ADD[1] MB_ADD[2] U
2] 5] 5] 5] 5]
MA_CLK_L[ MA_CLK_H[ MB_EVENT MB_CLK_H[
V VDD VSS VDD VSS VDD VSS VDD VDDIO VDDIO VDDIO VDDIO V
2] 4] _L 2]
MA_CLK_L[ MA_CLK_H[ MA_CLK_L[ MB_CLK_L[ MB_CLK_H[ MA_EVENT MB_CLK_L[
W VSS VDD VSS VDD VSS VDD VSS MA_ADD[0] W
3] 3] 4] 4] 4] _L 2]
MA_ADD[10 MA_BANK[1 MB_CLK_L[ MB_CLK_H[
Y VDD VSS VDD VSS VDD VSS VDD VDDIO VDDIO VDDIO VDDIO Y
] ] 3] 3]
MA0_CS_L[0 MA1_CS_L[0 MA_BANK[0 MB_BANK[0 MB_ADD[10 MB_BANK[1
AA VSS VDD VSS VDD VSS VDD VSS MA_RAS_L MB_ADD[0] AA
] ] ] ] ] ]
MB1_CS_L[0
AB VDD VSS VDD VSS VDD VSS VDD VDDIO MA_CAS_L VDDIO MA_WE_L VDDIO MB_RAS_L VDDIO AB
]
MA0_CS_L[1 MA_ADD[13 MA1_ODT [0 MA0_ODT[0 MB0_CS_L[0
AC VSS VDD VSS VDD VSS VDD VSS VDDIO MB_CAS_L MB_WE_L AC
] ] ] ] ]
MA_DATA[6 MA_DATA[5 MA1_CS_L[1 MB0_ODT [0 MB1_ODT [0
AD VOID VOID VSS VSS VDD VSS RSVD VDDIO VDDIO VDDIO AD
0] 3] ] ] ]
MA_DATA[5 MA_DAT A[5 MA_CLK_L[ MA_CLK_H[ MA_DATA[4 MA_DAT A[4 MA_DATA[4 MA_DAT A[3 MA1_ODT [1 MA0_ODT[1 MB1_CS_L[1 MB0_CS_L[1 MB_ADD[13
AE RSVD RSVD AE
1] 4] 6] 6] 8] 3] 6] 6] ] ] ] ] ]
MA_DATA[5 MA_DATA[4 MA_DATA[4 MA_DATA[4 MA_DATA[3 MA_DAT A[3 MB0_ODT [1
AF VSS MA_DM[6] VSS VSS VSS VSS VSS VDDIO AF
0] 9] 7] 0] 2] 7] ]
MA_DATA[5 MA_DQS_H[ MA_DQS_L[ MA_CLK_L[ MA_CLK_H[ MA_DAT A[5 MA_DATA[4 MA_DQS_H[ MA_DQS_L[ MA_DAT A[4 MA_DQS_H[ MA_DQS_L[ MA_DAT A[3 MB_DAT A[3 MB1_ODT [1
AG AG
5] 6] 6] 7] 7] 2] 2] 5] 5] 4] 4] 4] 3] 6] ]
MB_DATA[4 MB_DATA[4 MB_DATA[4 MA_DATA[4 MA_DATA[3 MB_DAT A[3
AH MB_DM[6] VSS VSS VSS VSS VSS VSS MA_DM[4] VSS AH
9] 2] 1] 1] 4] 7]
MB_DQS_L[ MB_CLK_H[ MB_DATA[4 MB_DAT A[4 MB_DAT A[4 MA_DAT A[4 MA_DATA[3 MA_DAT A[3 MA_DAT A[3 MB_DAT A[3 MB_DAT A[3
AJ RSVD RSVD MB_DM[5] MA_DM[5] AJ
6] 7] 3] 7] 0] 5] 5] 9] 8] 3] 2]
MB_DQS_H[ MB_CLK_L[ MB_DATA[5 MB_DQS_H[ MB_DATA[4 MB_DATA[3
AK VSS VSS VSS VSS VSS VSS MB_DM[4] VSS VOID AK
6] 7] 3] 5] 4] 8]
MB_DATA[5 MB_CLK_L[ MB_CLK_H[ MB_DAT A[4 MB_DATA[5 MB_DAT A[4 MB_DQS_L[ MB_DAT A[4 MB_DATA[3 MB_DAT A[3 MB_DATA[3 MB_DQS_H[ MB_DQS_L[
AL VOID VOID AL
4] 6] 6] 8] 2] 6] 5] 5] 5] 4] 9] 4] 4]

17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Figure 4. Color-Coded Connection Diagram (Right Half)

Pins 19
 AMD Confidential – Advance Information
PID:40778 Rev 1.13 – January 2009 Socket AM3 Processor Functional Data Sheet

2 Package Specifications

2.1 Mechanical Loading for Lidded Parts

Table 10 provides the mechanical loading specification for lidded parts. These specifications should
not be exceeded during heat sink installation, system testing, or system shipment.
Table 10. Mechanical Loading for Lidded Parts
Maximum
Type Units Notes
Force
Static lbf 100 1, 2
Dynamic lbf 200 1, 3

Notes:
1. Load specified for coplanar, uniform contact to lid surface.
2. The static specification specifies the allowable range to be applied by the heat sink to the processor package.
3. The dynamic specification assumes a dynamic load that includes the static load and is applied at 50 G for 11 ms.

2.2 Package Insertions

Table 11 provides the recommended number of times that the processor package can be inserted and
removed from a socket.

Table 11. Recommended Number of Insertions

Package Number of Insertions
AM3 15

Package Specifications 20
 AMD Confidential – Advance Information
PID:40778 Rev 1.13 – January 2009 Socket AM3 Processor Functional Data Sheet

2.3 Package Diagram

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Figure 5. Organic Micro Pin Grid Array Package(UOF): Top, Side, and Bottom Views
(Lidded)

Package Specifications 21