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Controller Unit - Lpc2148

The LPC2148 is an ARM-7 microcontroller manufactured by Philips with many built-in peripherals. It has 32KB of SRAM, 512KB of flash memory, 45 GPIO pins, two timers, 10-bit ADC, 10-bit DAC, RTC, I2C, SPI, UART, and USB. It has two 32-bit ports, P0 and P1, that can be configured for input, output, and alternate functions using registers like IOPIN, IODIR, IOCLR and IOSET.

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Suraj Vinod Nayak
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64 views6 pages

Controller Unit - Lpc2148

The LPC2148 is an ARM-7 microcontroller manufactured by Philips with many built-in peripherals. It has 32KB of SRAM, 512KB of flash memory, 45 GPIO pins, two timers, 10-bit ADC, 10-bit DAC, RTC, I2C, SPI, UART, and USB. It has two 32-bit ports, P0 and P1, that can be configured for input, output, and alternate functions using registers like IOPIN, IODIR, IOCLR and IOSET.

Uploaded by

Suraj Vinod Nayak
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© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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LPC2148

ARM-7: LPC2148 is the widely used IC from ARM-7 family. It is manufactured by Philips and
it is pre-loaded with many inbuilt peripherals making it more efficient and a reliable option for
the beginners as well as high end application developer.

Features:
 CPU operating voltage range of 3.0 V to 3.6 V (3.3 V ± 10 %) with 5 V tolerant I/O pads
 64-pin High-Performance ARM Microcontroller
 Flash Program Memory: 512 Kbytes
 SRAM Data Memory: 32 Kbytes
 GPIO Pins: 45
 Timers: Two 32-bit
 Up to nine edge or level sensitive external interrupt pins available
 A/D Converter: 10-bit Fourteen Channels
 DAC: 10-bit
 Real-Time Clock (RTC): Independent Power and Dedicated 32kHz Input
 I²C: Two Modules with Master or Slave Operation
 SPI: Full Duplex Serial Operation
 UART: Two Modules
 USB: 2.0B Fully Compliant Controller with RAM
 External Oscillator: up to 25MHz with integrated PLL for 60MHz Operation
Block diagram of LPC2148

LPC2148 Pin diagram:


MEMORY
LPC2148 has 32kB on chip SRAM and 512 kB on chip FLASH memory. It has inbuilt
support up to 2kB end point USB RAM also. This huge amount of memory is well suited for
almost all the applications.

On chip FLASH memory system


The LPC2148 incorporates a 512 KB Flash memory system. This memory may be used for both
code and data storage. The FLASH memory can be programmed by means of
1. Serial built-in JTAG interface
2. Using In System Programming (ISP) and UART0or
3. By means of In-Application Programming (IAP) capabilities.

The application program, using the IAP functions, may also erase and/or program the
Flash while the application is running, allowing a great degree of flexibility for data storage field
firmware upgrades, etc. When the LPC2148 on-chip boot loader is used, 500 KB of Flash
memory is available for user code.

The LPC2148 Flash memory provides minimum of 100,000 erase/write cycles and 20
years of data-retention.

On chip SRAM
The LPC2148 provides 32 KB of static RAM which may be used for code and/or data storage. It
may be accessed as 8-bits, 16-bits, and 32-bits.
I/O PORTS
LPC 2148 has two I/O Ports each of 32 bit wide giving us total 64 I/O Pins. Ports are
named as P0 and P1.

Pins of each port are labelled as PX.Y where X stands for port number, 0 or 1 where else
Y stands for pin number 0 to 31.

Each pin can perform alternate functions also. For eg. P0.8 serves as GPIO as well as
transmitter pin of UART1, PWM4 and AD1.1.

On RESET, each pin is configured as GPIO. For any of the other use, programmer must
configure it properly.

PORT0:
Total of 30 input/output and a single output only pin out of 32 pins are available on
PORT0.

PORT1:
PORT1 has up to 16 pins available for GPIO functions.
PORT0 and PORT1 are controlled via groups of registers explained below.

1. IOPIN
It is GPIO Port Pin value register. The current state of the GPIO configured port pins can always
be read from this register, regardless of pin direction.

2. IODIR
GPIO Port Direction control register. This register individually controls the direction of each port
pin.

3. IOCLR
GPIO Port Output Clear registers. This register controls the state of output pins. Writing ones
produces lows at the corresponding port pins and clears the corresponding bits in the IOSET
register. Writing zeroes has no effect.

4. IOSET
GPIO Port Output Set registers. This register controls the state of output pins in conjunction with
the IOCLR register. Writing ones produces highs at the corresponding port pins. Writing zeroes
has no effect.

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