International Journal of Electrical, Electronics and Data Communication, ISSN: 2320-2084 Volume-3, Issue-6, June-2015

IMPLEMENTATION OF 24T MEMRISTOR BASED ADDER

ARCHITECTURE WITH IMPROVED PERFORMANCE
1
JOY CHOWDHURY, 2J. K. DAS, 3N. K. ROUT

School of Electronics Engineering, KIIT University, Bhubaneswar

1
[email protected], [email protected], [email protected]

Abstract- In the recent history of electronics industry nano scale devices took a major leap through the invention of the
physical memristor device in 2008 by Hewlett Packard Labs. These are considered to be novel devices finding extensive
applications in the field of semiconductor memory integration and development. Design of logic function blocks are also an
important application of these memristive devices due to its minimized area, power consumption and compatibility with
existing CMOS fabrication technology. There are various design styles for designing digital logic such as MRL, IMPLY,
MAGIC. In this paper a full adder which is the most basic digital design unit has been developed using MRL (Memristor
Ratioed Logic) design style and then it was modified using the concept of mirror adder design thus obtaining further
optimized values of delay and power.

Keywords - Full adder, Memristor, MRL logic family, Optimization, digital logic, linear ion drift model.

I. INTRODUCTION influence of an uniform electric field. A state variable

is used to properly identify the switching
Chua's memristor[1] can easily qualify to be the phenomenon between the on and off states of the
landmark discovery in the field of nano-scale memristor. The mathematical expression representing
electronics redefining various concepts of circuit the same is in the form of a simple differential
theory. Memristors are considered as the fourth two equation given in the form;
terminal passive circuit elements. The basic concept = . ( ) (2)
underlying the functioning of the memristor is that
and
there exists a relationship between charge and ( ) ( )
magnetic flux. The electrical resistance of the ( )= . 1− (3)
memristor change with the past values of current where ( ) is the state variable of the
present in the device. Thus the device can be used for memristive system while is the resistance when
effectively storing bits of information. The basic ( ) = and is the resistance when ( ) = 0.
mathematical formula representing a memristor is
given by
The window functions serve a major role in the
= (1) validation of the 'linear ion drift model' as they help
where M represents the 'memristance' of the device. to limit the drift of the mobile ions within the
The mathematical model of the memristor physical bounds of the device. There are various
considering linear drift of the ions can be represented kinds of window function such as the Jogelkar
by two series connected variable resistors as window[8], Biolek window[12], Prodromakis
[13]
suggested by Williams .et. al. in [5]. This was window etc. The linear model has the advantage of
physically implemented in the form of a variably being mathematically simple, computationally
doped thin film TiO2 substrate as shown in figure1. efficient and optimized. The only disadvantage being
the reduced amount of non linearity that could be
exhibited through the use of this model. To suffice
this several new models have been proposed such as
the non linear ion drift model, Simmons Tunnel
Barrier model, TEAM model[11] etc. These models are
characterized by several assumptions, complex
mathematical equations and various complicating
physical phenomenon.
Figure 1: Memristor model from Hewlett Packard.
II. DIGITAL LOGIC IN MRL
The doping of thin film is actually represented by
oxygen vacancies. The doped oxide region has a high Memristor Ratioed Logic[9] is a kind of logic family
resistance value Ron while the undoped region has a in which the memristive devices are integrated with
low resistance Roff. Several assumptions which have the standard CMOS logic for the development of
been taken into consideration while establishing this various digital logic functions. Similar to CMOS
model. Those are : a) ohmic conductance b) equal technology the data in the logic levels is represented
mean ion mobility and c) linear drift of ions under the in the form of voltage. Basic logic gates like the AND

Implementation Of 24t Memristor Based Adder Architecture With Improved Performance

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International Journal of Electrical, Electronics and Data Communication, ISSN: 2320-2084 Volume-3, Issue-6, June-2015

and OR can be implemented by direct use of the

memristive device while for the design of inverting
logic the help of cmos inverters has to be taken. The
initial state of the memristor has got no role to play in
the computation of the logical results. The OR and
AND gates can be constructed by the series
combination of memristors as shown in figure 2.
Only the polarity is reversed in each case to vary the
functionality. Here the sole purpose of the memristor
is bipolar resistive switching and not storage of any
data bits.

Figure 4: Design of MRL based Full Adder standard cell.

IV. PROPOSED DESIGN

The 28T full adder architecture has the disadvantage

Figure 2 : MRL based AND and OR gates.
of stacking effect due to tall pmos transistor stacks,
delay is not optimized because the concept input
ordering is not followed and also area consumed is
more due to use of greater number of transistors. Now
applying some logic modification and using
symmetry conditions 24T mirror adder architecture is
obtained which has optimized delay and area
considerations as compared to the previous designs.
In this deign there is use of propagate, generate and
delete signals and the sum is obtained in terms of the
carry out signal. So now the 24T mirror adder design
is suitably modified and implemented in MRL logic
and the resulting circuit block is simulated and
functional verification is carried out using the Spectre
simulator in Cadence Virtuoso Environment.
Figure 3 : Inverted MRL
V. RESULTS AND DISCUSSION
For NAND and NOR functionality which has invert
property uses the CMOS inverter along with the The 28T adder in the memristor level was
memristive devices as shown in figure 3. implemented and the transient analysis was
performed to check the adder functionality. Then the
III. ADDER delay of the critical path i.e. from the input carry to
the carry out was calculated and power analysis was
The full adder is one of the most fundamental and done, shown in figure 6 and figure 7. Finally the
basic digital building block which finds wide spread average power dissipation was noted.
application in the design of digital computational
systems like ALU, processor design, ADC, Data
Converters, Samplers, Quantizers, Digital signal
processing units, multipliers, etc. The basic
functionality of the full adder is to add three input
numbers(one of which is carry in) and produce
sum and carry outputs.

= ⊕ ⨁
= . + . + .
The conventional CMOS transistor level schematic
consists of 28 transistors. The memristor based
implementation has been done and shown in [9]. The
following figure 4 highlights some of the already
implemented designs.
Figure 5 : Schematic of 28T adder architecture.

Implementation Of 24t Memristor Based Adder Architecture With Improved Performance

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International Journal of Electrical, Electronics and Data Communication, ISSN: 2320-2084 Volume-3, Issue-6, June-2015

Figure 10: 24T architecture waveform

Figure 6 : 28T Full adder waveforms showing inputs and
output sum and carry Critical path delay is 0.377 ns.
Average power = 3.646 nW.
The critical path delay was found to be 30.18 ns.
The average power dissipation was extracted from the
transient power curve and the value was found out to
be 60.77 µW.

Figure 11: Power Analysis of 24T adder architecture.

Due to the use of cmos inverters in the intermediate

stages there is some logic degradation. A few
Figure 7: Power Analysis of 28T architecture. techniques that can be used such as appropriate sizing
of the inverters, increasing the voltage of the high
Now based on suitable modifications the 24T mirror logic levels and connecting capacitors at the output
adder design was also implemented. A capacitor was nodes to account for the loading effect of succeeding
connected at the carry out node to observe the stages.
switching effect in a more prominent fashion. A cmos
inverter is used in this stage to generate the CONCLUSION
complement of the output carry which is to be used in
the successive sum generation phase. Then the critical Thus we can see from the values of delay and power
path delay was calculated and power analysis was that our proposed 24T memristor based adder
done. architecture gives improved performance than the
existing memristor based adder model. The
performance comparison is shown in table below
Table 1: Comparison of 28T and 24T adders based on power,
delay, number of cells used

Desig Powe Delay(ns No. of No. of

n r ) memristor CMO
s S
(µW) invert
ers
28T 60.77 30.18 21 4
full
adder
24T 3.646 0.377 18 1
full
adder
Figure 8 : Schematic of proposed 24T design.

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