Lecture-45

CPU Initiated Conditional Data Transfer

In CPU initiated conditional data transfer, the processor initiates
the data transfer process but the execution of I/O instruction for data
transfer is conditioned on the I/O device being ready for the data
transfer. Readiness is determined by an unconditional transfer of
status information from the I/O device to the processor that contains
the state of the I/O device hardware. Often 1 or 2 bits indicate the
status of an I/O device.
A single bit of status information indicates when a single input
port has information available for input or when a single output port is
ready to receive information. The software that tests the status flag
increases the time associated with the I/O operation; the additional
time is the I/O overhead.

D7
D6 8
PORT 1 Data from
8-it Latch input device
Tristate
Buffer
D0

+5V
IDSP 01 H

D
Tri-state Buffer

Q
High indicating
data available
IDSP 00H

IDSP 01 H

Fig.7.21 Checking of Status of Input Device in Conditional Polled I/O

 Consider, for example an input device that has data available at
input port „1‟ (let‟s call it DATA) for transmission to microprocessor.
To indicate the availability of data, the input device sets a flag bit 7 of
input port „0‟(let‟s call it STATUS). The use of flags in controlling
conditional transfer is referred to as handshaking with programmed
I/O. It is the only way of knowing when new data is available for input
to the microprocessor.
PIN: IN STATUS ; Input status byte
ORA A ; Set flags.
JP PIN ; Check data available status bit (bit7)
; if data is not available, wait
IN DATA ; Data is available, input data and
; clear data available flag.
MOV M,A ; Transfer data to memory
INX H ; Increment memory pointer
DCR B ; Decrement counter
JNZ PIN ; Back to pin if more data is to be input
RET

Fig.7.22 ALP to Input Data from an I/O Device in Polled I/O

To determine availability of data for inputs, the microprocessor

periodically input the status word at input port „0‟ and tests bit 7. If bit
7 is 1, data is available & an instruction inputs it from port „1‟. The
input device select strobe that enables the data from port „1‟ also
resets the data available flag.
The frequency with which the status flag is checked determines
the minimum length of time it takes to transfer the data. An input
subroutine executes a tight loop to check the status flag. The
subroutine given above assumes that the number of bytes of data to
be transferred is in B and that (H,L) points to the starting address of
the data buffer in memory when the subroutine is called.
This problem is best illustrated by taking an example. The
example to be considered is a direct interfacing of a tri-state ADC
based on Successive Approximation method. The block diagram is
shown in fig.7.23.
EOC D7-D0
8

CE

TRI STATE ADC

SOC
H H
L

VA(t)
Fig.6.23 Schematic Diagram of Tri-state 8-bit ADC

In fig.7.23 VA(t) is the analog input signal whose digital equivalent is

required. The 8-bit digital equivalent is obtained internally as and
when necessary by successive approximation principle which is very
fast. The data is made available at the output terminals D7 –D0 when
the chip enable signal CE is made ACTIVE LOW. When CE is HIGH,
the D7–D0 terminals are tri-stated. This ADC does not produce the
digital equivalent as and when the analog input changes but it needs
a start pulse designated as START OF CONVECSION (SOC) pulse.
In the ADC shown in figure, the SOC pulse is normally HIGH, goes
LOW and again HIGH. This LOW to HIGH transition of SOC signal
starts the conversion process. Once the process starts the digital
equivalent is not available instantaneously. It takes time, and the time
taken to get the digital equivalent, once the conversion starts is
known as the conversion time. Normally for a successive
approximation ACD chip the conversion time TC is around 100μsec. It
is assumed that the analog input is not changing during this
conversion time. This is true in the case of slow changing analog
signals. In the case of fast changing, analog input signal vA(t) of fig-2
shall be the output of a sample and hold circuit. Sample and hold
circuit is also available in the form of an IC chip.
Once the conversion begins, the external world must be told
that the ADC is busy in conversion. ADC issues a control signal
output known as “END OF CONVERSION (EOC)” signal for this
purpose. EOC is normally LOW and goes HIGH when conversion
starts. It remains HIGH as long as the conversion is not over and
goes LOW again when the conversion is complete. The complete
timing signal are shown in fig.7.24.
 H H
SOC L

Internal
D7-D0 Don't care data Valid Data

EOC
Tc

CE

External Tri-state
Valid Data
D7-D0

Fig.7.24 Timing Diagram during Analog to Digital Conversion

We shall use the timing signals shown in fig.7.24, to interface the
ADC of fig.7.23 directly to microprocessor.
Let us interface the given ADC as memory mapped I/O
through the CPU initiated polled I/O transfer. Let the memory spaced
allocated to this device page C0H. It means that the complete
memory space address C000H to CFFH is allocated to this device.
Studying fig.7.23 and fig.7.24 we see that three different control
signals are to be generated or checked at appropriate time to read
one byte of data from the given ADC. Let us allocate the following
locations, all falling with in page C0H to generate these signals.
1) SOC : C0 X2 H
2) EOC : C0 X1 H
3) CE : C0 X0 H
Having allocated the addresses we can, draw the internal circuitry, of
given ADC of fig.7.23 for polled I/O transfer. Necessary interfacing
diagram is shown in fig.7.25.
To generate or checked control signals, the address lines A1
and A0 are to be decoded provided the higher order address is C0H.
A3 A2 A1 A0
X X 1 0 ------- SOC
X X 0 1 ------- EOC
X X 0 0 ------ CE
The desired address is put on address bus using MOV M,A
instruction. Content of accumulator is put on data bus during the
execution of MOV M, A. It is a fictitious write operation since it is used
to generate only a control pulse for ADC operation. No other device is
selected.
AB
BDB
D0 8 D7-D0 BCB

15 14 13 12 11 10 9 A8 EOC RD
RD WR
IO/M

A1 A0

74138
A0 0
A1 1
2
A2
3 EOC D7-D0
E1 4
E2 5
E3 6 TRI- STATE
7 SOC ADC

VA(t)

Fig.7.25 Interfacing of ADC with System Bus in Memory Mapped I/O

The producer to be followed to get one byte of data from the ADC is
as follows:
1) Initiate the conversion process by generating an SOC pulse. This
is done by a write operation on to the address C002H. This is a
fictitious write operation as the content of BDB is not written
anywhere but this operation is used only to generate SOC pulse.
However, fictitious write operations are always performed to
generate search pulses. Fictitious read operation is not
performed to generate a pulse because internal registers are not
to be disturbed.
2) Having applied SOC pulse, microprocessor should monitor the
EOC signal continuously to find whether the conversion is
complete. This is done by the processor by reading from the
memory location C001H and clerking whether D0 bit is zero.
3) It waits in step (2) continually monitoring the EOC signal as long
as EOC is HIGH.
4) When EOC is found LOW – a READ operation is performed from
the memory address C000H to take in 8-bits of digital equivalent
of analog signal at that time. The above process has to be
repeated for reading more than one sample of analog signal.
The detailed flow chart for reading one byte of data from fig.7.25
through polled I/O transfer is given in fig.7.26.
 (H,L) C002

M(H,L) (A)

(L) (L) - 1

(A) M(H,L)

RRC

IS No
CY =0 ?

Yes
(L) (L) - 1

(A) M(H,L)

Fig.7.26 Flowchart for ADC Interfaced in Memory Mapped I/O

The ALP corresponding to fig.7.26 is shown in fig.7.27.
:
SOC EQU C0002H
LXI H, SOC ; (H,L) pints to SOC
MOV M,A ; Generate SOC pulse
DCR L
NEXT: MOV A,M ; Read EOC signal
RRC
JC NEXT ; If conversion is not over
; go back to check it again
DCR L ; If conversion is over
MOV A,M ; read data from ADC
:
Fig.7.27 ALPfor ADC Interfaced in Memory Mapped I/O
In the above discussions, we have interfaced the ADC directly with
the processor bus. It is possible, however, to interface the ADC with
the bus through programmable peripheral interface support chip. It
will be discussed later on.