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Question Paper (Unit-Test-1) Analog IC Design (MEL G 632) Date: 21-02-2017 Time: 12:00 Hours To 13:00 Hours Closed Book Full-Marks: 15

The document is a past question paper that contains a single question asking the student to: 1. Design a common-source amplifier stage with a gain of 5 and a large bypass capacitor for a given source resistance and voltage. 2. Design a biasing stage using a resistor divider network such that the input impedance looking into the gate is high. 3. Ensure the device operates in saturation. The question then provides a hint for the design and suggests using realistic parameter values. A possible design is outlined that meets the requirements using the given values.

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Gaurav Patil
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212 views2 pages

Question Paper (Unit-Test-1) Analog IC Design (MEL G 632) Date: 21-02-2017 Time: 12:00 Hours To 13:00 Hours Closed Book Full-Marks: 15

The document is a past question paper that contains a single question asking the student to: 1. Design a common-source amplifier stage with a gain of 5 and a large bypass capacitor for a given source resistance and voltage. 2. Design a biasing stage using a resistor divider network such that the input impedance looking into the gate is high. 3. Ensure the device operates in saturation. The question then provides a hint for the design and suggests using realistic parameter values. A possible design is outlined that meets the requirements using the given values.

Uploaded by

Gaurav Patil
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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Question Paper (Unit-Test-1)

Analog IC Design (MEL G 632)

Date: 21-02-2017 Time: 12:00 hours to 13:00 hours

Closed Book Full-Marks: 15

1. Given and voltage


drop across source-resistance design a common-source stage with source
degeneration for an overall voltage gain = 5 when a capacitance of sufficiently large value
bypasses the source resistance.
Design the biasing stage for the above using a resistor-divider network such that the input
impedance looking into the gate-terminal from signal-source .
Ensure that the device operates in saturation.
5+5+5=15
Hint.

( )

Ans. There could be many designs possible. Using the hint and some realistic values of parameters
we can propose the following design.
VDD = 1.8V
AV=5, VTh=0.5

R1 RD
Vout
Q1
NMOS

+
R2 RS VRS = 400mV
C1
-

The power-budget

√ ( )

Since ( )
This

To ensure that the NMOS-device remains in saturation, we must ensure a reasonable value for VGS, to be
decided by appropriate selection of R1 and R2 for VDD given as 1.8V. As an initial choice, we select VGS =
1V. This leads to: ( )

Finally we need to find


=224.98 . This completes the design.

Selection of shall depend on the minimum frequency of the input signal for instance, for 10kHz
signal, Usually such large capacitors are
never inserted in the IC and are used externally.

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