DIVISOR DE FRECUENCIA DE 50 MHZ A 10 HZ

library.ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity div_frec is
port( clk: in std_logic;
q: out std_logic);
end div_frec;

architecture solucion of div_frec is

signal cuenta: std_logic_vector(21 downto 0);

begin
process(clk)
begin
if rising_edge(clk)
then
cuenta<=cuenta+1;
if cuenta=2499999
then
cuenta<=(others=>'o');
q<=not q;
end if;
end if;
end process;
end solucion;
ESCALER

library.ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity escaler is
port( clk: in std_logic;
s: in std_logic_vector(2 downto 0);
q: out std_logic);
end escaler;

architecture solucion of escaler is

signal cuenta:std_logic_vector(7 downto 0);

begin
process(clk)
begin
if rising_edge(clk) then
cuenta<=cuenta+1;
end if;
end process;

with s select z<= cuenta(0) when "000";

cuenta(1) when "001";
cuenta(2) when "010";
cuenta(3) when "011";
cuenta(4) when "100";
cuenta(5) when "101";
cuenta(6) when "110";
cuenta(7) when others;
end solucion;
RELOJ DE MM:SS PARA SER VISUALIZADOS EN 4 DISPLAY A 7 SEGMENTOS DEL TIPO
ANODO COMUN

library.ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity reloj is
port( clk: in std_logic;
display: out std_logic_vector(6 downto 0);
t: out std_logic_vector(3 downto 0));
end reloj;

architecture solucion of reloj is

signal clkg: std_logic;
signal sel: std_logic_vector(1 downto 0);
signal US,DS,UM,DM,X: std_logic_vector(3 downto 0);
signal contador: std_logic_vector(24 downto 0);
signal cuenta: std_logic_vector(17 downto 0);

begin
with sel select '1'<= "1000" when "00",
"0100" when "01",
"0010" when "10",
"0100" when others;

process(clk)
begin
if falling_edge(clk) then
contador<=contador+1;
if contador=24999999 then
contador<=(others=>'0');
clkg<=not clkg;
end if;
end if;
end process;

process(clkg)
begin
if falling_edge(clk) then
US<=US+1;
 if US=9 then
DS<=DS+1;
US<="0000";
if DS=5 then
UM<=UM+1;
DS<="0000";
if UM=9 then
DM<=DM+1;
DS="0000";
if DM=5 then
DM<="0000";
end if;
end if;
end if;
end if;
end if;
end process;

x<=select US when sel="00" else

DS then sel="01" else
UM when sel="10" else DM;

process(x)
begin
case x is --gfedcba
when "0000"=> display <="1000000";
when "0001"=> display <="1111001";
when "0010"=> display <="0100100";
when "0011"=> display <="0110000";
when "0100"=> display <="0011001";
when "0101"=> display <="1000000";
when "0110"=> display <="1110010";
when "0111"=> display <="0000011";
when "1000"=> display <="1111000";
when "1001"=> display <="0000000";
when others=> display <="1111111";
end case;
end process;
process(clk)
begin
if falling_edge(clk) then
cuenta<=cuenta+1;
end solucion;
DIVISOR DE FRECUENCIA CON CICLOS DE TRABAJO DEL 5%, 25%, 50%

library.ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity controlador is

port( clk,ENA,f5,f25,f50,f75,f95:in std_logic;

salida: out std_logic);
end controlador;

architecture solucion of controlador is

signal d5,d25,d50: std_logic;
signal contador: std_logic_vector(15 downto 0);
signal m: std_logic_vector(4 downto 0);

begin
process(clk,ena)
begin
if(ena='1') then
if(clk='1' and clk'event) then
contador<=contador+1;
if(contador<=47499) then
d5<='1';
end if;
if(contador<=37499) then
d25<='1';
end if;
if(contador<=24999) then
d50<='1';
end if;
if(contador<=49999) then
contador<=(others=>'0');
d5<='0';
d25<='0';
d50<='0';
end if;
end if;
end if;
end process;

m=f5&f25&f50&f75&f95;
salida<= d5 when m="10000" else;
d25 when m="01000" else;
d50 when m="00100" else;
not(d25) when m="00010" else;
not(d5) when m="00001" else 'z';

end solucion;

CONTADOR HH:MM:SS SABIENDO QUE LA SEÑAL DEL RELOJ ES DE 65536 HZ

library.ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity reloj is

port( clk:in std_logic;

US,UM,UH,DS,DM,DH: out std_logic_vector(3 downto 0));
end reloj;

architecture solucion of reloj is

signal contador: std_logic_vector(15 downto 0);
signal x: std_logic;

begin
process(clk)
begin
if clk='1' and clk'event then
contador<=contador+1;
if contador<=32680 then
contador<=(others=>'0');
x<=not x;
end if;
end if;
end process;

process(x)
begin
if clk='1' and clk'event then
US<=US+1;
if US="1001" then
US<=(others=>'0');
 DS<=DS+1;
if DS="0101" then
US<="0000";
UM<=UM+1;
if UM="1001" then
DM<=DM+1;
DM<="0000";
if DM="0101" then
UH<=UH+1;
DM<=(others=>'0');
if UH="1001" then
DH<=DH+1;
UH<="0000";
if DH="0010" and UM="0100" then
DH<=(others=>'0');
end if;
end if;
end if;
end if;
end if;
end if;
end if;
end process;
end solucion;

CONTADOR 9 BITS MOD 500 QUE TENGA:

 ENABLE(0=CONTADOR HABILITADO PARA CONTAR / 1=NO HABILITADO)

 RESET (1=BORRA LA CUENTA) DEBER SER SINCRONA.
 LOAD(1=PERMITE CARGAR UN DATO)
 UP(1=ASCENDENTE / 0=DESCENDENTE)
 8 ENTRADAS DE DATOS PARA EL INICIO DE LA CUENTA SI SE ACTIVA LOAD
 CARRY_OUT (DEBE GENERAR UN PULSO EN BAJO CADA VEZ QUE HAY UN
DESBORDAMIENTO DE LA CUENTA 15 A 0 EN UNA CUENTA ASCENDENTE)
 BORROW_OUT( DEBE GENERAR UN PULSO BAJO CADA VEZ QUE HAY UN
DESBORDAMIENTO DE LA CUENTA O A 15 ENB UNA CUENTA DESCENDENTE)

library.ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity cont_9bit is

port( enable,reset,load,up,clk: in std_logic;

 entrada: in std_logic_vector(8 downto 0));
carry_out,borrow_out: out std_logic;
salida: out std_logic_vector(8 downto 0));

end cont_9bit;

architecture solucion of cont_9bit is

signal contador: std_logic_vector(8 downto 0);

begin
process(clk)
if reset='1' then
salida<="000000000";
elsif clk='1' and clk'event then
if enable='1' then
if load='1' then
salida<=entrada;
else
salida<="zzzzzzzzz";
end if;
elsif up='1' then
contador<=contador+1;
carry_out='1';
salida<=contador;
if contador=500 then
contador<="000000000";
carry_out<='0';
end if;
else contador<=contador-1;
borrow_out<='1';
salida<=contador;
if contador then
contador<=500;
borrow_out<='0';
end if;
end if;
end if;
end process;
end solucion;