BSc IT

Digital and Computer Organization

Semester - III

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 Instruction Codes
A process is controlled by a program

– A program is a set of instructions that

specify the operations, data, and the control
sequence

– An instruction is stored in binary code that

specifies a sequence of micro operations

– Instruction codes together with data are

stored in memory (Stored Program Concept)
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 Program Statements and Computer Instructions

Computer
instruction

Field specifying the Field specifying the

operation to be data
executed To be operated on

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 Instruction Code Format
• Instruction code format with two parts :
1. Operation Code (Op Code)
2. Address
– Op. Code : specify 16 possible operations(4 bits)
– Address : specify the address of an operand(12 bits)
– If an operation in an instruction code does not need
an operand from memory, the rest of the bits in the
instruction(address field) can be used for other
purpose
15 12 11 0 15 12 11 0

Op. Code Address data

instruction Not an instruction

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 Components of Instructions
• Operations (op codes)

• Number of operands (Number of data locations)

Op code: add value in src1 to

add r1,r2,r3
value in src2 and place the
result in dst.
Op code src1 src2 dst
ADD R1, R2, R3 R1  R2 + R3

• Instruction encodings

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 Number of Operands Per Instruction
• No Operands HALT NOP

• 1 operand NOT R4 R4  R4

• 2 operands ADD R1, R2 R1  R1 + R2

• 3 operands ADD R1, R2, R3 R1  R2 + R3

• > 3 operands MADD R4,R1,R2,R3 R4  R1+(R2*R3)

• Each specify one operation and 1,2, 3 or 4 data locations.

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 OPERATION CODE
In computer technology, an opcode (operation code) is
the portion of a machine language instruction that
specifies the operation to be performed.

Their specification and format are laid out in the

instruction set architecture of the processor in question
(which may be a general CPU or a more specialized
processing unit).

Apart from the opcode itself, an instruction normally also

has one or more specifies for operands (i.e. data) on
which the operation should act, although some operations
may have implicit operands, or none at all.
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 OPERATION CODE
Depending on architecture, the operands may be register values,
values in the stack, other memory values, I/O ports, etc, specified
and accessed using more or less complex addressing modes.

The types of operations include arithmetics, data copying, logical

operations, and program control, as well as special instructions.

Opcodes can also be found in so called byte codes and other

representations intended for a software interpreter rather than a
hardware device.

These software based instruction sets often employ slightly higher-

level data types and operations than most hardware counterparts,
but are nevertheless constructed along similar lines.

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 OPERATION CODE
There are instruction sets with nearly uniform fields for
opcode and operand specifies, as well as others (the x86
architecture for instance) with a more complicated, varied
length structure.

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 Address Part of Instruction
Instructions are divided by number of addresses into multiple-
address, single-address, and zero-address instructions.

In multiple-address instructions, the instruction format may be

uniform or non-uniform.

The uniform instruction format is characterized by identical

structure and length in all addresses of the instruction.

With the nonuniform instruction format, the same part of the

instruction contains complete addresses (based on the entire
capacity of the direct-access storage) and short addresses
(linked with part of the direct-access storage).

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 Address Part of Instruction
In many cases the short addresses pertain to special
ultrahigh-speed direct-access storage units of limited
capacity.

For general-use computers, single-address instructions are

most common. They make it possible to expand the working
section substantially or to assign two instructions to each
cell.

The extreme case is the zero-address instruction, in which

the address part in the instruction is entirely absent, and
operands are either assigned to the instruction itself or
specially assigned to the direct-access storage and are
selected according to a previously determined law.
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 Address Part of Instruction
The zero instruction format is most frequently used in
combination with other command structures.

A distinction is made between the constant instruction format,

when the number of addresses in an instruction is set during
the design of the computer, and the variable instruction
format, which foresees operational change in the instruction
format during the process of computations depending on the
nature of the procedures being carried out.

The variable instruction format substantially increases the

performance of the computer, but its realization involves
design and circuitry complications
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 INTRUCTION CYCLE
• An instruction cycle (sometimes called fetch-and-
execute cycle, fetch-decode-execute cycle, or FDX) is
the basic operation cycle of a computer.

• It is the process by which a computer retrieves

aprogram instruction from its memory, determines what
actions the instruction requires, and carries out those
actions.

• This cycle is repeated continuously by the central

processing unit (CPU), frombootup to when the
computer is shut down.

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 Instruction Cycle
A computer goes through the following instruction cycle
repeatedly:

1. Fetch an instruction from memory

2. Decode the instruction

3. Read the effective address from memory if the

instruction has an indirect address

4. Execute the instruction until a HALT instruction is

encountered

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 Instruction and Interrupt Cycles
Interrupt Cycle

Instruction cycle

Interrupts Enabled
Interrupts Disabled
Fetch, decode
Execute Interrupt
START Next
Instruction Instruction cycle

HALT

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 INTRUCTION CYCLE

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 CIRCUIT USED INTRUCTION CYCLE
The circuits used in the CPU during the cycle are:

Program Counter (PC) - an incrementing counter that keeps track of the

memory address of which instruction is to be executed next

Current Instruction Register (CIR) - a temporary holding ground for the

instruction that has just been fetched from memory

Control Unit (CU) - decodes the program instruction in the CIR, selecting
machine resources such as a data source register and a particular
arithmetic operation, and coordinates activation of those resources

Arithmetic logic unit (ALU) - performs mathematical and logical

operations

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 Fetch and Decode
• The programme counter (pc) is loaded with the address
of the first instruction in the program.

• The Seq Counter (sc) is cleared to 0,providing a decode

timining signal T0,T1,T2 and so on.

• The instruction decoder interprets the instruction. If the

instruction has an indirect address, the effective address
is read from main memory, and any required data is
fetched from main memory to be processed and then
placed into data registers. During this phase the
instruction inside the IR (instruction register) decode.
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 Fetch and Decode

19
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 Execution in instruction cycle
• The instruction decoder interprets the instruction.

• If the instruction has an indirect address, the effective address is

read from main memory, and any required data is fetched from
main memory to be processed and then placed into data
registers.

• During this phase the instruction inside the IR (instruction

register) decode.

• The CU passes the decoded information as a sequence of control

signals to the relevant function units of the CPU to perform the
actions required by the instruction such as reading values from
registers, passing them to the ALU to perform mathematical or
logic functions on them, and writing the result back to a register. If
the ALU is involved, it sends a condition signal back to the CU.

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 Execution in Instruction Cycle

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 Timing and Control Unit
Timing and Control Unit consist of:

• Clock pulses

• Timing signals

• Control unit

• Hardwired control

• Microprogrammed control
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 Clock Pulses & Timing Signal
The timings for all registers in the
basic computer is controlled by
master clock generator.

The clock pulses are applied to all

flip flops and registers in the system,
including the flip flops and register in
the control unit.

The clock pulse do not change the

state of a register unless is enabled
by a control signal..

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 Control Unit
• It consist of 2 decoders, a sequence, and number of control logic gates

• The functions performed by the control unit vary greatly by the internal
architecture of the CPU, since the control unit really implements this
architecture.

• On a regular processor that executes x86 instructions natively the control unit
performs the tasks of fetching, decoding, managing execution and then storing
results. It manages the translation of x86 instructions to RISC micro-
instructions, manages scheduling the micro-instructions between the various
execution units, and juggles the output from these units to make sure they end
up where they are supposed to go.

• On one of these processors the control unit may be broken into other units
(such as a scheduling unit to handle scheduling and a retirement unit to deal
with results coming from the pipeline) due to the complexity of the job it must
perform.
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 Control Unit

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 Hardwired Control

• In the hardwired the control logic

is implemented with gates flip-
flops, decoders and other digital
circuit.

• It has the advantage that it can

be optimized to produce a fast
mode of presentation

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 Microprogrammed control

• In the micro-programmed
control, the control
information is stored in a
control memory.

• It requires changes in the

wiring among the various
components if the
designed has to be
modified or changed.

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 Memory Reference Instructions

• Opcode (000 - 110) or the decoded output Di (i = 0, ..., 6)

are used to select one memory-reference operation out of 7.

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 AND to AC
• AND to AC: Logical AND operation between AC and the
memory word specified by AR.

• (Note that T0-T2 for fetch an instruction; T3 for AR 

M[AR] if indirect memory addressing.

• Need 2 more cycles for the AND logical operation since

only DR is connected to ALU.)

• D0T4: DR  M[AR]

• D0T5: AC  AC ˆ DR, SC  0

– SC – start counter
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 ADD to AC

• ADD to AC: Arithmetic addition operation

between AC and the memory word
specified by AR.

• D1T4: DR  M[AR]

• D1T5: AC  AC + DR, SC  0

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 Load to AC

• LDA: Load to AC.

• (Need 2 cycles since AC input is not

connected to the bus.)

• D2T4: DR  M[AR]

• D2T5: AC  DR, SC  0
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 Store AC
• STA: Store AC.

• D3T4: M[AR]  AC, SC  0

• BUN: Branch unconditionally. Transfers the

program to the instruction specified by AR. (Note
that the branch target must be in AR
beforehand.)

• D4T4: PC  AR, SC  0
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 Branch Unconditionally
• BUN: Branch unconditionally.

• Transfers the program to the instruction

specified by AR.
(Note that the branch target must be in AR
beforehand.)

• D4T4: PC  AR, SC  0

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 Branch and Save Return Address
• This instruction in is useful for branching to a position of
the program called a subprogram.

• BSA: Branch and save return address. Branch to

address AR and save PC address.

• BSA is used to implement a subroutine call.

• The indirect BUN instruction at the end of the subroutine

performs the subroutine return.

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 Branch and Save Return Address

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 Branch and Save Return Address
• Note that the above micro operations
require 2 cycles.

1. D5T4: M[AR]  PC, AR  AR + 1

(increment, INR AR)

2. D5T5: PC  AR, SC  0

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 Increment and skip if zero
• ISZ: Increment and skip if zero.

• Programmer usually stores a negative number in

the memory word (in two’s complement form).

• As this negative number is repeatedly

incremented by one, it eventually reaches zero.

• At that time PC is incremented by one in order to

skip the next instruction.

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 Increment and skip if zero
• Increment: M[AR] M[AR] + 1, if (M[AR] + 1 = 0)
then PC  PC + 1

• Increment and skip if zero requires 3 cycles.

– D6T4: DR  M[AR]

– D6T5: DR  DR + 1

– D6T6: M[AR]  DR, if DR=0 then

PC  PC + 1, SC  0

• The ISZ instructions is used to implement a loop.

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 FLOWCHART FOR MEMORY REFERENCE INSTRUCTIONS
Memory-reference instruction

AND ADD LDA STA

D0T 4 D1T 4 D2T 4 D 3T 4

DR M[AR] DR M[AR] DR M[AR] M[AR] AC
SC 0

D0T 5 D1T 5 D2T 5

AC AC DR AC AC + DR AC DR
SC 0 E Cout SC 0
SC 0

BUN BSA ISZ

D4T 4 D5T 4 D6T 4

PC AR M[AR] PC DR M[AR]
SC 0 AR AR + 1

D5T 5 D6T 5
PC AR DR DR + 1
SC 0
D6T 6
M[AR] DR
If (DR = 0)
then (PC PC + 1)
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 I/O instructions have as one operand the address of a port in the I/O
address space.

There are two classes of I/O instruction:

1. Those that transfer a single item (byte, word, or doubleword)

located in a register.

2. Those that transfer strings of items (strings of bytes, words, or

double words) located in memory. These are known as "string I/O
instructions" or "block I/O instructions".

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 In computing, input/output, or I/O, refers to the communication between an information
processing system (such as a computer), and the outside world possibly a human, or
another information processing system.

Inputs are the signals or data received by the system, and outputs are the signals or
data sent from it. The term can also be used as part of an action; to "perform I/O" is to
perform an input or output operation.

I/O devices are used by a person (or other system) to communicate with a computer.
For instance, a keyboard or a mouse may be an input device for a computer, while
monitors and printers are considered output devices for a computer. Devices for
communication between computers, such as modems and network cards, typically
serve for both input and output.

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 Note that the designation of a device as either input or output depends on
the perspective.

Mouse and keyboards take as input physical movement that the human
user outputs and convert it into signals that a computer can understand.

The output from these devices is input for the computer. Similarly, printers
and monitors take as input signals that a computer outputs. They then
convert these signals into representations that human users can see or
read.

For a human user the process of reading or seeing these representations

is receiving input. These interactions between computers and humans is
studied in a field called human–computer interaction.

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 In computer architecture, the combination of the CPU and main
memory (i.e. memory that the CPU can read and write to directly, with
individual instructions) is considered the brain of a computer, and from
that point of view any transfer of information from or to that combination,
for example to or from a disk drive, is considered I/O.

The CPU and its supporting circuitry provide memory-mapped I/O that is
used in low-level computer programming in the implementation of device
drivers.

An I/O algorithm is one designed to exploit locality and perform

efficiently when data reside on secondary storage, such as a disk drive.

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 I/O Interface is required whenever the I/O device is driven by the processor. The
interface must have necessary logic to interpret the device address generated by the
processor.

Handshaking should be implemented by the interface using appropriate commands

like (BUSY,READY,WAIT), and the processor can communicate with I/O device
through the interface.

If different data formats are being exchanged, the interface must be able to convert
serial data to parallel form and vice-versa. There must be provision for
generating interrupts and the corresponding type numbers for further processing by
the processor if required.

A computer that uses memory-mapped I/O accesses hardware by reading and writing
to specific memory locations, using the same assembler language instructions that
computer would normally use to access memory.
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 • In the hardwired the control logic is implemented with gates flip
flops, decoders and other digital circuit.

• It has the advantage that it can be optimized to produce a fast

mode of presentation

• Hardware methods fall into two categories: the processor's

hardware signals are generated either by hardwired control, in
which the instruction bits directly generate the signals, or
by microprogrammed control in which a dedicated microcontroller
executes a microprogram to generate the signals.

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 Before microprocessors, hardwired control usually was implemented
using discrete components, flip-chips, or even rotating discs or
drums. This can be generally done by two methods.

1. The classical method of sequential circuit design. It attempts to

minimize the amount of hardwire, in particular, by using only
log2p flip flops to realize a p state circuit.

2. An approach that uses one flip flop per state. While expensive in
terms of flip flops, this method simplifies controller unit design
and debugging.

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 Microcode is a layer of hardware-level instructions and/or data structures
involved in the implementation of higher level machine code instructions
in many computers and other processors; it resides in a special high-
speed memory and translates machine instructions into sequences of
detailed circuit-level operations.

It helps separate the machine instructions from the underlying electronics

so that instructions can be designed and altered more freely.

It also makes it feasible to build complex multi-step instructions while still

reducing the complexity of the electronic circuitry compared to other
methods.

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 Writing microcode is often called microprogramming and the
microcode in a particular processor implementation is sometimes
. called a micro program.

Modern microcode is normally written by an engineer during the

processor design phase and stored in a ROM and/or PLA structure,
although machines exist which have some writable microcode in
SRAM or flash memory.

Microcode is generally not visible or changeable by a normal

programmer, not even by an assembly programmer. Unlike machine
code which often retains some compatibility among different
processors in a family, microcode only runs on the exact electronic
circuitry for which it's designed
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 The elements composing a micro program exist on a lower conceptual level than a
normal application program.

Each element is differentiated by the "micro" prefix to avoid confusion:

microinstruction, micro assembler, micro programmer, micro architecture, etc.

Micro programs consist of series of microinstructions. These microinstructions control

the CPU at a very fundamental level of hardware circuitry.
.
Micro programs are carefully designed and optimized for the fastest possible
execution, since a slow micro program would yield a slow machine instruction which
would in turn cause all programs using that instruction to be slow.

In the micro-programmed control the control information is stored in a control

memory
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 It requires changes in the wiring among the various components if the
designed has to be modified or changed.

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 A single typical micrllowing operations:
Connect Register 1 to the "A" side of the ALU
Connect Register 7 to the "B" side of the ALU
Set the ALU to perform two's-complement addition
Set the ALU's carry input to zero
Store the result value in Register 8
Update the "condition codes" with the ALU status flags ("Negative",
"Zero", "Overflow", and "Carry")
Micro jump to Micro PC for the next microinstruction

To simultaneously control all processor's features in one cycle, the

microinstruction is often wider than 50 bits.
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 In common with many other complex mechanical devices, Charles
Babbage's analytical engine used banks of cams to control each operation,
i.e. it had a read-only control store. As such it deserves to be recognized as
the first micro-programmed computer to be designed.

Most models of the IBM System/360 series were micro-programmed.

1. The Model 25 was unique among System/360 models in using the top
16k bytes of core storage to hold the control storage for the micro-program.

2. The Model 85 had separate instruction fetch (I-unit) and execution (E-
unit) to provide high performance. The I-unit is hardware controlled. The E-
unit is micro-programmed; the control words are 108 bits wide on a basic
360/85 and wider if an emulator feature is installed.
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 Control memory is a random access memory (RAM) consisting of
addressable storage registers.

It is primarily used in mini and mainframe computers.

It is used as a temporary storage for data.

Access to control memory data requires less time than to main memory;
this speeds up CPU operation by reducing the number of memory
references for data storage and retrieval.

Access is performed as part of a control section sequence while the

master clock oscillator is running.
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 The control memory addresses are divided into two groups:

 A task mode and

 An executive (interrupt) mode.

Addressing words stored in control memory is via the address select logic
for each of the register groups. There can be up to five register groups in
control memory.

These groups select a register for fetching data for programmed CPU
operation or for maintenance console or equivalent display or storage of
data via a maintenance console or equivalent.
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 During programmed CPU operations, these registers are accessed directly by the
CPU logic.

Data routing circuits are used by control memory to interconnect

the registers used in control memory.

Some of the registers contained in a control memory that operate in the task and
the executive modes include the following:
•Accumulators
•Indexes
•Monitor clock status indicating registers
•Interrupt data registers

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 In computing, an interrupt is an asynchronous signal indicating the
need for attention or a synchronous event in software indicating the
need for a change in execution.

A hardware interrupt causes the processor to save its state of

execution and begin execution of an interrupt handler.

Software interrupts are usually implemented as instructions in

the instruction set, which cause a context switch to an interrupt handler
similar to a hardware interrupt.

An act of interrupting is referred to as an interrupt request (IRQ).

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 Interrupts can be broadly divided into the following.

Events occurring on peripherals devices:

A processor having initiated a control on a peripheral device on behalf of
one process may start some other process. When the transfer
terminates, the peripheral device will cause an interrupt.

Voluntary events within processes:

A process wishing to use the services of operating system may use a

specific type of interrupt, a supervisor call (SVC) as a means of notifying
the supervisor.

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 Involuntary events within the processes:

A process that attempts an undefined or prohibited action will cause an

interrupts that will notify the supervisor.

Action by operators:

An operation wishing to communicate with the supervisor may cause an

interrupt.

Timer interrupts:

many systems incorporate a timer that causes a fixed interval of time as

a means of guaranteeing that the supervisor will be entered periodically.
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 Interrupts are a commonly used technique for computer multitasking,
especially in real-time computing. Such a system is said to be
interrupt-driven.

Interrupt can be divided into three types:

1. Internal Interrupt

2. External interrupt

3. Software Interrupt

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 Internal interrupt arise from illegal or erroneous use of an instruction
or data. Internal interrupt are also called TRAPS.

Examples of interrupt caused by internal error conditions are

register overflow, attempt to divide by zero, an invalid operation
code, stack overflow, and protection violation.

These error conditions usually occur as a result of a premature

termination of the instruction execution.

An interrupt that is caused by processing, for example, a request

for input or output or an arithmetic overflow error.

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 External interrupt come from input/output devices, from a timing
device from a circuit monitoring the power supply, or from any other
external source.

Examples that cause external interrupt are I/O device requesting

transfer of data I/O device finished transfer of data, elapsed time of
event, or power failure.

External interrupts are a mechanism for I/O devices that communicate

infrequently with the CPU to get the attention of the CPU. Rather than
have the CPU constantly check to see if the I/O device needs
attention (this is polling), the device interrupts the CPU.

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 A software interrupt is initiated by executing an instruction.
Software interrupt is a special call/cell instruction that behaves like
an interrupt rather than a array subroutine call.

It can be used by the programmer to initiate an interrupt procedure

at any desired point in the program.

Software interrupts are essentially function calls to the operating

system. They can call the same handlers that external devices
call.

The most common use of software interrupt is associated with a

supervisor call instruction
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 CPU organization
The central processing unit (CPU) of a
computer is the main unit that dictates
the rest of the computer organization Control
Unit
• 1. Register set: Stores intermediate Arithmetic
data during the execution of instructions; Logic Unit
• 2. Arithmetic logic unit (ALU): Registers
Performs the required micro-operations
for executing the instructions;

• 3. Control unit: supervises the transfer

of information among the registers and
instructs the ALU as to which operation
to perform by generating control signals.

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 CPU Organization
• Central Processing Unit = “brain”
• Executes programs by:
– Fetching and decoding the next
instruction from memory
– Execute it
• Consists of:
– Control Unit
– Arithmetic Logic Unit (ALU)
– Registers (high-speed memory)
• Program Counter (PC)
Control • Instruction Register (IR)
Unit
Arithmetic
I/O Devices
Logic Unit
Main
Registers Disk Printer
Memory

Bus
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 General Register Organization
• CPU must have some working space (fast
access and close to CPU)

• This space is efficiently used to store

intermediate values

• The most convenient way to communicate

registers is trough common bus system

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 General Register Organization
Bus organization for 7 CPU
registers:

l2 MUX

lBUS A and BUS B

lALU

l3 X 8 Decoder

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 General Register Organization
• Bus organization for 7 CPU registers:
• 2 MUX: select one of 7 register or external data input by
SELA and SELB

• BUS A and BUS B : form the inputs to a common ALU

• ALU : OPR determine the arithmetic or logic microoperation

– The result of the microoperation is available for external data
output and also goes into the inputs of all registers

• 3 X 8 Decoder: select the register (by SELD) that receives

the information from ALU

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 General Register Organization
• An operation is selected by the ALU operation
selector (OPR).

• The result of a microoperation is directed to a

destination register selected by a decoder
(SELD).

• Control word: The 14 binary selection inputs (3

bits for SELA, 3 for SELB, 3 for SELD, and 5
for OPR)

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 Example 1 R1 R 2 R3
Binary selector input

l1)
MUX A selector
(SELA) : to place the
content of R2 into BUS A
l2)
MUX B selector
(SELB) : to place the
content of R3 into BUS B
l3) ALU operation
selector (OPR) : to
provide the arithmetic
addition R2 + R3
l4)Decoder selector
(SELD) : to transfer the
content of the output bus
into R1
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 Thank You

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