Tutorial: Subject Code: 2150707 Subject Name: Microprocessor & Interfacing

G.H.PATEL COLLEGE OF ENGINEERING AND TECHNOLOGY, V.V.
NAGAR
Department of Electronics and Communication Engineering
TUTORIAL
Subject Code: 2150707 Subject Name: Microprocessor & Interfacing
1 Explain Paging and Segmentation. 7
2 Explain the block diagram of 8259- Programmable Interrupt Controller. 7

3 List the four major processing units in an 80286 microprocessor and briefly describe 7 the
function of each.
4 How do 80386 switches from real mode to protected mode? How 80386 generate 7
address in protected mode and how it is mapped to physical address? What is the size of
each segment in protected mode?
5 List three major advances that 80386 microprocessor has over the 80286.Describe 7 how
the real mode operation of an 80286 is different from protected mode operation
6 How are tasks in an 80386 system protected from each other? How can operating 7
system kernel procedures and data be protected from access by application programs in
an 80386 system?
7 Briefly explain virtual 8086 mode of 80386. 7

8 Describe three major improvements that the 80486 processor has over 80386 7 processor
and three major improvements that the Pentium processor has over 80486 processor.
9 Explain the block diagram of 8255- Programmable Peripheral Interface.
Data Bus Buffer
This three-state bi-directional 8-bit buffer is used to interface the 8255 to the system data bus. Data is
transmitted or received by the buffer upon execution of input or output instructions by the CPU. Control
words and status informa-tion are also transferred through the data bus buffer.
Read/Write and Control Logic
The function of this block is to manage all of the internal and external transfers of both Data and Control or
Status words. It accepts inputs from the CPU Address and Control busses and in turn, issues commands
to both of the Control Groups.
(CS) Chip Select. A "low" on this input pin enables the communcation between the 8255 and the CPU.
(RD) Read. A "low" on this input pin enables 8255 to send the data or status information to the CPU on the
data bus. In essence, it allows the CPU to "read from" the 8255.
(WR) Write. A "low" on this input pin enables the CPU to write data or control words into the 8255.
(A0 and A1) Port Select 0 and Port Select 1. These input signals, in conjunction with the RD and WR
inputs, control the selection of one of the three ports or the control word register. They are normally
connected to the least significant bits of the address bus (A0 and A1).
(RESET) Reset. A "high" on this input initializes the control register to 9Bh and all ports (A, B, C) are set to
the input mode.
A1 A0 SELECTION
0 0 PORT A
0 1 PORT B
1 0 PORT C
1 1 CONTROL
Group A and Group B Controls
The functional configuration of each port is programmed by the systems software. In essence, the CPU
"outputs" a control word to the 8255. The control word contains information such as "mode", "bit set", "bit
reset", etc., that initializes the functional configuration of the 8255. Each of the Control blocks (Group A
and Group B) accepts "commands" from the Read/Write Control logic, receives "control words" from the
internal data bus and issues the proper commands to its associated ports.
Ports A, B, and C The 8255 contains three 8-bit ports (A, B, and C). All can be configured to a wide
variety of functional characteristics by the system software but each has its own special features or
"personality" to further enhance the power and flexibility of the 8255.
Port A One 8-bit data output latch/buffer and one 8-bit data input latch. Both "pull-up" and "pull-down"
bus-hold devices are present on Port A.
Port B One 8-bit data input/output latch/buffer and one 8-bit data input buffer.
Port C One 8-bit data output latch/buffer and one 8-bit data input buffer (no latch for input). This port can
be divided into two 4-bit ports under the mode control. Each 4-bit port contains a 4-bit latch and it can be
used for the control signal output and status signal inputs in conjunction with ports A and B.
10 Briefly explain 80386 descriptor.
Figure 5-2 shows in more detail how the processor converts a logical address into a linear addres
To perform this translation, the processor uses the following data structures:
1. Descriptors
2. Descriptor tables
3. Selectors
4. Segment Registers
5.1.1 Descriptors
The segment descriptor provides the processor with the data it needs to map a logical address into
descriptor formats. All types of segment descriptors take one of these formats. Segment-descriptor
BASE: Defines the location of the segment within the 4 gigabyte linear address space. The processor concatenates the th
LIMIT: Defines the size of the segment. When the processor concatenates the two parts of the limit field, a 20-bit value re
1. In units of one byte, to define a limit of up to 1 megabyte.

2. In units of 4 Kilobytes, to define a limit of up to 4 gigabytes. The limit is shifted left by 12 bits
Granularity bit: Specifies the units with which the LIMIT field is interpreted. When thebit is clear, the
TYPE: Distinguishes between various kinds of descriptors.
DPL (Descriptor Privilege Level): Used by the protection mechanism (refer to Chapter 6 ) .
Segment-Present bit: If this bit is zero, the descriptor is not valid for use in address transformation; the processor will sign
locations marked AVAILABLE. Operating systems that implement segment-based virtual memory clear the present bit in
1. When the linear space spanned by the segment is not mapped by the paging mechanism.
2. When the segment is not present in memory.
Accessed bit: The processor sets this bit when the segment is accessed; i.e., a selector for the des
periodically testing and clearing this bit, monitor frequency of segment usage.
Creation and maintenance of descriptors is the responsibility of systems software, usually requiring the cooperation of co
11 How 32-bit linear address is converted to physical address when paging is enabled? 7
Illustrate with proper example.
12 Explain the meaning and use of Selector and GDTR with proper example.
13 Explain the Page Table and Page Directory Entry with example.
14 What is descriptor table? What is its use? Dedifferentiate between GDT and LDT.
Descriptor Tables
Segment descriptors are stored in either of two kinds of descriptor table:
3. The global descriptor table (GDT)

4. A local descriptor table (LDT)
A descriptor table is simply a memory array of 8-byte entries that contain descriptors, as Figure 5-5 shows. A descri
The processor locates the GDT and the current LDT in memory by means of the GDTR and LDTR registers. These regis
access to the LDTR.
Descriptor Tables
Segment descriptors are stored in either of two kinds of descriptor table:
 The global descriptor table (GDT)

 A local descriptor table (LDT)
A descriptor table is simply a memory array of 8-byte entries that contain descriptors, as Figure 5-5 shows. A descrip
registers store the base addresses of the tables in the linear address space and store the segment limits. The instructions
15 What are privilege levels? What is their use? Give the role of call gates.
16 Explain the architectural features of ARM7 microprocessor.
17 Explain the SUN SPARC Microprocessor architecture.

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G.H.PATEL COLLEGE OF ENGINEERING AND TECHNOLOGY, V.V.

Department of Electronics and Communication Engineering

1 Explain Paging and Segmentation. 7

2 Explain the block diagram of 8259- Programmable Interrupt Controller. 7

7 Briefly explain virtual 8086 mode of 80386. 7

9 Explain the block diagram of 8255- Programmable Peripheral Interface.

Data Bus Buffer

Read/Write and Control Logic

Group A and Group B Controls

1. In units of one byte, to define a limit of up to 1 megabyte.

3. The global descriptor table (GDT)

 The global descriptor table (GDT)

16 Explain the architectural features of ARM7 microprocessor.

17 Explain the SUN SPARC Microprocessor architecture.

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