Compte Rendu Du TP1: Réalisé Par: SLIMANI Mouhssine Encadrée Par: ASMAE HAFIAN
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redCompte Rendu Du TP1: Réalisé Par: SLIMANI Mouhssine Encadrée Par: ASMAE HAFIAN
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redUniversité sidi Mohammed ben Abdallah
Faculté des sciences Dhar El Mahraz Fès
Département de Physique
Filière LP Systèmes Mécatroniques et Embarqués
Module : Systèmes Embarqués
Compte rendu du TP1
Réalisé par : SLIMANI Mouhssine
Encadrée par : ASMAE HAFIAN
Année Universitaire : 2018 / 2019
Porte logique Ou :
Programme :
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entityporteOU is
port (
I1: in std_logic;
C1: in std_logic;
S: out std_logic);
endporteOU;
architectureOu OF porteOU is
BEGIN
processOU:process(I1,C1)
BEGIN
S<= I1 or C1 after 1 ns;
end process processOU;
endOu;
Simulation :
Porte logique ET :
Programme :
Library IEEE;
Use IEEE.STD_LOGIC_1164.all;
ENTITY PorteET1 IS
port (
A1: in Std_Logic ;
B1: in Std_Logic ;
S1: out Std_Logic );
END PorteET1;
ARCHITECTURE Comportementale1 OF PorteET1 IS
BEGIN
ProcessPorteET1 : PROCESS(A1,B1)
begin
S1 <= B1 AND A1 AFTER 1 ns;
END PROCESS ProcessPorteET1;
END Comportementale1;
Simulation :
Circuit logique Y=(A.B)+C
Programme :
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entitytestetou IS
port(
A:in std_logic;
B:instd_logic;
C:instd_logic;
Y:outstd_logic);
endtestetou;
architectureporteETOU of testetou IS
component porteET1
port (
A1: in std_logic;
B1: in std_logiC;
S1: out std_logic
);
end component;
Simulation :
componentporteOU
port (
I1: in std_logic;
C1: in std_logiC;
S: out std_logic
);
end component;
signal S2 : std_logic:='Z';
BEGIN
U1: porteET1 port map (A1=>A,B1=>B,S1=>S2);
U2: porteOU port map (I1=>S2 ,C1=>C, S=>Y);
endporteETOU;
Porte logique inverseuse :
Programme :
library IEEE;
use IEEE.STD_LOGIC_1164.all;
ENTITY PorteINV IS
port(
A: in Std_Logic ;
S: out Std_Logic );
END PorteINV;
ARCHITECTURE INV OF PorteINV IS
BEGIN
S <= not(A) AFTER 1 ns;
END Comportementale1;
Simulation :
Multiplexeur 2 vers 1 :
Programme :
Multiplexeur 2 vers 1 :
Programme :
library ieee;
use ieee.std_logic_1164.all;
entity multiplixeur is
port
(
a:in std_logic;
b:in std_logic;
sel:in std_logic;
z:out std_logic);
end multiplixeur;
architecture multiplixeur1 of multiplixeur is
begin
p1:process(sel,a,b)
begin
if (sel='0') then
z <= a;
else z <= b;
end if;
end process;
Simulation :
end multiplixeur1;
Décodeur 1 parmi 8 :
Programme :
library ieee;
use ieee.std_logic_1164.all;
entity decodeur is
port(
x: in std_logic_vector(2 downto 0);
s: out std_logic_vector(7 downto 0)
);
end decodeur;
architecture dec_arch of decodeur is
begin
with x select s<=
"00000001" when "000",
"00000010" when "001",
"00000100" when "010",
"00001000" when "011",
"00010000" when "100",
"00100000" when "101",
"01000000" when "110",
"10000000" when "111",
"00000000" when others;
end dec_arch;
Simulation :
