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Lab12 - Sequence Detector

This document provides instructions for a lab activity on designing a sequence detector circuit using T flip-flops. Students are asked to: 1. Complete the sequential design method and design a circuit to detect the 10110 sequence using T flip-flops. 2. Draw the Mealy state diagram and determine that 3 T flip-flops are needed. 3. Provide the state table and obtain the simplified output and flip-flop input equations. 4. Draw the complete circuit diagram using T flip-flops and external NAND gates. 5. Implement the sequence detector in hardware and demonstrate it to the instructor.

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Muhammad Asim
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© © All Rights Reserved
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166 views

Lab12 - Sequence Detector

This document provides instructions for a lab activity on designing a sequence detector circuit using T flip-flops. Students are asked to: 1. Complete the sequential design method and design a circuit to detect the 10110 sequence using T flip-flops. 2. Draw the Mealy state diagram and determine that 3 T flip-flops are needed. 3. Provide the state table and obtain the simplified output and flip-flop input equations. 4. Draw the complete circuit diagram using T flip-flops and external NAND gates. 5. Implement the sequence detector in hardware and demonstrate it to the instructor.

Uploaded by

Muhammad Asim
Copyright
© © All Rights Reserved
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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Department of Electrical Engineering

Faculty Member: __Dr.Huma Ghafoor___ Dated: ____9/5/2019_________

Semester: _________2nd______________ Section: ______BSCS-8C_____

Group No.: 6

EE-221: Digital Logic Design

Lab 12: Sequence Detector

PLO4/CLO4 PLO4/CLO4 PLO5/CLO5 PLO8/CLO6 PLO9/CLO7


Name Reg. No Viva / Lab Analysis Modern Ethics and Individual Total
Performanc of data in Tool Usage Safety and Team marks
e Lab Report Work Obtained

5 Marks 5 Marks 5 Marks 5 Marks 5 Marks 25 Marks


Muhammad Asim 254089
Khan

Abdul Moiz Asif 263802

Hassan Munir Ahmad 243211

EE-241: Digital Logic Design Page 1


Lab12: Sequence Detector

This Lab Activity has been designed to familiarize the students with design and
implementation of a sequence detector that detects 10110 from an incoming binary stream
received serially. The students are expected to do the following:-

 Complete the Sequential Design Method


 Design the circuit using T Flip-Flops
 There are related questions at the end of this activity. Give complete answers.
Use diagrams if needed for clarity.
 The students are required to complete Pre-Lab work before coming to the lab and
submit lab report before leaving.

Pre-Lab Tasks:
1. We wish to design a circuit with single input x, and a single output z, that detects an
overlapping sequence 10110 in a string of bits coming through an input line. We start it in
the initial state S0. In our design the detector circuit will only advance to the next state if
some valid bit of the specified sequence is received, otherwise will go back to either S0 or
any other state depending upon whether sequence breaks totally or partially. As and
when complete sequence is received, the detector circuit will output 1.

There are two FSM models for your design. Name these models and give advantages/
disadvantages of each? Which method you prefer and why? (1 Mark)

The two FSM models are Mealy FSM and Moore FSM

Advantage of Mealy: Mealy leads to reduction in number of states

Advantage of Moore: Advantage of Moore model is easy to code, it is simplification of the design.

Disadvantage of Mealy: Mealy is complicated compared Moore.

Disadvantage of Moore: It leads to slower because of clocking the output but leads to stable output

Preferred: Mealy

EE-241: Digital Logic Design Page 2


Draw the Mealy state diagram for this sequence detector. How many T Flip-Flops would
you need for implementing this sequence detector and why? (5 Marks)

3 T flip flops will be required

2. List the State Table (3 Marks)

Present Sate Input Next State Output Flip Flop Inputs


Q3 Q2 Q1 x Q3+ Q2+ Q1+ z T3 T2 T1
0 0 0 0 0 0 0 0 0 0 0
0 0 0 1 0 0 1 0 0 0 1
0 0 1 0 0 1 0 0 0 1 1
0 0 1 1 0 0 1 0 0 0 0
0 1 0 0 0 0 0 0 0 1 0
0 1 0 1 0 1 1 0 0 0 1
0 1 1 0 0 1 0 0 0 0 1
0 1 1 1 1 0 0 0 1 1 1
1 0 0 0 0 1 0 1 1 1 0
1 0 0 1 0 0 1 0 1 0 1

101, 110, 111 are don’t cares

EE-241: Digital Logic Design Page 3


3. Obtain the simplified equations for Output z and Flip-Flop Inputs using map method.

(3 Marks)

EE-241: Digital Logic Design Page 4


4. . Draw complete circuit diagram for the sequence detector using T flip flops and external
NAND gates (3 Marks)

Lab

Tasks:
5. Implement the sequence detector in hardware and show results to your Instructor/Lab
Engr. (10 Marks)

Remarks by Teacher/Lab Engineer:

EE-241: Digital Logic Design Page 5

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