2012 Comparative Evaluation of MC and Voltage DC-Link Back-To-Back Converter Systems

IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 59, NO.
12, DECEMBER 2012 4487
Comparative Evaluation of Three-Phase AC–AC

Matrix Converter and Voltage DC-Link
Back-to-Back Converter Systems
Thomas Friedli, Member, IEEE, Johann W. Kolar, Fellow, IEEE,
Jose Rodriguez, Fellow, IEEE, and Patrick W. Wheeler, Member, IEEE
Abstract—This paper introduces the methodology and the re- for example, the lack of voltage step-up capability and/or the
sults of a comprehensive comparison of a direct matrix con- limited maximum output voltage, and thus would not justify the
verter (MC), an indirect MC, and a voltage dc-link back-to-back higher implementation effort that they assume in comparison to
converter for a 15-kW permanent magnet synchronous motor
drive. The comparison involves the investigation of the passive V-BBCs.
components, including the EMI input filter, the required silicon Despite the broad spectrum of partially very detailed and
chip area for a defined maximum admissible thermal loading in-depth investigations, research work performing a compre-
of the power semiconductors, the total losses and/or achievable hensive comparison of direct ac-ac converter topologies for
efficiency, a prediction of the resulting volume and weight of the drive applications is comparatively rare. Most of the investi-
passive components, and, finally, a tradeoff study between the
efficiency, volume, and weight of the converters. Different perfor- gations focus on a performance comparison based on semi-
mance indicators that ultimately allow a systematic determination conductor loss calculations or measurements. In [1]–[3], the
of the application area of each converter topology are provided semiconductor losses and the design of the CMC and VSBBC
with this comparative evaluation. are compared to identify the potential benefits and risks of
Index Terms—Comparative evaluation, matrix converter (MC), the MC technology. Reference [3] suggests an electrothermal
voltage dc-link back-to-back converter (V-BBC). simulation-based approach to analyze the thermal stress of the
power semiconductors of the CMC and V-BBC. A rather novel
I. I NTRODUCTION approach in academia is comparisons based on power cycling
tests of the semiconductors [4], considering the amplitude of
I N ACADEMIA, matrix converters (MCs) have been consid-
ered for more than three decades as a main future concept
for a wide range of industrial applications and, more recently,
the cyclic changes of the power semiconductor junction tem-
peratures which can be related to the semiconductor lifetime
and thus also to the converter system lifetime. However, other
also for “more electric aircraft” applications. However, despite
converter features such as the volume of passive components
intensive research, MCs have, until now, only achieved a low
or EMI, which have an important impact on the overall con-
market penetration. The most widely used bidirectional low-
verter performance, are often neglected. A systematic and more
voltage ac-ac converter topology in industry remains the two-
complete converter topology evaluation is presented in [5] on
level voltage dc-link back-to-back converter (V-BBC). The
ac-dc-ac converter systems for applications on aircraft.
proponents of the MC technology argue that the direct ac-ac
The main objective of this paper is to show the methodology
power converters without intermediate energy storage elements
and criteria required for a systematic and comprehensive ac-
would not only permit a more compact implementation but
ac converter system evaluation and to perform a comprehen-
would also considerably increase the system lifetime due to
sive comparison of the conventional (direct) MC [CMC; cf.,
the absence of the dc-link capacitor. On the contrary, crit-
Fig. 1(a)], the indirect MC [IMC; cf., Fig. 1(b)], and the
ics claim that MCs would not provide significant advan-
V-BBC [cf., Fig. 1(c)] for low-voltage and low-power appli-
tages that would compensate for their limitations, such as,
cations (≤ 100 kW) based on a 15-kW permanent magnet
synchronous motor (PMSM) drive system.
Manuscript received June 30, 2011; revised September 27, 2011; accepted
October 31, 2011. Date of publication December 9, 2011; date of current
Section II first gives an overview of the main properties
version July 2, 2012. of the MC and V-BBC and highlights the similarities and
T. Friedli and J. W. Kolar are with the Power Electronic Systems Labora- differences between the two converter concepts. Then, a brief
tory, ETH Zurich, 8092 Zurich, Switzerland (e-mail: [email protected];
[email protected]).
overview of the modulation schemes considered and the main
J. Rodriguez is with the Department of Electronics Engineering, Uni- converter control loops is given. Section III is dedicated to the
versidad Tecnica Federico Santa Maria, Valparaiso 2390123, Chile (e-mail: passive components and derives the basic relations between
[email protected]).
P. W. Wheeler is with the School of Electrical and Electronic Engi- the volume, weight, and losses of capacitors and inductors.
neering, University of Nottingham, Nottingham NG7 2RD, U.K. (e-mail: In Section IV, the essential considerations for a volume-
[email protected]). optimized design of the passive components, including the EMI
Color versions of one or more of the figures in this paper are available online
at http://ieeexplore.ieee.org. input filter, are demonstrated for all three converter topologies.
Digital Object Identifier 10.1109/TIE.2011.2179278 Section V summarizes the main properties of the selected power
0278-0046/$26.00 © 2011 IEEE

4488 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 59, NO. 12, DECEMBER 2012
Fig. 2. Characteristic waveforms of the CMC for Φ1 ≈ 0 and Φ2 = π/9

(inductive load). (a) Input line voltage i1a , input current i1a , and input current
ī1a averaged over TP . (b) Output line voltage uA , output line voltage ūA
averaged over TP , and output line current iA .
V-BBC is performed. Finally, in Section VIII, a compilation

of the key findings is provided, including a decision-guidance
using nine different performance indicators for the selection
of an adequate converter topology with respect to an intended
application. This paper concludes with a discussion of suitable
application areas for MCs in the field of low-voltage drive
systems.
II. K EY C ONVERTER P ROPERTIES

Forced commutated ac-ac converter topologies without any
intermediate energy storage are referred to as MCs [6]. They
can provide simultaneous amplitude and frequency transforma-
tion of three-phase voltage–current systems. Their operating
principle is based on the constant power flow in a symmetrical
three-phase voltage–current system. The CMC performs the
voltage and current conversion in one stage. As an alternative,
the IMC features a two-stage (indirect) power conversion. The
CMC and IMC topologies are equivalent regarding their basic
functionality. Their different physical implementation merely
results in a different loading of the semiconductors and a
different commutation scheme. Compared to the (two-level)
V-BBC, MCs are inherently “quasi three-level” converters as
all three instantaneous (but obviously not constant) line-to-line
input voltages can be applied to the converter output terminals
(cf., [6, Figs. 13 and 21]). The V-BBC is a two-stage topology
that is formed by a back-to-back connection of a voltage-
source-type input and an output stage, which are decoupled by
the dc-link capacitor CDC . The (boost) inductors LB enable
power factor correction at the input under √ the restriction of
Fig. 1. Considered converter topologies (only the first stage of the EMI input boost operation of the input stage (UDC > 6U1 ).
filter, which is required for the basic operation, is shown). (a) CMC. (b) IMC.
(c) V-BBC. In summary, MCs require impressed voltages at the input
(input capacitors CF ) and impressed currents at the output
semiconductor devices and then discusses the design relevant (inductive load). In contrary, V-BBCs have impressed currents
operating points and their impact on the semiconductor losses at the input (boost inductors LB ) and output (inductive load).
and stress considering the mission profile of the drive system. Figs. 2–4 show the characteristic waveforms of the CMC, IMC,
Next, the motivation and procedure for a semiconductor-area- and V-BBC when supplying a three-phase ohmic-inductive
based comparison are described, and the thermal design of the load.
semiconductors and the cooling system is defined. Section VI
summarizes the assumptions and models of the auxiliary com-
A. Voltage Step-Up Capability
ponents such as the control and measurement hardware. Based
on the criteria, models, and methods of comparison identified Output voltage step-up capability (boost operation) is a de-
and derived in the previous sections, ultimately, in Section VII, sirable feature of converter systems for drive applications as
the actual comparative evaluation of the CMC, IMC, and it enables a less conservative motor design and ultimately a
FRIEDLI et al.: COMPARATIVE EVALUATION OF THREE-PHASE AC–AC MC AND V-BBC SYSTEMS 4489
the switching sequence of the output stage is repeated for two

different link voltage levels u. The advantage of this modulation
scheme is that the switching state of the input stage can be
changed during the freewheeling state of the output stage, when
no current flows in the link (i = 0), and thus, no special com-
mutation strategy is required for the IMC. No switching losses
occur in the input stage apart from losses due to component
parasitics. An alternative modulation scheme that enables zero-
voltage switching of the output stage is described in [6]–[9],
but it is not further considered as it requires a voltage/current-
dependent commutation and leads to a lower efficiency at part
load. The CMC requires a multistep commutation strategy to
guarantee safe commutation. In this paper, a conventional four-
step commutation sequence (cf., [6, Fig. 22]), based on the
Fig. 3. Characteristic waveforms of the IMC for Φ1 ≈ 0 and Φ2 = π/9
measured input voltages and the measured output currents, is
(inductive load). (a) Input line voltage u1a , input current u1a , and input current selected. The selected modulation scheme for the input and
ī1a averaged over TP . (b) Link voltage u and link current i. (c) Output line output of the V-BBC [cf., [6, Fig. 5(b)]] is synchronized to
voltage uA , output line voltage ūA averaged over TP , and output line current
iA .
minimize the current ripple of the dc-link capacitor.
A more detailed description of the modulation and commu-
tation scheme considered is provided in [6]. The modulation
schemes selected have in common that, in total, six relative
turn-on times need to be calculated per pulse period for all
converter topologies. In terms of commutation safety, the CMC
represents the most critical solution, followed by the IMC and
the V-BBC.
C. Control
The main control properties of the individual converter
topologies for a basic feedback control scheme of a motor drive
are briefly discussed. There is no significant difference between
the CMC and IMC from a point of view of control. Hence, it is
sufficient to restrict the considerations to MCs in general.
Fig. 4. Characteristic waveforms of the V-BBC for Φ1 ≈ 0 and Φ2 = π/9 The motor control of the MC and V-BBC is basically identi-
(inductive load). (a) Input voltage u1a , input voltage ū1a averaged over TP , cal and typically consists of an outer speed control loop and
and input line current ia . (b) DC-link voltage uDC , dc-link currents iDC,1 , and two inner current control loops for the d- and q-axis stator
iDC,2 . (c) Output line voltage uA , output line voltage ūA averaged over TP ,
and output line current iA . currents. The motor control is actually the whole feedback
control required for a simple MC-based drive system [buck-
better usage of√the motor. The maximum output voltage of MCs type control equivalent; cf., [6, Fig. 36(c) and (d)]]. The
is limited to 3/2 ≈ 86% of the input voltage for sinusoidal V-BBC requires another three control loops for its input stage
modulation, and hence, the control can only compensate input [boost-buck-type control equivalent; cf., [6, Fig. 36(a)]]: one
voltage sags as long as the maximum voltage transfer ratio is outer control loop for the dc-link voltage and two inner loops
not reached. As opposed to MCs, V-BBCs inherently provide for the d- and q-axis input currents that are impressed in the
voltage step-up (boost) functionality and thus are able to main- boost inductors. As opposed to V-BBCs, MCs do not allow
tain the nominal output voltage also at reduced input voltages. for feedback control of the input currents independent of the
load currents, which affects the input current quality and leads
to a typical input current THD of 5% for standard switching
B. Considered Modulation Schemes
frequencies (e.g., 8 kHz) of low-voltage variable-speed drives.
The basic functionality, the electrical properties, and the More advanced control schemes such as direct torque control or
semiconductor losses of ac-ac converters are significantly de- model predictive control can also obviously be applied to MC
termined by the implemented modulation schemes. In this and have been investigated in detail [10], [11].
comparison, for all three converter topologies, discontinuous
space vector modulation schemes with loss optimal clamping
D. Reactive Power Compensation
are considered, as described in [6] and [7], which provide two
active and one zero state per pulse period TP . Another preferable characteristic of three-phase ac-ac con-
A modulation scheme is used for the IMC (cf., [6, Fig. 14]), verters is the capability to supply or absorb reactive input
which enables zero-current switching (ZCS) of the input stage power in order to compensate the capacitive currents drawn
in which, for a complete switching sequence of the input stage, by the input filter or to perform power factor correction or
active damping. Assuming a proper design, the reactive power TABLE I

C ONVERTER D ESIGN , M OTOR , AND L OAD S PECIFICATIONS
compensation capability of V-BBCs is limited primarily by
the component ratings, whereas for MCs, there are different
restrictions imposed by the topology. The formation of real
input power P1 and reactive input power Q1 can be quantified
by the subsequent equations, for standard modulation schemes
of MCs, whereby the converter losses are neglected
√
3 3
P1 = M12 Û1 Iˆ2 cos (Φ∗1 ) cos(Φ2 ) (1)
4
√
3 3
Q1 = M12 Û1 Iˆ2 cos (Φ∗1 ) sin(Φ2 ) (2)
4
2 Û2 1
M12 = √ = [0 . . . 1] (3)
3 Û1 cos (Φ∗1 )
where Û1 represents the amplitude of the input line voltage, Iˆ2
is the amplitude of the output line current, M12 is the mod-
ulation index [voltage transfer ratio; cf., [6, eqs. (12)–(19)]],
Φ∗1 is the desired (reference) current-to-voltage displacement
angle at the converter input, and Φ2 is the current-to-voltage
displacement angle at the converter output. Thus, it appears that
the formation of reactive input power is only possible if the
real power flow is different from zero and that the maximum
reactive input power decreases with an increasing displacement
angle Φ2 . The maximum output voltage achievable depends on
the desired current-to-voltage displacement angle at the input,
which is represented by the definition of the modulation index
M12 in (3).
Special hybrid modulation schemes, suggested in [12] and
[13], allow for decoupling the real power transfer from the
reactive power transfer and, hence, also enable, for example,
the formation of reactive input power for a purely reactive load
(Φ2 = ±π/2). However, if the instantaneous output currents of
the MC are equal to zero (zero apparent output power, S2 = 0),
in principle, no reactive input power can be provided, neither
with standard nor with extended hybrid modulation schemes.
On the contrary to the MC, the V-BBC does not have such
a restriction due to its intermediate energy storage and can
provide reactive power at the input also at zero output current.
The input power factor control is implemented for both
the MC and the V-BBC by adding an offset to the reference
displacement angle Φ∗1 at the converter input.
Fig. 5. Volume VC versus capacitance C of polypropylene dc, X2, and Y2
capacitors (B320xx-, B3277x-, and B3292x-series; EPCOS) for an operating
temperature of 85 ◦ C.
E. Specifications
The considered specifications for the CMC, IMC, and
V-BBC, including the motor and the assumed mission (load) A. Capacitors
profile, are shown in Table I. If not specified otherwise, they The following considerations are restricted to polypropylene
are valid throughout this paper. foil capacitors which allow for a long enough lifetime. Two
characteristic foil capacitor types are utilized for ac-ac convert-
ers: dc-link and EMI suppression capacitors. The component
III. PASSIVE C OMPONENTS
characteristics and ratings of different manufacturers are very
Passive components have a significant impact on the overall similar. EPCOS is the reference manufacturer selected.
converter losses, volume, weight, and lifetime due to their Fig. 5 shows the scaling of the boxed volume of the foil
physical properties and must therefore be considered when capacitors selected. The corresponding model parameters, in-
comparing different converter concepts. cluding the ranges of validity, are summarized in Table II.
TABLE II 2) EMI Suppression Capacitors: In this comparison, X2

DC-L INK AND X2 C APACITOR M ODEL PARAMETERS
and Y2 capacitors, both rated for a continuous rms voltage
of 305 V, are considered for EMI suppression. The X-type
capacitors are used for differential mode (DM) filtering, and the
Y-type capacitors are used for common mode (CM) filtering.
The boxed volume of the considered X2 capacitors for
a given operating voltage and an operating temperature of
TCX2 = 85 ◦ C can be written as
VCX2 |UX2 = k1,V,CX2 · CX2 + k2,V,CX2 . (8)
The resulting losses of polypropylene X2 EMI suppression

capacitors are typically significantly lower than that for an
equally sized dc-link capacitor in a V-BBC as the current ripple
injected into the input filter capacitors is low for typical voltage-
source-type input stages. The losses are accordingly determined
mainly by the reactive currents generated by the mains voltage
and are uncritical for 50/60-Hz applications. Exceptions are
the input filter capacitors CF of MCs (and, in general, for
current-source-type converters) as they absorb the switched
1) DC-Link Capacitors: The volume per capacitance scales (rectangular-shaped) line currents. The series resistance of the
with the rated voltage UC and the surge voltage capability. If the considered X2 capacitors is approximately two to three times
relation between volume and capacitance (for a given voltage larger than that for the selected dc-link capacitors of equal
class) is evaluated, for instance, for the dc-link capacitors capacitance as an assembly structure with a higher pulse peak
(B3277x-series; EPCOS), it is found that the volume scales, for voltage capability is required for mains application. The result-
a given rated voltage, linearly with the capacitance and, for a ing ESR of the X2 capacitors can be approximated by
given capacitance, approximately with the square of the rated k
CX2 2,RS,X2
voltage, which is proportional to the stored energy ESRCX2 |UX2 = k1,RS,X2 · . (9)
F
VC |UC ∝ C and ∝ UC2 . (4)
An additional important constraint for the X2 capacitors is
DC-link capacitors (800 V) are selected for the V-BBC due given by the maximum admissible voltage rise and fall time,
to the specified dc-link voltage of 700 V and for providing a which, however, is not modeled for this investigation.
margin of 100 V for transient voltage variations. The resulting The Y2 capacitors have a marginal impact on the filter
scaling between the boxed volume VCDC of the dc-link capaci- volume and the losses as the maximum allowable capacitance
tors and the capacitance, evaluated for an operating temperature is limited by the specified current in the protective earth (PE)
TCDC = 85 ◦ C, yields to conductor and is small compared to the required DM input
capacitors. The maximum CM capacitance value, assuming a
VCDC |UDC = k1,V,CDC · CDC + k2,V,CDC . (5) maximum tolerable PE current of ICM,Y,max = 3.5 mA for a
400-V/50-Hz mains system, is then limited to
The capacitor losses scale with the volume of the dielectric
material and, thus, with the capacitance and the resulting cur- ICM,Y,max
CCM,max ≤ = 48.4 nF. (10)
rent ripple. The resulting total losses can be modeled with 2πU1 f1
an equivalent series resistance (ESR). The ESR represents the
By inspection of the curves in Fig. 5, it can be seen that the Y2
dielectric and the ohmic (skin effect) losses of the metallic
capacitance value hardly contributes to the overall filter volume
contacts for the considered polypropylene capacitor technol-
and is accounted for with a default volume of 10 cm3 .
ogy. Evaluated for a current ripple frequency of 10 kHz (the
The resulting mass of the capacitors can be calculated by
frequency dependence of the ESR is neglected), the ESR of the
utilizing the average density of foil capacitors ρC
selected dc-link capacitors can be expressed as
k mC |UC = ρC · VC . (11)
CDC 2,ESR,CDC
ESRCDC |UDC = k1,ESR,CDC · . (6)
F
In order to meet the lifetime requirements (e.g., ≥ 100 000 h) B. Inductors
of the dc-link capacitors, the rms current ripple of the dc-link
capacitors needs to be limited. The maximum tolerable current 1) DM Inductors: DM inductors are required to implement
ripple, determined for a current ripple frequency of 10 kHz and the boost inductors of the V-BBC and the DM filter inductors
an operating temperature of 85 ◦ C, is then given by of all topologies. In this comparison, toroidal powder core
inductors are considered. They provide a good compromise
ICDC ,rms |UDC = k1,IC ,rms · CDC + k2,IC ,rms . (7) between the achievable inductance per volume and ac and dc
TABLE III
H IGH F LUX 60 C ORE M ATERIAL AND I NDUCTOR PARAMETERS
Fig. 7. Resulting boxed volume of the designed DM inductors using High

Flux 60 powder core material (Magnetics) for the nominal peak inductor current
IˆL = 32.5 A and different inductance as a function of rtor . The minimum
achievable core volumes are marked with circles. The resulting optimal core
dimensions are, for example, ator,opt = 3.1 cm, htor,opt = 8.0 cm, and
rtor,opt = 3.1 cm for IˆL = 32.5 A and LDM = 1.0 mH.
Fig. 6. (a) Top view of the considered toroidal DM inductor. (b) Core cross
section with core dimensions.
magnetization properties. In order to minimize the parasitic

winding capacitance, only single-layer designs are considered.
The material selected is the powder core alloy High Flux HF 60, Fig. 8. Boxed volume VLDM versus inductance LDM of the designed single-
manufactured by Magnetics. A summary of the core material layer toroidal DM inductors for different peak DM inductor currents using High
Flux 60 powder core material (Magnetics). The top view and cross section are
data is given in Table III. shown in Fig. 6.
The main inductor parameters are the inductance at zero cur-
rent LDM,0 , the inductance at the peak current value LDM , and
coating thickness of dct /2 = 0.05 mm is assumed. The resul-
the rms inductor current IL,rms at a given frequency and tem-
tant boxed volume of the DM inductors can then be calculated
perature. Based on these quantities, the inductors are designed
as a function of the core radius rtor
such that the desired DM inductance
√ LDM is provided at the
2
peak inductor current IˆL = 2IL,rms and that the inductance ator + 3dw,tot
value drops at the peak current to γμ = 80% of its initial value VL,box = 4 rtor + (htor + 3dw,tot ). (14)
2
at zero current. The peak inductor current, which corresponds to
the nominal converter input current, is equal to IˆDM = 32.5 A The minimum inductor volume and, thus, the optimal radius of
for an estimated converter efficiency ηest = 95%. The core data the toroidal core rtor,opt are found by minimizing (14)
are extracted from the manufacturer data. The core dimensions
(cf., Fig. 6) are optimized to minimize the boxed volume of the VLDM |IL (rtor,opt ) = min VL,box |IˆL (rtor ) (15)
DM inductors. The width ator and the height htor of the core are
expressed as a function of the radius rtor of the toroidal core for as shown in Fig. 7.
that purpose and the aforementioned constraints In analogy to the capacitors, the inductor volume scales, for a
given peak current, approximately linearly with the inductance
dw,tot (IˆL + 2Hmax rtor γtt ) and, for a given inductance, approximately with the square of
ator (rtor ) = 2rtor − (12)
IˆL the peak current, which again corresponds to the stored energy
IˆL2 LDM VLDM |IL ∝ L and ∝ IˆL2 . (16)
htor (ator , rtor ) = 2 a
. (13)
2πμ0 μr γμ Hmax tor rtor
The resulting relation between the boxed volume of the DM
The total wire diameter dw,tot is selected such that a maxi- inductor and the inductance is shown in Fig. 8 for different peak
mum rms current density Jw,max of 6 A/mm2 results, providing inductor currents and may be written as
a good compromise between the resulting volume and losses for
the selected core material and inductor design. An insulation VLDM |IL = k1,V,LDM · LDM + k2,V,LDM . (17)
TABLE IV
DM I NDUCTOR M ODEL PARAMETERS
Fig. 9. Boxed volume VLCM versus the absolute value of the impedance
|ZLCM | of the three-phase toroidal CM inductors for different peak DM
inductor currents using Vitroperm 500 F nanocrystalline tape-wound core
material (Vacuumschmelze).
The ratio between the mass of the core material and the TABLE V
CM I NDUCTOR M ODEL PARAMETERS
copper wire within the boxed inductor volume is not constant.
The mass of the inductor thus has to be estimated by
mLDM |IL ≈ k1,m,LDM · LDM + k2,m,LDM (18)
for a given inductor current IL .

The dc wire resistance of the DM inductors can be calcu-
lated by
k2,R,L
LDM DM
RDC,LDM |IL = k1,R,LDM · . (19)
H
If not specified otherwise, the wire temperature is assumed as

TwCu = 85 ◦ C. The DM inductor parameters are compiled in
Table IV.
The major loop core losses at the mains frequency, referred to
as low-frequency (LF, i.e., 50 Hz) core losses, are modeled with
the standard Steinmetz equation. If the Steinmetz parameters fabricated of Vitroperm 500 F core material. The main design
were known as a function of the dc bias of the core, the HF parameters of a CM inductor are the impedance |Z CM | (inser-
core losses could be determined by a calculation approach tion loss) provided at a certain frequency, the CM saturation
based on the modified Steinmetz equation according to [14]. current and/or the corresponding voltage-time area product, and
The pragmatic approach chosen here is to perform core loss the inductor current. In order to minimize the parasitics, again
measurements on sample inductors with a square-wave voltage a single-layer winding design is assumed with a winding sector
that is generated with a switched bridge-leg. The measurement angle of 100◦ each.
results prove that, for the selected DM inductor design, the As opposed to the DM inductors, the CM inductor model is
core losses hardly depend on the resulting dc bias of the minor based on standard core sizes (VAC W409, W380, and W424)
loop and that the HF core losses can be approximated by the and substantiated by inductor impedance measurements as the
maximum amplitude B̂Δi,max of the resulting flux density of selected core material features strongly nonlinear characteris-
the current ripple in the inductor tics to enable simple scaling of the core geometry. The scaling
α β law for the boxed volume of the CM inductor volume, evaluated
B̂Δi,max fsw at 100 kHz, is modeled with
Pcore,HF,LDM ≈ k · · . (20)
T Hz
VLCM |ILDM = k1,V,LCM · |Z CM | + k2,V,LCM . (21)
This quasi-linear loss behavior results from the selected core
material and the applied inductor design, limiting the variation The impedance of the CM inductor at fZCM = 100 kHz and the
of the relative permeability in operation to γμ = 80% of its equivalent (small-signal) resistance are then given by
initial value μr,ini .
2) Three-Phase CM Inductors: Toroidal cores from Vacu- |Z CM ||ILDM = (2πfZCM · LCM )2 + RS,Z,L 2
CM
(22)
umschmelze (VAC) are considered for the three-phase CM filter
inductors with a tape-wound nanocrystalline core, which is RS,Z,LCM |ILDM = k1,RS ,LCM · LCM + k2,RS ,LCM . (23)
Fig. 10. EMI input filter topology considered. CDM,1 corresponds to the input capacitors CF of the MCs. The boost inductors LB of the V-BBC, colored
in gray, are connected to the terminals a1 , b1 , and c1 and represent the DM filter inductors LDM,1 of the input filter. Over-voltage protection devices such as
varistors or components for inrush current control or precharging of the dc-link capacitor in case of the V-BBC are not shown.
Finally, the leakage inductance can be approximated by TABLE VI

CE L IMITS AT THE M AINS T ERMINALS FOR C LASS B
E QUIPMENT ACCORDING TO CISPR 11
Llk,LCM |ILDM ≈ k1,lk,LCM · LCM + k2,lk,LCM . (24)
The relationship between the boxed volume of the CM induc-

tors and the impedance is shown in Fig. 9, and the inductor
model parameters are summarized in Table V.
The mass of the CM inductor is modeled with
mLCM |ILDM ≈ k1,m,LCM · |Z CM | + k2,m,LCM (25)
in a similar manner as that for the DM inductors. The impact of the PMSM on the DM input current can be
An rms current density of 8 A/mm2 is assumed for the CM neglected for the DM filter design. However, for the CM filter
inductors, leading to a dc wire resistance of design, a second-order equivalent circuit of the CM impedance
Z M,CM,HF of the load is used. The impedance is parameterized
RDC,LCM |ILDM = k1,RDC ,LCM · |Z CM | + k2,RDC ,LCM . (26) based on measurement results of a PMSM (LST-series, LTi
Drives), including a 3-m-long motor cable
CM inductors generate core losses similar to any other mag- 1
netic component. However, for the filter topology (cf., Fig. 10) Z M,CM,HF = + j2πf LM,CM + RM,CM
j2πCM,CM
and switching frequency range considered, the losses of the CM
inductors are dominated by the copper losses, and hence, the CM,CM = 2 nF LM,CM = 435 nH RM,CM = 2.1 Ω.
core losses can be neglected. (27)
The impedance parameters are valid within the frequency range
IV. PASSIVE C OMPONENT AND EMI F ILTER D ESIGN of 100 kHz to 5 MHz, which is sufficient for the CM filter de-
The EMI input filter should allow for a highly efficient sign. In order to ensure that the CM inductors do not saturate in
power transfer at the mains frequency with a minimal voltage- the frequency range of the electrical input and output frequency
to-current phase lag and should meet the specified conducted of the converter, the low-frequency CM impedance of the load
emission (CE) EMI levels (cf., Table VI) and power quality Z M,CM,LF has to be determined, which, for the sake of brevity,
standards. Additionally, in order to avoid oscillations that could is not shown.
occur at resonance frequencies of the input filter above the The parasitic capacitance of the semiconductors to the

converter input current control bandwidth and/or around the heat sink per unit area can be approximated by CSM,PE ≈
switching frequency, passive damping has to be provided. In 2
20 pF/cm . The omission of CSM,PE in the derived DM and
the frequency range of the input current control bandwidth, CM equivalents (cf., Fig. 12) is justifiable to determine the
filter resonances should be avoided. filter volume as the capacitance of the load Z M,CM,HF is
approximately ten times larger than the expected maximum
value of CSM,PE .
A. LISN and Load
The DM noise of the CMC and IMC is virtually identical
A detailed description of the CE measurement chain can within the considered EMI measurement range from 150 kHz
be found in [15] and [16]. It consists of the following main to 30 MHz for the selected modulation schemes, and the
components: the line impedance stabilizing network (LISN), CM noise spectrum differs mainly in the low-frequency range
the EMI test receiver, the power converter, and the load (motor). at multiples of the input and output frequencies. Thus, it is
The LISN for the required three-phase converters is modeled sufficient to consider in the following paragraphs the EMI filter
with three single-phase 50-Ω/50-μH LISNs. requirements for MCs in general.
B. Filter Topology
Although different advanced filtering concepts have been
introduced for ac-ac converters, as, for instance, in [17] for
the CMC, in this comparison, a conventional multistage LC
filter topology is applied in order to enable comparability with
typical EMI filters of ac-ac converters. The filter topology
considered is shown in Fig. 10. CDM,1 corresponds to the input
filter capacitors CF of the CMC and IMC. The boost inductors
LB of the V-BBC are connected to the terminals a1 , b1 , and c1
and represent the DM filter inductors LDM,1 of the first filter
stage.
The main attenuation is achieved with the first two DM and
CM stages. The third capacitor stage CDM,3 together with the
DM leakage inductance Llk,CM,2 of LCM,2 is used to suppress
the HF noise typically above 5 MHz and thus hardly contributes
to the overall filter volume.
C. Filter Design Procedure

The suggested filter design procedure is demonstrated by the
flowchart in Fig. 11. It is performed with a custom-developed
automated filter design software that incorporates the filter
transfer function, the second-order equivalents of the passive
components, and the models of the CE measurement setup. In
a first step, the considered EMI filter topology (cf., Fig. 10), the
EMI standard for CE (i.e., CISPR 11, class B, and 150 kHz–
30 MHz), and the load parameters have to be determined.
1) Reactive Power Limitation of the Input Filter: Special
attention has to be given to the sizing of the DM input filter
capacitors, particularly to the size of the input capacitors CF of
the MC, in order to meet the requirements for the input power
factor. A reasonable measure is to restrict the total reactive
power drawn by the input filter to 15% of the nominal converter
output power P2,nom . In respect of [6, eq. (19)], the desired
maximum current-to-voltage displacement angle Φ∗1,max at the
input of the MC can be varied for a practical implementation
within −25◦ to 25◦ in order to limit the corresponding reduction Fig. 11. Flowchart of the design procedure for the EMI input filter and the
ac-side passive components at the converter input.
of the output voltage to 90% of the maximum output voltage.
The suggested design guideline enables the provision of a of the type W380 (3 × 5 turns, IˆLDM = 32.5 A; cf., Fig. 9)
unity input power factor down to a minimum output power is selected for LCM,2 , and CCM,1 is set to CCM,1 = 3.3 nF.
P2,Φ1 =1,min of one third of the nominal output power The remaining CM capacitance (CCM,max − 3 · CCM,2 )/3 is
0.15P2,nom ηest equally distributed to CCM,1 = 12.7 nF. This approach is bene-
P2,Φ1 =1,min =
≈ 0.31 · P2,nom (28) ficial for the following two reasons: first, the size and, therewith,
tan Φ∗1,max
the impedance of LCM,1 are significantly larger compared to
and an estimated converter efficiency of ηest = 95%. This leads LCM,2 , leading to a nonnegligible leakage (DM) inductance
to a maximum DM capacitance per input phase of Llk,CM,1 that can be used to partly implement LDM,2 . Second,
due to the comparatively small size of LCM,2 , the component
CDM,max = 45 μF (29) parasitics are low and thus still enable a high CM impedance
above 5 MHz.
for a line-to-line voltage of 400 V (rms), a mains frequency of 3) Input Capacitors CF and Boost Inductors LB : The input
50 Hz, and a nominal converter output power P2,nom = 15 kW. capacitors CF have to be dimensioned for a maximum peak-
2) Constraints for CM Design: The selected CM filter strat- to-peak voltage ripple ΔuCF,pp,max as the measured capacitor
egy is to provide most of the required CM attenuation between voltage is required for the sector detection of the applied space
150 kHz and 1 MHz with the first CM stage implemented by vector modulation or may even determine the commutation
CCM,1 and LCM,1 and, in the case of the V-BBC, also with sequence as in the case of the CMC. The maximum peak-to-
the boost inductors, and the attenuation above 1 MHz with peak voltage ripple across the input capacitors should be limited
the second stage, given by CCM,2 and LCM,2 . A VAC core to δuC,pp,max = 20% of the input voltage amplitude Û1 based
on practical experience. In order to enable safe operation, in

this paper, ΔuCf ,pp,max is limited to δuC,pp,max = 10%. The
required capacitance can then be calculated by
Iˆ2
CF = CF,Δu = . (30)
4Û1 fsw δuC,pp,max
The switching frequency fsw in the aforementioned equation

refers to the switching frequency of the output stage when
considering the IMC. The maximum voltage ripple across the
input capacitors is obtained for Φ2 = 0 for the considered
modulation schemes of the two MCs.
To meet the dynamic requirements that are imposed by
the load and/or the control, for all of the converter concepts
considered, a minimal internal energy storage is required,
which, in the case of the MC, is mainly provided by the
input capacitors CF . It is hence reasonable from a control
perspective to constrain the voltage drop ΔuCF across the input
capacitors during transient operation, leading to an additional
control-based constraint for CF . However, for the converter and
load specifications considered (cf., Table I), the ripple-based
design criterion according to (30) is more conservative than
the control-based one. Accordingly, this is not further discussed
here. The corresponding equations can be found in [18]. Fig. 12. Simplified DM and CM conducted EMI emission equivalent circuits
In analogy to the filter input capacitors CF , the boost in- for (a) MC and (b) V-BBC.
ductors LB of the V-BBC are designed based on the current
ripple at the switching frequency fsw for a given input voltage
amplitude Û1 and a dc-link voltage UDC . In this comparison,
they are dimensioned for a maximum peak-to-peak current
ripple ΔiLB,pp,max of δiL,pp,max = 20% of the fundamental
input current amplitude Iˆ1 . The inductance value of the boost
inductors can be calculated as follows:

1 3Û12
LB = LB,Δi = Û1 − . (31)
Iˆ1 fsw δiL,pp,max 2UDC
Attention has to be paid to converter stability when reducing

the boost inductance with increasing switching frequencies. Fig. 13. Required DM and CM attenuations AttDM and AttCM for the MC
The theory and methodology for investigating the ac system and V-BBC at fsw = 8 kHz and a switching frequency fsw = 32 kHz.
stability are described in [19] and [20]. A practical rule of
thumb is that the minimum boost inductance LB,min should be capacitors CF of the MC or the boost inductors LB of the
at least eight to ten times larger than the inner mains inductance V-BBC.
LN for switching frequencies below 100 kHz 5) Completion of Filter Design: Finally, the remaining filter
components are designed using algorithms that minimize the
LB,min = 400 μH ≈ 8 . . . 10 · LN LN,typ = 50 μH. (32) overall filter volume. It should be noted again that CDM,3 is
used to provide attenuation above 5 MHz, which requires small
4) DM and CM Filter Equivalent Circuits: The filters are capacitance values and therefore hardly contributes to the filter
designed for nominal converter operation to meet the CISPR volume. Its design is mainly determined by the parasitics of the
11 class B quasi-peak standard for CE levels (150 kHz– other components, which are not shown here for the sake of
30 MHz) that is compiled in Table VI. The used DM and CM brevity.
equivalent circuits are shown in Fig. 12. A detailed description The capacitance range for the MC of CDM,2 is defined by
of the derivation of the equivalent circuits can be found in
[7]. The required DM and CM input filter attenuations AttDM CDM,2 ≤ min(CF , CDM,max − CF ). (33)
and AttCM of the MC and V-BBC to meet the specified EMI
standard are shown in Fig. 13 for a switching frequency of This constraint ensures that the reactive power drawn by the
8 and 32 kHz. The attenuation values presented refer to the filter is limited as desired, and the larger DM capacitor of CF
(additional) attenuation that has to be provided by the input and CDM,2 (if they are not equal) is always placed closest to the
filter without the attenuation that is already given by the input converter input stage. In consequence, the input filter always
and is not a key design criterion for the filter. Therefore, the
constraint in (33) can be weakened
CDM,max
CDM,2 = CDM,1 ≤ (38)
2
and the capacitances of CDM,1 and CDM,2 are selected to be
equal for simplicity. The rest of the DM filter design algorithm
does not vary compared to the MC. The design equation that
is used to obtain the component values of CDM,2 , LDM,2 , and
LDM,2d under the condition of a minimum filter component
volume may then be written as
Fig. 14. CF = CDM,1 and CDM,2 capacitance values versus the switching
frequency for the considered EMI input filter design for MCs. VCDM,1 + VCDM,2 = VLDM,2 + VLDM,2d . (39)
Next, the impedance of LCM,1 is calculated to meet the CM

provides the lowest filter output impedance at terminals a1 ,
attenuation requirements. Finally, the resulting filter transfer
b1 , and c1 for the given component values. The DM damping
function is analyzed to avoid any occurrence of resonances
inductors LDM,2d are designed depending on LDM,2
at critical frequencies such as the switching frequency or the
beginning of the CE measurement range at 150 kHz.
LDM,2d = n · LDM,2 , n = 0.5 (34)
leading to a good compromise between damping performance D. DC-Link Capacitor

and additional volume with respect to LDM,2 . The inductors In a similar manner as that for the input capacitors CF of the
LDM,2d and resistors RDM,2d are used to damp oscillations that MC, a minimum dc-link capacitance needs to be determined to
may occur between CDM,1 , CDM,2 , and LDM,2 . RDM,2d is de- meet the dynamic requirements and to enable safe operation.
termined in respect of [21] to ensure an optimally damped filter The worst case considered for the V-BBC occurs for a step
stage, which means to minimize the peak output impedance of change from nominal motor operation to no load, which is
the input filter. The resistance RDM,2d that provides optimal initiated by the load and therefore cannot be precontrolled
damping for a given choice of LDM,2d can be calculated as (prevented) by the converter control. This load change is more
severe than a change from motor to generator operation as,
LDM,2,tot n(3 + 4n)(1 + 2n) in such a case, the power reversal of the input and output
RDM,2d = . (35) stage would be coordinated to minimize the transient dc-link
CDM,1 2(1 + 4n)
voltage variation. In order to limit the relative overshoot of
Ultimately, the values of CDM,2 and LDM,2 are determined the dc-link voltage δuDC = ΔuDC /UDC , a minimal dc-link
such that capacitance is required, which can be calculated, based on [18]
(cf., Section III-B), by
VCDM,2 = VLDM,2 + VLDM,2d (36) P2
CDC,ctrl ≥ 2
18UDC δuDC ηest
and (33) as well as (34) are fulfilled. This algorithm always ⎛ ⎞
√
leads to the smallest resultant total volume of CDM,2 , LDM,2 , 3L P 36ηest ⎠
and LDM,2d independent on the volumetric scaling of the DM ·⎝ √ B 2 + (40)
2
U1 U√DC
2U1 + 3 U DC fsw
capacitors and inductors (cf., [7] and [22]) under the constraint
that CDM,2 ≤ CF and the capacitive reactive power of the
assuming regular sampling and a maximum dead time of two
filter is minimized. Thereby, the value of the filter capacitance −1
pulse periods (2TP = 2fsw ).
CF = CF,Δu is designed based on the voltage ripple criterion
The minimum dc-link capacitance may also be determined
given in (30). However, for the filter topology selected and
by an energy-based dimensioning guideline as an extension
switching frequencies above 35 kHz (cf., Fig. 25), a lower
to the control-based design. Energy-based criteria are applied
passive component volume can be obtained if
to ensure a certain ride-through capability and robustness
or can be considered as a simplification of (40) when the
CDM,2 = CF ≥ CF,Δu . (37)
dc-link voltage and the switching frequency vary only within
a small range. Typical values for compact low-voltage drive
The voltage-ripple-based design criterion for CF and the allow- trains reported in [22] are within 5 to 10 μF/kVA. Thus, for the
able design spaces considered for CDM,2 are shown in Fig. 14 case at hand, the minimum dc-link capacitance to enable robust
depending on the switching frequency. operation is assumed with
Slightly different DM filter design algorithms are applied for
the V-BBC as the reactive power caused by the input filter can μF
CDC,rob ≥ 7.5 · S2,nom = 110 μF (41)
be compensated independent of the output power of the V-BBC kVA
Fig. 15. Volume of the passive components of the MC Vpas,MC versus

switching frequency fsw .
Fig. 17. Characteristic operating points of a bidirectional drive system, shown
in two quadrants of the torque-speed (M −n) plane.
their performance and the variety of available devices and

semiconductor modules. Both devices are rated for a maximum
junction temperature of 175 ◦ C. Although it is known that
CMCs are often implemented with reverse-blocking IGBTs
(RB-IGBTs), in this comparison, conventional IGBTs are used
as only a few manufacturers of RB-IGBTs exist and also higher
switching frequencies are considered.
B. Design-Relevant Operating Points

Fig. 16. Volume of the passive components of the V-BBC Vpas,V−BBC In this comparison, it is assumed that the mission profile
versus switching frequency fsw . requires continuous duty (S1 operation) mainly for nominal
motor and generator operation (cf., Table I). It is hence essential
and the required dc-link capacitance is then selected to identify adequate operating points for the dimensioning
according to of the power semiconductors and for the semiconductor loss
calculation. A method to determine the required operating
CDC = max(CDC,ctrl , CDC,rob ). (42)
points is to consider the operating range of the drive system
An additional design criterion for the dc-link capacitance is in the torque-speed plane. The semiconductor losses of three-
to limit the voltage variation with twice the mains frequency for phase ac-ac converters are modulated with the electrical input
two-phase operation; however, this is not considered here. frequency f1 and/or output frequency f2 of the converter. This
means that, the lower the resulting frequency that modulates the
semiconductor losses is, the more is the modulation (pulsation)
E. Volume of Passive Components of the losses, resulting in a variation of the semiconductor
junction temperature TJ for a given thermal impedance of the
Finally, the passive components and the EMI input filters of
semiconductor chip. In order to ensure a minimum semiconduc-
the MC and the V-BBC are designed with the dimensioning
tor lifetime, the amplitude of the cyclic junction temperature
guidelines derived in Sections IV-A–D. Figs. 15 and 16 show
variation ΔTJ,max and the maximum junction TJ,max have to
the total boxed volume of the passive components for the MC
be limited for the main operating range of the mission profile.
and V-BBC, including the contribution of the individual com-
Fig. 17 shows the design-relevant operating points for con-
ponent volumes in the dependence of the switching frequency
tinuous operation that have been identified in the torque-speed
from 8 to 32 kHz. It can be seen that, for the MC, the share
plane based on the aforementioned considerations. It is suffi-
of the individual component volumes is balanced, whereas for
cient to consider only two instead of four quadrants for reasons
the V-BBC, the volume of the passive component is dominated
of symmetry.
by the boost inductors under the applied constraint of a small
dc-link capacitance. 1) OP1/OP5: motor/generator operation at nominal
motor speed (nominal electrical output frequency
f2 = ±f2,nom , |f2 | > |f1 |) and nominal motor torque
V. S EMICONDUCTOR D ESIGN AND L OSSES MM,nom .
2) OP2/OP4: motor/generator operation at reduced motor
A. Semiconductor Selection
speed (the electrical output frequency is equal to the input
The power semiconductors considered are fourth-generation frequency f2 = ±f1 ).
Trench and Field-Stop T&FS 1200 V silicon IGBT4 devices 3) OP3: motor operation at electrical standstill (the elec-
and emitter controlled EmCon4 diodes from Infineon due to trical output frequency is equal to zero f2 = 0 Hz) and
at standstill torque MM,0 . At this operating point, it

is assumed that the output voltage is equal to 2% of
the topology-dependent maximum output voltage level
(ohmic voltage drop of cable and motor).
The operating points at nominal operation (OP1 and OP5)
and at standstill (OP3) are relevant for all three ac-ac converter
topologies from the point of view of an application.
C. Required Semiconductor Chip Area

Semiconductor-related comparisons of power converters are
frequently applied. A commonly used method is to compare
different converter topologies by determining the losses us- Fig. 18. Typical progression of the junction temperature TJ (t) over time
for the CMC, IMC, and V-BBC at f2,nom = 140 Hz, showing the different
ing the same semiconductors for all topologies, as shown in characteristic patterns of the (periodic) junction temperature variation.
[23]–[26]. In this approach, the semiconductors have to be
selected such that they fulfill the ratings of all of the con-
verter topologies compared, and thus, they are not necessarily Fig. 18 shows typical waveforms of the junction temperature
matched to the individual topologies. TJ for the CMC, IMC, and V-BBC at OP1. The junction
In order to enable a comparative evaluation with semicon- temperature of the IMC/V-BBC is modulated with the output
ductors matched to each converter topology, a semiconductor- frequency, whereas in case of the CMC, the progression of
chip-area-based converter comparison (SABC) is introduced the junction temperature depends on the input and output
[27]. The basic idea is that, if the same transistor and diode chip frequencies and on the phase-angle between the current–voltage
configuration is implemented in different converter topologies systems at the input and output. The impact of these properties
and is analyzed regarding losses and thermal stress, it is most on the performance of the CMC is discussed in Section VII.
likely that, for one topology, the transistor chip is overdi- In this comparison, the semiconductors of CMC, IMC, and
mensioned and the diode chip is underdimensioned, whereas V-BBC are designed for continuous nominal motor and gen-
for an another topology, the opposite is true. That is exactly erator operation (OP1 and OP5) with the algorithm shown in
where the SABC provides benefits. The implemented algorithm Fig. 19 for the SABC to determine the minimum required
allows the calculation of the minimum required semiconductor semiconductor chip area. The additional operating points are
area for the individual transistor and diode chips for a given then investigated to further characterize the performance of the
converter topology, operating point, and semiconductor module three converter systems. The relevant design constraints can be
assembly such that the maximum junction temperature TJ,max , summarized as follows.
the average junction temperature TJ,avg , or the maximum junc- 1) The minimum chip areas of the individual transistors
tion temperature variation ΔTJ,max of the individual transistor and diodes are determined such that all three converter
and diode chips are equal or less than a predefined maximum systems can supply/absorb the nominal electrical output
value. This method does not only guarantee optimal chip area power P2,nom = ±15 kW at the nominal output fre-
partitioning and semiconductor material usage but also provides quency |f2 | = 140 Hz such that the required lifetime of
a common basis for converter topology comparisons: the re- 10 a (cf., Table I) can be achieved. For that purpose,
quired total semiconductor chip area. The chip area data can the maximum cyclic junction temperature variation is
then be directly used to determine the semiconductor costs. limited to ΔTJ,max = 10 K, and the maximum junction
Another advantage seen in the SABC is that, with the junction temperature is limited to TJ,max = 140 ◦ C for nominal
temperature variation, the average junction temperature, and the operation (OP1/OP5) at 90% of the corresponding maxi-
respective energy loss, the reliability of the semiconductors can mum converter output voltage and a heat sink temperature
also be predicted [28]. beneath the semiconductor module of TS = 95 ◦ C in re-
The transistor and diode current rating is proportional to the spect of the reliability data provided by the manufacturer
active chip area Achip,act , whereas the resulting thermal im- [29], [30].
pedance between the junction and the heat sink Zth,JS depends 2) Custom designs for the PMSMs with nominal motor volt-
on the total chip area Achip > Achip,act , the semiconductor ages UM,nom,MC and UM,nom,V−BBC and stator induc-
module assembly (shown in Fig. 21), and the cooling system. tances LS,MC and LS,V−BBC matched to the converter
The electrical equivalent circuit of the thermal impedance is output voltage ranges of the MC and V-BBC are assumed
modeled with an RC network and can be written as a complex (cf., Table I).
transfer function Gth,JS (ω). The resulting time behavior of the 3) The switching frequency applied to the motor is identical
junction temperature TJ (t) can be calculated using the heat sink for all three converter topologies and is selected to be
temperature TS (t) according to equal for the input and output stages of the V-BBC
(Fig. 20).
TJ (t) = TS (t) + F −1 Gth,JS (ω) · Pchip (ω) (43)
The margin between TJ,max = 140 ◦ C and the maximum
with reference to [18, Sec. 5.1.1]. specified junction temperature of 175 ◦ C is required to enable
Fig. 21. (a) Cross section of the semiconductor module assembly considered.
(b) Typical thermal FEM simulation result of a single chip for the module
assembly at the left, showing the heat spreading.
current-, chip-area-, and temperature-dependent semiconductor

loss equations (cf., [18, Sec. 4]).
1) Conduction Losses: The instantaneous transistor and
diode conduction losses pcond,S/D are modeled with an active
chip area AS/D,chip,act and junction temperature TJ dependent
forward voltage drop US/D,F and a differential forward resis-
tance rS/D,F , leading to
pS/D,cond = US/D,F (AS/D,chip,act , TJ ) · iS/D

+ rS/D,F (AS/D,chip,act , TJ ) · i2S/D (44)
where iS/D denotes the instantaneous transistor or diode

current.
2) Switching Losses: The instantaneous transistor or diode
switching losses pS/D,sw are calculated based on switching
loss energy functions of the transistor or diode wS/D,tot . These
switching loss energy functions model the loss energies of an
entire switching cycle (turn-on and turn-off) depending on the
active chip area AS/D,chip,act , the switched current iS/D , the
switched voltage uS/D , and the junction temperature TJ . For
Fig. 19. Simplified flowchart of the SABC. the transistors, the turn-on and turn-off losses are considered,
whereas for the diodes, only the reverse-recovery (turn-off)
losses are modeled
pS/D,sw = fsw · wS/D,tot (AS/D,chip,act , iS/D , uS/D , TJ ).

(45)
E. Semiconductor Module
1) Module Assembly: In order to determine the thermal
impedance between the semiconductor junction and the heat
sink, a well-defined thermal interface between the chip and
the heat sink and/or power the power semiconductor module
construction is required. A model of a semiconductor module is
Fig. 20. Transient thermal impedance Zth,JS for various chip areas and a developed for that purpose, inspired by the EconoPACK3 from
CSPI of 11 W/(Kdm3 ), calculated with the semiconductor module model.
Infineon. The cross section of the selected module assembly is
shown in Fig. 21.
safe shutdown, when an over-current limit at 200% of the 2) Thermal Impedance: The dependence of the thermal im-
respective nominal converter output current is assumed. pedance Zth,JS between the semiconductor junction and the
heat sink on the total chip area is determined by transient
thermal simulations with the simulation software ICEPAK. It
D. Semiconductor Models
is shown in [31] that, for an optimized custom-made aluminum
The required semiconductor loss and chip size data of the heat sink with forced air-cooling, a cooling system performance
IGBT4 devices and EmCon4 diodes are determined based on a index (CSPI) between 10 and 12 W/(Kdm3 ) can be imple-
statistical analysis of power module data sheets and manufac- mented with a justifiable manufacturing expenditure. Assuming
turer data. The extracted data are related to a set of voltage-, an average CSPI of 11 W/(Kdm3 ), the specific thermal power
TABLE VII
S EMICONDUCTOR M ODULE AND G ATE D RIVER M ODEL PARAMETERS
Fig. 22. (a) Schematic profile and (b) cross section of a heat sink element,
showing the dimensions and the direction of the air flow.
given gate charge QG , the losses generated in the gate resistor

flow through the heat sink cooling surface can be calculated can be calculated by
and is then used to define the boundary conditions required
PG = QG (UGE/S,max − UGE/S,min )fsw (49)
for the thermal simulations. The resulting thermal impedance
curves, shown in Fig. 20, are approximated with fourth-order nC
QG = 6.5 AS,chip,act + 4.5 nC. (50)
RC foster networks and interpolated with chip-area-dependent mm2
functions as the thermal impedance is inversely proportional to
the total chip area. The functions for R1...4,th,JS and τ1...4,th,JS , The losses in the gate resistor can be utilized to estimate the
the step response, i.e., the transient thermal impedance between resulting gate driver losses Pdrv . A model of a gate driver circuit
the junction and the heat sink, can be expressed as a function of is developed for that purpose, comprising an H-bridge oscillator
the chip area by solving the differential equation resulting from and a transformer for the galvanically isolated gate driver power
the RC network and substitution supply, a magnetic coupler for the gate signal isolation, and
a gate driver IC with a half-bridge MOSFET output stage.

4 −t
The power consumption of the driver IC is derived from the
Zth,JS (Achip , t) = Ri,th,JS 1 − e τi,th,JS
. (46) IXDN4xx gate driver series from IXYS and is verified with
i=1 the results of gate driver power consumption measurements.
The overall power consumption of a gate driver may then be
3) Volume and Mass: The total required semiconductor chip approximated by the empirical equation
area of a power electronic converter can be used to determine
the volume of its semiconductor module. The ratio ξAchip−SM PG
Pdrv ≈ 1

+ 0.1 W (51)
between the total implemented chip area of a semiconductor 0.053 ln Hz fsw + 0.074
module Achip,SM and the area of the base plate ASM needs
to be determined for that purpose. Considering commercial derived in [18] and thus can be expressed with (49) as a
power modules, a realistic value for ξAchip−SM is found to be function of the active chip area and the switching frequency (the
15%. Assuming a constant height of the semiconductor module constant term of 0.1 W accounts for the standby losses of the
of hSM = 15 mm, the volume of the module can then be gate driver).
calculated by
Achip,SM G. Cooling System

VSM = · hSM . (47)
ξAchip−SM 1) Heat Sink Profile: The cooling system design aims for
a simple and compact construction with an average CSPI of
Finally, the mass of the semiconductor module can be esti- 11 W/(Kdm3 ) as assumed for the simulation of the semicon-
mated by the average density ρSM found for commercial power ductor module (cf., Section V-E). The demanded characteristics
modules can be achieved with a forced air-cooled optimized aluminum
heat sink as suggested in [32]. The schematic profile and the
Achip,SM
mSM = VSM · ρSM = · hSM · ρSM . (48) cross section of a single heat sink element are shown in Fig. 22.
ξAchip−SM Such a heat sink element consists of a high-performance
12-V dc fan from Sanyo Denki (SanAce 40, GA-series) and
The main semiconductor module model parameters are com- a custom-made aluminum heat sink with a variable length lS ,
piled in Table VII. a width wS = 40 mm, and a height hS = 46 mm. Depending
on the cooling requirements and the base plate area of the
semiconductor module, nS heat sink elements are arranged
F. Gate Driver
in parallel, thus forming a heat sink to obtain the required
The SABC also enables the estimation of the losses of thermal resistance of the cooling system. The components and
the gate driver as the active transistor chip area AS,chip,act dimensions of the designed cooling system are summarized in
is proportional to the gate charge. With a difference between Table VIII.
the maximum and minimum gate–emitter UGE/S,max = +15 V 2) Thermal Resistance: The thermal resistance of the cool-
and UGE/S,min = −3 V and a switching frequency fsw , for a ing system between the heat sink and the ambient air Rth,CS is
TABLE VIII TABLE IX

C OOLING S YSTEM M ODEL PARAMETERS PARAMETER OVERVIEW OF THE AUXILIARY C OMPONENTS
requirement, the V-BBC has to be implemented with a brake

chopper connected across the dc-link capacitor. Additional
protection circuitry, ideally integrated with the auxiliary supply,
is necessary for the CMC and IMC. Thereby, it is assumed that
the auxiliary supply is implemented with a three-phase diode
rectifier that is connected to the input phases√and thus provides
a dc-bus voltage of approximately Uaux = 6U1 . In order to
provide a path for the motor currents during mains phase loss,
for the CMC, an additional three-phase diode rectifier needs
to be connected between the output phases and the dc input
Uaux of the auxiliary supply [33], [34]. The IMC requires only
two additional power diodes that are connecting the rails of
the intermediate link to the dc input of the auxiliary supply
[35]. In order to provide a similar protection capability for the
CMC and IMC, the three-phase diode rectifiers at the input
and output of the CMC are implemented by utilizing the same
total chip area as is required for the freewheeling diodes of
Fig. 23. Thermal resistance Rth,CS of the cooling system depending on its
length lCS and width wCS .
the output stage of the IMC. The two protection diodes of the
IMC are dimensioned for the resultant nominal link current.
determined according to [32, eqs. (11)–(14)]. The heat sink (cf., A brake chopper [33], [36] is connected across the dc-bus of
Fig. 22) is modeled by the thermal resistance of the base plate, the auxiliary supply in a similar manner as that for the V-BBC.
the fins, and the interface between the fin surface and the air The chopper IGBTs of all converter topologies are dimensioned
flow through the heat sink. The resulting thermal resistance of for a continuous current that is equal to the peak output
the cooling system Rth,CS can then be represented as a function current.
of the length lCS and width wCS of the cooling system. In
Fig. 23, the thermal resistance of the designed cooling system
is plotted as a function of its length VI. AUXILIARY C OMPONENTS

1 A. Control and Measurement
2
Rth,CS = k1,RCS lCS + k2,RCS lCS + k3,RCS · . (52)
wCS The control and measurement hardware includes a DSP, a
FPGA, and analog and digital circuitries. The main system
3) Volume and Mass: The volume of the cooling system
quantities that need to be measured are the following:
VCS is the boxed volume of the heat sink and the fans and is
modeled using the length lCS and width wCS of the cooling 1) for the CMC/IMC, the input voltages ua , ub , and uc ; the
system dc input voltage of the auxiliary supply uaux ; and the
output currents iA , iB , and iC ;
VCS = (k1,VCS lCS + k2,VCS ) · nS wS . (53) 2) for the V-BBC, the three input voltages ua , ub , and uc ;
the dc-link voltage uDC ; the input currents ia , ib , and ic ;
Using the density of aluminum and the mass of a fan, the and the output currents iA , iB , and iC .
total mass of the cooling system mCS can be calculated with
the length lCS and width wCS of the cooling system Additionally, for all topologies, the motor speed is sensed,
and the base plate temperature of the semiconductor module,
mCS = (k1,mCS lCS + k2,mCS ) · nS wS + k3,mCS . (54) the motor temperature, and the operating state of the auxiliary
supply and the fans are monitored. The data of the power
consumption, the boxed volume, and the weight are acquired
from the implemented hardware prototypes [7], [35], [36] with
H. Protection Concepts and Semiconductor Requirements
a TMS320F2808 DSP (Texas Instruments), a MachXO FPGA
All converters should enable a controlled emergency stop of (Lattice), and magnetoresistive current sensors (CDS4000-
the drive, even in case of mains phase loss. In order to meet this series, Sensitec) and are compiled in Table IX.
Fig. 24. Three-dimensional conceptual drawing of an IMC, showing the

components modeled and the layout considered. Fig. 25. Volume of the passive components (without heat sink) Vpas versus
the switching frequency fsw of the MC (CMC/IMC) and V-BBC for different
filter designs (cf., Section IV). The gray shaded area indicates the switching
B. Auxiliary Supply frequency range considered from fsw = 8–32 kHz.
An isolated auxiliary supply with a wide input voltage range

(e.g., 200–900 V) is considered to provide the voltage for the
fans of the cooling system, the gate drivers, and the control
board. The required input power can be calculated by
1
Paux = (PCS + Pdrv,tot + Pctrl ) (55)
ηaux
and is supplied via a three-phase diode rectifier that is con-
nected to the DM capacitors CDM,1 = CF of the input filter.
The key data can be found in Table IX.
VII. C OMPARATIVE E VALUATION

In this section, the results of the comparative evaluation
of the CMC, IMC, and V-BBC for a 15-kVA drive system Fig. 26. Required total semiconductor chip area Achip,tot of the CMC, IMC,
with a PMSM for switching frequencies of 8 and 32 kHz are and V-BBC for TJ,max ≤ 140 ◦ C, ΔTJ,nom ≤ 10 K, TS = 95 ◦ C, and
introduced by applying the models, the design equations, and fsw = {8, 32 kHz}.
the optimization concepts derived in the previous sections. The
results of this comparison are used subsequently to provide the total volume of the passive components, and thus, the DM
a comprehensive and unbiased evaluation of the three con- filter capacitors of the MC can be designed according to the
verter concepts for low-voltage and low-power applications voltage ripple criterion to reduce the reactive power.
(≤ 100 kW), which is supported by various experimental results In conclusion, the boxed volume of the passive components
[18], [35], [37]. Fig. 24 shows, as an example, the construction with or without the cooling system of the MC (CMC or IMC) is
considered and the components modeled for an IMC. approximately ten times smaller at fsw = 8 kHz and approx-
imately 3.5 times smaller at fsw = 32 kHz compared to the
V-BBC. It is important to note that increasing the switching
A. Volume of Passive Components
frequency for the MC leads to a reduction of the filter volume
In a first step, the boxed volumes of the passive components only up to fsw ≈ 23 kHz, which occurs mainly as a result of
for the MC and the V-BBC are compared in Fig. 25 as a the limitation of the maximum DM capacitance per phase
function of the switching frequency for the passive compo- of CDM,max = 45 μF. Contrary to the MC, the total volume
nent introduced and EMI input filter design guidelines from of the passive components of the V-BBC steadily decreases
Section IV to meet the CE noise levels for CISPR 11 class B. for increasing switching frequencies over the whole switching
Two options are shown for both converter concepts. The input frequency range considered as the total volume is mainly dom-
filter of the MC is designed by using the maximum amount of inated by the volume of the boost inductors, which scales with
DM capacitance CDM,2 = CF = CDM,max /2 (cf., gray shaded the inverse of the switching frequency due to the applied current
area in Fig. 14) or just the amount required by the voltage ripple ripple criterion.
criterion to minimize the reactive current drawn by the filter
with CDM,2 = CF ≤ CDM,max /2 (cf., hatched area in Fig. 14).
B. Semiconductor Chip Area
Correspondingly, the input filter for the V-BBC is calculated
with and without restricting the boost inductance to a mini- Fig. 26 shows the required semiconductor chip area, split into
mum value LB,min . Within the switching frequency range of the chip area used for the main power circuit and protection,
8 to 32 kHz, the two design methods considered hardly affect such that the maximum junction temperature does not exceed
Fig. 27. Achievable efficiency considering only the semiconductor losses Fig. 28. Total converter efficiency versus switching frequency for TJ,max ≤
ηsemi versus the chip area per output power α evaluated for TJ,max = 140 ◦ C, ΔTJ,nom ≤ 10 K, and TS = 95 ◦ C. The required chip areas without
115 ◦ C−150 ◦ C, TS = 95 ◦ C, and fsw = {8, 32 kHz}. protection hardware are shown at fsw = {10, 20, 30, 40 kHz}.
TABLE X
TJ,max ≤ 140 ◦ C and the maximum cyclic junction temperature T OTAL E FFICIENCIES FOR N OMINAL M OTOR O PERATION (OP1) AT
variation is limited to ΔTJ,max ≤ 10 K for both nominal motor TJ,max ≤ 140 ◦ C, ΔTJ,max ≤ 10 K, AND TS = 95 ◦ C
operation (OP1) and nominal generator operation (OP5) at
fsw = 8 kHz and fsw = 32 kHz (cf., considerations regarding
the semiconductor lifetime in Section V). The CMC as well as
the IMC requires a total Si chip area of Achip,tot = 11−15 cm2
for fsw = 8−32 kHz, whereby the CMC uses typically 15%
more chip area compared to the IMC. On the contrary to
the MCs, the V-BBC requires a total Si chip area of only is evaluated as a function of the switching frequency. The
Achip,tot = 7 cm2 at 8 kHz but Achip,tot = 15 cm2 at fsw = semiconductor chip areas are again designed such that the
32 kHz similar to the MCs. In consequence, at low switching maximum junction temperature is limited to TJ,max ≤ 140 ◦ C
frequencies, the V-BBC is the most advantageous topology with and/or the maximum junction temperature variation at f2,nom is
regard to the semiconductor expenditure and, in general, has the limited to ΔTJ,max ≤ 10 K for both nominal motor operation
best ratio of the installed chip area in the power circuit with (OP1) and generator operation (OP5). The calculated efficiency
respect to the chip area required for the protection circuitry, curves are shown in Fig. 28, and the resultant efficiency values
followed by the IMC and the CMC. evaluated at fsw = 8 kHz and fsw = 32 kHz are summarized in
Table X.
C. Efficiency Versus Chip Area per Output Power At fsw = 8 kHz, the IMC as well as the V-BBC al-
lows for approximately the same total efficiency ηtot,CMC ≈
The dependence of the resulting efficiency, considering only ηtot,V−BBC ≈ 97%. The achievable efficiency with the CMC is
the semiconductor losses on the chip area per output power α, higher compared to the IMC or V-BBC within the considered
is shown in Fig. 27, evaluated at a sink temperature beneath switching frequency range; at fsw = 8 kHz, the CMC reaches
the power module of TS = 95 ◦ C and switching frequencies 97.8% compared with 97.0% of the IMC and 96.7% of the
of fsw = 8 kHz and fsw = 32 kHz when the maximum junc- V-BBC, and at fsw = 32 kHz, the CMC reaches 97.0% com-
tion temperature is varied between TJ,max = 115 ◦ C−150 ◦ C. pared with 95.8% of the IMC and 92.9% of the V-BBC. The
TJ,max is controlled by changing the chip areas of the individual lower efficiency of the IMC compared to the CMC mainly re-
semiconductors without restricting ΔTJ,max . sults from its higher conduction losses as, in the IMC topology,
Two key results can be extracted: the V-BBC enables the always three semiconductor devices are in the current paths
lowest chip area per output power α at fsw = 8 kHz and is between the input and output terminals compared to only two
comparable to the CMC at fsw = 32 kHz. Both the IMC and the in the CMC topology.
V-BBC (topologies with two-level voltage source input and/or The higher efficiency of the CMC and IMC compared to
output stage) show a decrease in the efficiency at fsw = 32 kHz the V-BBC (particularly at higher switching frequencies) is
when the junction temperature is reduced, and thus, the chip enabled by the lower commutation voltage of the MCs, which
area is increased. This is due to the fact that the reduction in is approximately two thirds of the commutation voltage of the
conduction losses is overcompensated by the contribution of the V-BBC for the selected dc-link voltage of UDC = 700 V, and
capacitive switching losses due to the large chip area. the ZCS strategy of the input stage of the IMC. The efficiency of
the V-BBC for switching frequencies below 10 kHz is limited
primarily by the copper losses of the boost inductors. Thus, by
D. Total Efficiency Versus Switching Frequency
using boost inductors with a lower rms current density value
Next, the total efficiency, including the losses of the semicon- than 6 A/mm2 , the V-BBC can reach almost the same efficiency
ductors, all passive components, the fans, the gate drivers, the as the CMC at 4 kHz and a higher efficiency than the IMC
control and measurement hardware, and the auxiliary supply, below 10 kHz.
Fig. 29. Normalized output current versus electrical output frequency such Fig. 31. Total converter efficiency for nominal motor operation (OP1) ηnom
that TJ,max = 140 ◦ C and TS = 95 ◦ C ⇒ ΔTJ,max ≤ 45 K, and fsw = versus power density ρ for TJ,max ≤ 140 ◦ C, ΔTJ,nom ≤ 10 K, TS =
8 kHz. The considered chip areas can be found in Fig. 26. 95 ◦ C, and fsw = 4−46 kHz.
and thus, the output current has to be decreased to maintain

the specified thermal constraints. The IMC and V-BBC feature
a similar derating of the output current for fsw = 8 kHz and
fsw = 32 kHz when the output frequency is decreased to zero
as both topologies have the same output stage topology and gen-
erate conduction and switching losses in the output stage (for
the selected discontinuous modulation schemes, cf., Section II
and [6]). The maximum available output current of the IMC
and V-BBC slightly exceeds the nominal output current above
30 Hz, while the thermal constraints of the semiconductors are
still fulfilled. This is due to the variation of the modulation
index which leads to a different loading of the transistors and
Fig. 30. Normalized output current versus the electrical output frequency diodes compared to OP1 and OP5 and the margin of the peak
such that TJ,max = 140 ◦ C, TS = 95 ◦ C ⇒ ΔTJ,max ≤ 45 K, and fsw = junction temperature to TJ,max = 140 ◦ C (cf., Fig. 18) and thus
32 kHz. The considered chip areas can be found in Fig. 26.
allows for an output current above the nominal current level
(cf., Figs. 29 and 30).
E. Output Current Versus Output Frequency The semiconductor losses of the CMC are modulated with
the input frequency f1 and the output frequency f2 , and the
The available output current I2 for a given output frequency phase angle between the input and output currents due to the
f2 under the specified thermal constraints of the junction tem- missing dc-link. Thus, the CMC shows a significantly different
perature is of particular importance for the characterization of derating curve compared to the IMC and V-BBC, with dips
ac-ac converters for drive applications. The normalized maxi- in the available output current at 50 and 100 Hz. If f1 ≈ f2 ,
mum output current for that purpose the loading of the individual semiconductors is modulated with
I2,max |f1 | − |f2 | ≈ 0 (beating effect). The most critical operating
I2,max,n = (56) points (OP2/OP4) occur at f2 = ±f1 , which may be considered
I2,nom
as equivalent to the electrical standstill condition of a V-BBC
which is proportional to the motor torque, is shown in Figs. 29 for the semiconductor losses of the CMC. In particular, for drive
and 30 versus the output frequency for fsw = 8 kHz and fsw = systems that are mainly operated at f2 ≈ f1 , a careful thermal
32 kHz such that TJ,max ≤ 140 ◦ C and TS = 95 ◦ C. This means design of the semiconductors is mandatory in order not to limit
that the peak-to-peak junction temperature variation due to the semiconductor lifetime of the CMC. The CMC can provide
the modulation of the semiconductor losses with the electrical the highest available output current (torque) particularly at f2 =
input and/or output frequency is limited to ΔTJ,max ≤ 45 K. 0 Hz (OP3) as the semiconductor losses are modulated with
The semiconductor chip areas are again designed as previously |f1 | − |f2 | = f1 , and thus, it prevents a strong loading of single
specified and visualized in Fig. 26 for nominal operation at semiconductors compared with the output stage of the IMC and
f2,nom = ±140 Hz. V-BBC but requires also the largest semiconductor chip area for
The modulation index of the converter system is reduced in the switching frequency range of interest from 8 to 32 kHz.
proportion to the output frequency for the PMSM load being
considered from 90% at 140 Hz to 2% at standstill. When
F. Efficiency, Power Density, and Power-to-Mass Ratio
the output frequency is lowered, the modulation frequency
of the semiconductor losses is also decreased (or changes), In Figs. 31–33, the tradeoff between the total efficiency at
whereas the thermal time constant of the semiconductor chips nominal motor operation (OP1) ηnom , the achievable power
remains obviously invariant. This leads to a higher ΔTJ,max , density ρ, and the resultant power-to-mass ratio γ are shown
Fig. 32. Total converter efficiency for nominal motor operation (OP1)
ηnom versus power-to-mass ratio γ for TJ,max ≤ 140 ◦ C, ΔTJ,nom ≤ 10 K,
TS = 95 ◦ C, and fsw = 4−46 kHz.
Fig. 34. Comparison of the CMC, IMC, and V-BBC with performance
indicators for TJ,max ≤ 140 ◦ C, ΔTJ,max ≤ 10 K, TS = 95 ◦ C, and fsw =
8 kHz.
Fig. 33. Power-to-mass ratio γ versus power density ρ for TJ,max ≤ 140 ◦ C,
ΔTJ,nom ≤ 10 K, TS = 95 ◦ C, and fsw = 4−46 kHz, indicating all optima
as a function of the switching frequency.
for the considered design guidelines. The switching frequency

range is within 4 and 46 kHz.
The CMC and IMC enable a 2.5 times higher maximum
power density at a nominal efficiency of 97.6% at fsw ≈ 16 kHz
for the CMC and 96.3% at fsw ≈ 23 kHz for the IMC compared
to 90.9% at fsw = 39 kHz for the V-BBC. The achievable
power density decreases for the CMC and IMC for lower
switching frequencies, as shown in Fig. 31. This occurs mainly
due to the limitation of CDM,max , which leads to a relative
increase of the input filter volume compared to the required
attenuation as a larger amount of DM inductance with a higher
volumetric scaling than that for the DM capacitors (cf., Figs. 5
and 7) is required. A similar result is obtained when comparing
the maximum power-to-mass ratio in Fig. 32, which is five
times higher for the CMC and IMC than that for the V-BBC at Fig. 35. Comparison of the CMC, IMC, and V-BBC with performance
a difference of the nominal efficiency of approximately 97.8% indicators for TJ,max ≤ 140 ◦ C, ΔTJ,max ≤ 10 K, TS = 95 ◦ C, and fsw =
32 kHz.
for the CMC and 97.2% for the IMC compared to 90.4% for the
V-BBC. The optimal power-to-mass ratio for the MCs occurs at
performance indicators for a switching frequency of 8 and
low switching frequencies, whereas for the V-BBC, it is found
32 kHz. The following measures are defined for that purpose.
at fsw = 41 kHz as a result of the reduction in boost inductance
1) Voltage Transfer Ratio:
with increasing switching frequency and, therewith, a reduction
of the mass of the inductors. U2,max
MU,12 = . (57)
U1
G. Overview of Performance Indicators
The dc-link voltage of the V-BBC is assumed with UDC =
Finally, the resultant main properties of the CMC, IMC, and 700 V. U1 and U2 denote the rms value of the input and output
V-BBC are shown in Figs. 34 and 35 with nine characteristic line voltages.
2) Nominal Efficiency at OP1: the power module), leading to a limitation of the maximum
junction temperature variation of ΔTJ,max = 45 K.
P2,nom The performance spaces where the MC is superior to the
ηnom = (58)
P2,nom + Ploss,nom V-BBC technology and vice versa are highlighted with the
corresponding colors in the aforementioned diagrams. The area
at a modulation index for the MCs of M12 = 0.9 and a
spanned by the polygon curves can be considered as a relative
modulation
√ index for the output stage of the V-BBC of measure for comparison. The better the converter performance
M2 = U2 6/UDC = 0.9.
is, the larger is the area.
3) Efficiency at 25% of the Nominal Output Power for Motor
Operation:
P2,25 1 VIII. C ONCLUSION

η25 = I2,25 = · I2,nom (59)
P2,25 + Ploss,25 2 A. Main Results
at half of the nominal output current I2,25 , a modulation index In this paper, a systematic methodology and the main compo-
for the MCs of M12 = 0.45, and a modulation index for the nent models required for a holistic comparison of three-phase
output stage of the V-BBC of M2 = 0.45. ac-ac converter systems have been presented and applied to
4) Power Density: perform a comparative evaluation of CMC, IMC, and V-BBC
for a 15-kW PMSM drive.
P2,nom All three converter systems are designed to operate on a
ρ= . (60)
Vtot balanced three-phase 50-Hz mains system with a nominal line-
to-line voltage of 3 × 400 V (rms) and to meet the CISPR
Vtot accounts for the total boxed volume of the passive 11 (class B) EMC standard for CE and are investigated for
components, the cooling system, the semiconductor module, a switching frequency range of 4–46 kHz. The converters are
the gate drivers, the control and measurement hardware, and controlled to provide sinusoidal input currents and unity power
the auxiliary supply (cf., Fig. 24). factor at the input. The dc-link voltage UDC of the V-BBC is
5) Power-to-Mass Ratio: assumed to be 700 V. In order to enable a fair comparison,
P2,nom the rated voltages of the PMSMs are matched to the respective
γ= . (61) output voltage ranges of the MC and V-BBC such that, at
mtot
90% of the maximum output voltage of the converter and at
mtot is equal to the total mass of the passive components, the equal electrical nominal output frequency of 140 Hz, all motors
cooling system, the semiconductor module, the gate drivers, the deliver the same mechanical shaft power (i.e., 14.4 kW ≈
control and measurement hardware, and the auxiliary supply. 20 hp). Si Trench and Field-Stop IGBT4 devices (1200 V)
6) Reactive Input Power Compensation Capability at Zero and EmCon4 diodes (Infineon) are utilized. The semiconductor
Apparent Output Power: chip areas are designed such that, at nominal motor/generator
operation, the maximum cyclic junction temperature variation
S1 is limited to 10 K and the maximum junction temperature does
Λ1,0 = . (62)
P2,nom S2 =0 not exceed 140 ◦ C.
Within the considered switching frequency range of
S1 and S2 refer to the apparent input and output powers of the 4–46 kHz, the MC topologies enable a 2.5 times higher max-
converter. imum power density and a five times higher maximum power-
7) Nominal Output Power per Si Chip Area: to-mass ratio at a higher efficiency of 97.6% at 16 kHz for the
CMC and 96.3% at 23 kHz for the IMC compared to the V-BBC
P2,nom
. (63) that allows for an efficiency of 90.9% at the point of maximum
Achip,tot power density at 39 kHz (cf., Fig. 31) and an efficiency of
8) Maximum Output Current When the Output Frequency Is 90.4% at the point of maximum power-to-mass ratio at 41 kHz
Equal to the Input Frequency: (cf., Fig. 32). At 4 kHz, the IMC and V-BBC feature a simi-
lar nominal efficiency of approximately 97%, whereby below

I2,max 10 kHz, the efficiency of the V-BBC is mainly determined
I2,max,f1 ,n = . (64)
I2,nom f2 =f1 by the copper losses of the boost inductors, which could
be reduced. The CMC allows for the highest efficiency in
9) Maximum Output Current When the Output Frequency Is the considered switching frequency range. The V-BBC re-
Equal to Zero: quires a significantly smaller semiconductor chip area com-
pared to the CMC and IMC for switching frequencies below
I2,max 30 kHz, e.g., at 8 kHz, only 7 cm2 compared to 12 cm2
I2,max,0,n = (65)
I2,nom f2 =0 for the CMC and 11 cm2 for the IMC under the considered
thermal constraints, whereas above 30 kHz, the V-BBC re-
such that the maximum junction temperature does not exceed quires the largest total chip area, followed by the CMC and
TJ,max = 140 ◦ C at a sink temperature TS = 95 ◦ C (beneath the IMC.
Unfortunately, the higher achievable power density and plication area. The high mains frequency and the capacitive
power-to-mass ratio of MCs compared to the V-BBC within input filter result in a high reactive input power, which can
the considered switching frequency range is outweighed by only be compensated within limits and typically at the expense
the lack of desirable basic converter properties such as output of a reduction of the available output voltage. In addition,
voltage step-up capability, unconstrained reactive input power simple feedback control of the input currents independent of
compensation, simple feedback control of the input currents in- the load currents as with the V-BBC is not possible with
dependent of the output currents, and the possibility for single- the MC. A voltage-source-based converter system from this
phase operation. Consequently, the MC is not the appropriate perspective, possibly with a three-level PFC input stage, is a
topology for a general-purpose, flexibly configurable, bidirec- more appropriate solution for an aircraft drive system [38], [39].
tional, low-voltage, and low-power ac-ac converter system. The This finding is confirmed by the investigation performed in
V-BBC clearly is the preferred choice for such requirements. [5], where different converter topologies have been analyzed
regarding their suitability for a lightweight aircraft ac-dc-ac
B. Application Areas of MCs converter system.
Suitable application areas for the MC technology for low-

voltage and low-power (≤ 100 kW) systems can be identified C. CMC Versus IMC
by analyzing the performance indicators shown in Figs. 34 Most of the properties of the CMC and IMC are identical or
and 35. The MC represents a converter concept that aims at can at least be achieved by adequate modulation and control.
minimizing the internal energy storage. This key converter The major difference is found in the three-phase symmetry of
system property should be considered as an assessment criteria the power circuit of the CMC compared to the IMC, which
on whether the MC well matches its intended application. inherently leads to an equal average loading of all semiconduc-
This means that, for ac-ac converter applications that require tors of the CMC and thus allows for a lower semiconductor
internal energy storage due to high load dynamics, single- area in the power circuit (without the power semiconductors
phase operation capability, extended ride-through capability, required for protection) than for the IMC. It can hence be stated
or unconstrained reactive power compensation, the MC is not that the simple commutation of the IMC due to its two-stage
the appropriate converter concept. In addition, there should structure is achieved at the expense of more power devices in
be a certain degree of freedom on the system design level to the current path, which results in a higher semiconductor effort
adapt the overall drive system to the MC, i.e., the nominal and typically a lower achievable efficiency compared with
voltage of the motor, in order to fully exploit its benefits without the CMC.
restricting the performance of the drive due to the limited A sort of electrical standstill condition for the CMC occurs
voltage transfer ratio of 86.6% for sinusoidal modulation. when the output frequency is equal to the input frequency
Ideal loads for MCs require low dynamic performance and f2 = ±f1 (OP2/OP4; cf., Fig. 17) or to a multiple of the
are mainly operated between 30% and 100% of their rated input frequency, and thus, only a few devices conduct the load
power level. This enables the reactive currents drawn by the current for a comparatively long time. The available output
filter to be compensated at a limited reduction of the available current has to be reduced for this operating condition for a
nominal output voltage (≤ 10%) and/or to maintain unity power given maximum junction temperature variation ΔTJ,max , or a
factor cos Φ1 ≈ 1 [cf., (28)] over the whole load (mission) larger semiconductor chip area has to be provided (cf., Figs. 29
profile of the drive. The MC enables, particularly at higher and 30). However, compared with the worst case of the IMC,
switching frequencies, better performance than the V-BBC as which occurs at f2 = 0, the operating conditions at f2 = ±f1
can be immediately seen by comparing Figs. 34 and 35 and for the CMC are less severe as the conduction intervals of the
requires, e.g., at 32 kHz, approximately the same semicon- more heavily loaded power devices are still cyclically changing
ductor chip area as the V-BBC. Suitable application areas for with the input/output frequency.
the MC technology based on the aforementioned performance In view of the dependence between the available output
indicators are therefore the following: current and the output frequency, the CMC should be selected
1) compressors (e.g., for air conditioners and vacuum for applications with a mission profile that mainly requires
dryers); operation at low output frequencies (<10 Hz), ideally with a
2) fans (blowers); maximum output frequency of 85% of the input frequency.
3) mixers; Correspondingly, the IMC should be applied for drives that are
4) general pumps or heat pumps; operated above 10 Hz. The efficiency of the IMC at part load
5) escalator drive systems for modulation indices below typically M12 = 0.5 is higher
for 50/60-Hz mains application, where a switching frequency compared to the CMC as the output stage is then comparatively
above the audible range (>20 kHz) is desirable. long in the freewheeling state which reduces the conduction
Although MCs are often suggested as an alternative topology interval and the losses of the input stage.
to the V-BBC for more electric aircraft applications with a The IMC should be considered for part load operation or
variable frequency mains system (360–800 Hz), despite its high switching frequency applications when advanced (more
unquestionable advantage of a high power density and power- expensive) semiconductor devices are indispensable. Such a
to-mass ratio, the properties of the MCs do not provide an high-performance IMC could be built with Si IGBT and diodes
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Thomas Friedli (M’09) received the M.Sc. degree Jose Rodriguez (M’81–SM’94–F’10) received the
in electrical engineering and information technology Engineer degree in electrical engineering from
(with distinction) and the Ph.D. degree from the the Universidad Federico Santa Maria (UTFSM),
Swiss Federal Institute of Technology (ETH) Zurich, Valparaiso, Chile, in 1977 and the Dr.-Ing. degree
Zurich, Switzerland, in 2005 and 2010, respectively. in electrical engineering from the University of
From 2003 to 2004, he worked as a Trainee Erlangen, Erlangen, Germany, in 1985.
with the R&D Center for Telecom Power Supplies, He has been with the Department of Electronics
Power-One. His Ph.D. research from 2006 to 2009 Engineering, University Federico Santa Maria, since
involved further development of current source and 1977, where he is currently a Full Professor and the
matrix converter topologies in collaboration with Rector. He has coauthored more than 250 journal
industry using silicon carbide JFETs and diodes and and conference papers. His main research interests
a comparative evaluation of three-phase ac-ac converter systems. include multilevel inverters, new converter topologies, control of power con-
Dr. Friedli received the 1st Prize Paper Award of the IEEE IAS IPCC in 2008 verters, and adjustable-speed drives.
and the IEEE T RANSACTIONS ON I NDUSTRY A PPLICATIONS Prize Paper Dr. Rodriguez is a member of the Chilean Academy of Engineering. He
Award in 2009. received the Best Paper Award from the IEEE T RANSACTIONS ON I NDUS -
TRIAL E LECTRONICS in 2007 and the Best Paper Award from the IEEE
I NDUSTRIAL E LECTRONICS M AGAZINE in 2008. He has been an Associate
Johann W. Kolar (M’89–SM’04–F’10) received Editor of the IEEE T RANSACTION ON P OWER E LECTRONICS and the IEEE
the M.Sc. and Ph.D. degrees (summa cum laude/ T RANSACTIONS ON I NDUSTRIAL E LECTRONICS since 2002.
promotio sub auspiciis praesidentis rei publicae)
from the University of Technology Vienna, Vienna,
Austria. Patrick W. Wheeler (M’00) received the B.Eng.
Since 1984, he has been working as an Indepen- degree (Hons) and the Ph.D. degree in electrical
dent International Consultant in close collaboration engineering for his work on matrix converters from
with the University of Technology Vienna in the the University of Bristol, Bristol, U.K., in 1990 and
fields of power electronics, industrial electronics, and 1994, respectively.
high-performance drives. He has proposed numerous In 1993, he was a Research Assistant with the De-
novel PWM converter topologies and modulation partment of Electrical and Electronic Engineering,
and control concepts, e.g., the V IENNA rectifier, the S WISS rectifier, and the University of Nottingham, Nottingham, U.K., where
three-phase ac-ac sparse matrix converter. On February 1, 2001, he was ap- he became a Lecturer with the Power Electronics,
pointed as a Professor and the Head of the Power Electronics Systems Labora- Machines and Control Group in 1996. Since January
tory, Swiss Federal Institute of Technology (ETH) Zurich, Zurich, Switzerland, 2008, he has been a Full Professor in the same
which was awarded as the leading academic research institution in power elec- research group. He has published over 250 papers in leading international
tronics in Europe by the European Power Supplies Manufacturers Association conferences and journals. His research interests are in power conversion,
(EPSMA) in 2006. He initiated and/or is the founder/cofounder of four spin- energy, and more electric aircraft technology.
off companies targeting ultrahigh-speed drives, multidomain/level simulation,
ultracompact/efficient converter systems, and pulsed power/electronic energy
processing. He has published over 400 scientific papers in international journals
and conference proceedings and has filed more than 80 patents. The focus of
his current research is on ac-ac and ac-dc converter topologies with low effects
on the mains, e.g., for power supply of data centers, more electric aircraft,
and distributed renewable energy systems. Further main areas of research are
the realization of ultracompact and ultraefficient converter modules employ-
ing latest power semiconductor technology (SiC and GaN), novel concepts
for cooling and EMI filtering, multidomain/scale modeling/simulation and
multiobjective optimization, physical-model-based lifetime prediction, pulsed
power, and ultrahigh-speed and bearingless motors.
Dr. Kolar is a member of the Institute of Electrical Engineers of Japan
and international steering committees and technical program committees of
numerous international conferences in the field (e.g., Director of the Power
Quality Branch of the International Conference on Power Conversion and
Intelligent Motion). He is the Founding Chairman of the IEEE PELS Austria
and Switzerland Chapter and Chairman of the Education Chapter of the EPE
Association. He received the Best Paper Award of the IEEE T RANSACTIONS
ON I NDUSTRIAL E LECTRONICS in 2005, the Best Paper Award of the ICPE
in 2007, the 1st Prize Paper Award of the IEEE IAS IPCC in 2008, the
IEEE IECON Best Paper Award of the IES PETC in 2009, the 2009 IEEE
T RANSACTIONS ON P OWER E LECTRONICS Prize Paper Award, and the 2010
Best Paper Award of the IEEE/ASME T RANSACTIONS ON M ECHATRONICS.
He also received an Erskine Fellowship from the University of Canterbury,
Christchurch, New Zealand, in 2003. From 1997 to 2000, he was an Associate
Editor of the IEEE T RANSACTIONS ON I NDUSTRIAL E LECTRONICS, and
since 2001, he has been an Associate Editor of the IEEE T RANSACTIONS ON
P OWER E LECTRONICS. Since 2002, he has also been an Associate Editor of
the Journal of Power Electronics of the Korean Institute of Power Electronics
and a member of the Editorial Advisory Board of the IEEJ Transactions on
Electrical and Electronic Engineering.

2012 Comparative Evaluation of MC and Voltage DC-Link Back-To-Back Converter Systems

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IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 59, NO.

12, DECEMBER 2012 4487

Comparative Evaluation of Three-Phase AC–AC

0278-0046/$26.00 © 2011 IEEE

Fig. 2. Characteristic waveforms of the CMC for Φ1 ≈ 0 and Φ2 = π/9

V-BBC is performed. Finally, in Section VIII, a compilation

II. K EY C ONVERTER P ROPERTIES

the switching sequence of the output stage is repeated for two

active damping. Assuming a proper design, the reactive power TABLE I

TABLE II 2) EMI Suppression Capacitors: In this comparison, X2

VCX2 |UX2 = k1,V,CX2 · CX2 + k2,V,CX2 . (8)

The resulting losses of polypropylene X2 EMI suppression

Fig. 7. Resulting boxed volume of the designed DM inductors using High

magnetization properties. In order to minimize the parasitic

mLDM |IL ≈ k1,m,LDM · LDM + k2,m,LDM (18)

for a given inductor current IL .

If not specified otherwise, the wire temperature is assumed as

Finally, the leakage inductance can be approximated by TABLE VI

The relationship between the boxed volume of the CM induc-

mLCM |ILDM ≈ k1,m,LCM · |Z CM | + k2,m,LCM (25)

C. Filter Design Procedure

on practical experience. In order to enable safe operation, in

The switching frequency fsw in the aforementioned equation

Attention has to be paid to converter stability when reducing

Next, the impedance of LCM,1 is calculated to meet the CM

leading to a good compromise between damping performance D. DC-Link Capacitor

Fig. 15. Volume of the passive components of the MC Vpas,MC versus

their performance and the variety of available devices and

B. Design-Relevant Operating Points

at standstill torque MM,0 . At this operating point, it

C. Required Semiconductor Chip Area

current-, chip-area-, and temperature-dependent semiconductor

pS/D,cond = US/D,F (AS/D,chip,act , TJ ) · iS/D

where iS/D denotes the instantaneous transistor or diode

pS/D,sw = fsw · wS/D,tot (AS/D,chip,act , iS/D , uS/D , TJ ).

given gate charge QG , the losses generated in the gate resistor

Achip,SM G. Cooling System

TABLE VIII TABLE IX

requirement, the V-BBC has to be implemented with a brake

Fig. 24. Three-dimensional conceptual drawing of an IMC, showing the

An isolated auxiliary supply with a wide input voltage range

VII. C OMPARATIVE E VALUATION

and thus, the output current has to be decreased to maintain

for the considered design guidelines. The switching frequency

P2,25 1 VIII. C ONCLUSION

Suitable application areas for the MC technology for low-

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