UNIT I THE 8086 MICROPROCESSOR

A microprocessor is a computer processor that incorporates the functions of a

computer's central processing unit (CPU) on a single integrated circuit (IC)

8085 Microprocessor:
8085 is pronounced as "eighty-eighty-five" microprocessor. It is an 8-bit microprocessor
designed by Intel in 1977 using NMOS technology.
It has the following configuration −
 8-bit data bus
 16-bit address bus, which can address upto 64KB
 A 16-bit program counter
 A 16-bit stack pointer
 Six 8-bit registers arranged in pairs: BC, DE, HL
 Requires +5V supply to operate at 3.2 MHZ single phase clock
It is used in washing machines, microwave ovens, mobile phones, etc.

8085 consists of the following functional units −

Accumulator
It is an 8-bit register used to perform arithmetic, logical, I/O & LOAD/STORE operations. It
is connected to internal data bus & ALU.
Arithmetic and logic unit
As the name suggests, it performs arithmetic and logical operations like Addition,
Subtraction, AND, OR, etc. on 8-bit data.
General purpose register
There are 6 general purpose registers in 8085 processor, i.e. B, C, D, E, H & L. Each register
can hold 8-bit data.
These registers can work in pair to hold 16-bit data and their pairing combination is like B-
C, D-E & H-L.
Program counter
It is a 16-bit register used to store the memory address location of the next instruction to be
executed. Microprocessor increments the program whenever an instruction is being
executed, so that the program counter points to the memory address of the next instruction
that is going to be executed.
Stack pointer
It is also a 16-bit register works like stack, which is always incremented/decremented by 2
during push & pop operations.
Temporary register
It is an 8-bit register, which holds the temporary data of arithmetic and logical operations.
Flag register
It is an 8-bit register having five 1-bit flip-flops, which holds either 0 or 1 depending upon
the result stored in the accumulator.
These are the set of 5 flip-flops −
 Sign (S)
 Zero (Z)
 Auxiliary Carry (AC)
 Parity (P)
 Carry (C)
Its bit position is shown in the following table −
D7 D6 D5 D4 D3 D2 D1 D0

S Z AC P CY
Sign Flag (S) – After any operation if the MSB (B(7)) of the result is 1, it in indicates the
number is negative and the sign flag becomes set, i.e. 1. If the MSB is 0, it indicates the
number is positive and the sign flag becomes reset i.e. 0.
Zero Flag (Z) – After any arithmetical or logical operation if the result is 0 (00)H, the zero
flag becomes set i.e. 1, otherwise it becomes reset i.e. 0.
Auxiliary Cary Flag (AC) – This flag is used in BCD number system(0-9). If after any
arithmetic or logical operation D(3) generates any carry and passes on to B(4) this flag
becomes set i.e. 1, otherwise it becomes reset i.e. 0.
Parity Flag (P) – If after any arithmetic or logical operation the result has even parity, an
even number of 1 bits, the parity register becomes set i.e. 1, otherwise it becomes reset i.e. 0.
Carry Flag (CY) – Carry is generated when performing n bit operations and the result is
more than n bits, then this flag becomes set i.e. 1, otherwise it becomes reset i.e. 0.

Instruction register and decoder

It is an 8-bit register. When an instruction is fetched from memory then it is stored in the
Instruction register. Instruction decoder decodes the information present in the Instruction
register.
Timing and control unit
It provides timing and control signal to the microprocessor to perform operations. Following
are the timing and control signals, which control external and internal circuits −
 Control Signals: READY, RD’, WR’, ALE
 Status Signals: S0, S1, IO/M’
 DMA Signals: HOLD, HLDA
 RESET Signals: RESET IN, RESET OUT
Interrupt control
As the name suggests it controls the interrupts during a process. When a microprocessor is
executing a main program and whenever an interrupt occurs, the microprocessor shifts the
control from the main program to process the incoming request. After the request is
completed, the control goes back to the main program.
There are 5 interrupt signals in 8085 microprocessor: INTR, RST 7.5, RST 6.5, RST 5.5,
TRAP.
Serial Input/output control
It controls the serial data communication by using these two instructions: SID (Serial input
data) and SOD (Serial output data).
Address buffer and address-data buffer
The content stored in the stack pointer and program counter is loaded into the address buffer
and address-data buffer to communicate with the CPU. The memory and I/O chips are
connected to these buses; the CPU can exchange the desired data with the memory and I/O
chips.
Address bus and data bus
Data bus carries the data to be stored. It is bidirectional, whereas address bus carries the
location to where it should be stored and it is unidirectional. It is used to transfer the data &
Address I/O devices.
8085 Architecture
8086 MICROPROCESSOR-INTRODUCTION
 INTEL launched 8086 in 1978
 8086 is a 16-bit microprocessor with 16-bit Data Bus {D0-D15}
 It has 20-bit Address Bus {A0-A19} [can access up to 2^20= 1 MB memory
locations].
 It has multiplexed address and data bus AD0-AD15 and A16–A19.
 It can support up to 64K I/O ports It provides 14, 16-bit registers.
 8086 requires one phase clock with a 33% duty cycle to provide optimized internal
timing. – Range of clock:
 5 MHz for 8086
 8 MHz for 8086-2
 10 MHz for 8086-1

BLOCK DIAGRAM OF8086

The 8086 CPU is divided into two independent functional units:
 Bus Interface Unit (BIU)
 Execution Unit (EU)
Bus Interface Unit (BIU)
The function of BIU is to:
 Fetch the instruction or data from memory.
 Write the data to memory.
 Write the data to the port.
  Read data from the port.
Instruction Queue
1. To increase the execution speed, BIU fetches as many as six instruction bytes ahead
to time from memory.
2. All six bytes are then held in first in first out 6 byte register called instruction queue.
3. Then all bytes have to be given to EU one by one.
4. This pre fetching operation of BIU may be in parallel with execution operation of EU,
which improves the speed execution of the instruction.
Segment Registers
Additional registers called segment registers generate memory address when combined
with other in the microprocessor. In 8086 microprocessor, memory is divided into 4 segments
as follow:
1. Code Segment (CS): The CS register is used for addressing a memory location in the
Code Segment of the memory, where the executable program is stored.
2. Data Segment (DS): The DS contains most data used by program. Data are accessed
in the Data Segment by an offset address or the content of other register that holds the
offset address.
3. Stack Segment (SS): SS defined the area of memory used for the stack.
4. Extra Segment (ES): ES is additional data segment that is used by some of the string
to hold the destination data.
Instruction pointer (IP)
The instruction pointer, also called program counter, is a special register in a
processor. It holds the address of the next instruction to be executed. Control
flow instructions such as jumps, conditional branches, and subroutine calls manipulate the
instruction pointer.
Execution Unit (EU)
The functions of execution unit are:
 To tell BIU where to fetch the instructions or data from.
 To decode the instructions.
 To execute the instructions.
The EU contains the control circuitry to perform various internal operations. A decoder in EU
decodes the instruction fetched memory to generate different internal or external control
signals required to perform the operation. EU has 16-bit ALU, which can perform arithmetic
and logical operations on 8-bit as well as 16-bit.
General Purpose Registers of 8086
These registers can be used as 8-bit registers individually or can be used as 16-bit in pair to
have AX, BX, CX, and DX.
1. AX Register: AX register is also known as accumulator register that stores operands
for arithmetic operation like divided, rotate.
2. BX Register: This register is mainly used as a base register. It holds the starting base
location of a memory region within a data segment.
3. CX Register: It is defined as a counter. It is primarily used in loop instruction to store
loop counter.
4. DX Register: DX register is used to contain I/O port address for I/O instruction.
Flag Registers of 8086
Flag register in EU is of 16-bit

Flags Register determines the current state of the processor. They are modified automatically
by CPU after mathematical operations, this allows to determine the type of the result, and to
determine conditions to transfer control to other parts of the program. 8086 has 9 flags and
they are divided into two categories:
 Carry Flag (CF): This flag indicates an overflow condition for unsigned integer
arithmetic. It is also used in multiple-precision arithmetic.
 Auxiliary Flag (AF): If an operation performed in ALU generates a carry/barrow
from lower nibble (i.e. D0 – D3) to upper nibble (i.e. D4 – D7), the AF flag is set i.e.
 carry given by D3 bit to D4 is AF flag. This is not a general-purpose flag, it is used
internally by the processor to perform Binary to BCD conversion.
 Parity Flag (PF): This flag is used to indicate the parity of result. If lower order 8-
bits of the result contains even number of 1’s, the Parity Flag is set and for odd
number of 1’s, the Parity Flag is reset.
 Zero Flag (ZF): It is set; if the result of arithmetic or logical operation is zero else it
is reset.
 Sign Flag (SF): In sign magnitude format the sign of number is indicated by MSB bit.
If the result of operation is negative, sign flag is set.
 Overflow Flag (OF): It occurs when signed numbers are added or subtracted. An OF
indicates that the result has exceeded the capacity of machine.
 Trap Flag (TP):
a. It is used for single step control.
b. It allows user to execute one instruction of a program at a time for debugging.
 Interrupt Flag (IF):
a. It is an interrupt enable/disable flag.
b. If it is set, the maskable interrupt of 8086 is enabled and if it is reset, the
interrupt is disabled.
 Direction Flag (DF):
a. It is used in string operation.
b. If it is set, string bytes are accessed from higher memory address to lower
memory address.
SI - source index register:
o Can be used for pointer addressing of data
o Used as source in some string processing instructions
o Offset address relative to DS
DI - destination index register:
o Can be used for pointer addressing of data
o Used as destination in some string processing instructions
o Offset address relative to ES
BP - base pointer:
o Primarily used to access parameters passed via the stack
o Offset address relative to SS
SP - stack pointer:
o Always points to top item on the stack
o Offset address relative to SS
o Always points to word (byte at even address)
o An empty stack will had SP = FFFEh
REGISTER ORGANIZATION
a) General Registers
b) Index Registers
c) Segment Registers
d) Pointer Registers
e) Status Register
A register is a very small amount of fast memory that is built in the CPU (or Processor) in
order to speed up the operation. Register is very fast and efficient than the other memories
like RAM, ROM, external memory etc,. That’s why the registers occupied the top position in
memory hierarchy model.
The 8086 microprocessor has a total of fourteen registers that are accessible to the
programmer. All these registers are 16-bit in size. The registers of 8086 are categorized into 5
different groups.
a) General registers
b) Index registers
c) Segment registers
d) Pointer registers
e) Status Register
 d) General Registers
All general registers of the 8086 microprocessor can be used for arithmetic and logic
operations. These all general registers can be used as either 8-bit or 16-bit registers. The
general registers are:
i. AX (Accumulator):
AX is used as 16-bit accumulator. The lower 8-bits of AX are designated to use as AL
and higher 8-bits as AH. AL can be used as an 8-bit accumulator for 8-bit operation.

This Accumulator used in arithmetic, logic and data transfer operations. For manipulation
and division operations, one of the numbers must be placed in AX or AL.
ii. BX (Base Register):
BX is a 16 bit register, but BL indicates the lower 8-bits of BX and BH indicates the
higher 8-bits of BX. The register BX is used as address register to form physical address
in case of certain addressing modes (ex: indexed and register indirect).
iii. CX (Count Register):
The register CX is used default counter in case of string and loop instructions. Count
register can also be used as a counter in string manipulation and shift/rotate instruction.
iv. DX (Data Register):
DX register is a general purpose register which may be used as an implicit operand or
destination in case of a few instructions. Data register can also be used as a port number
in I/O operations.
e) Segment Register:
The 8086 architecture uses the concept of segmented memory. 8086 can able to access a
memory capacity of up to 1 megabyte. This 1 megabyte of memory is divided into 16 logical
segments. Each segment contains 64 Kbytes of memory. This memory segmentation concept
will discuss later in this document.

There are four segment registers to access this 1 megabyte of memory. The segment registers
of 8086 are:
i. CS (Code Segment):
Code segment (CS) is a 16-bit register that is used for addressing memory location in the
code segment of the memory (64Kb), where the executable program is stored. CS register
cannot be changed directly. The CS register is automatically updated during far jump, far
call and far return instructions.
ii. Stack segment (SS)
Stack Segment (SS) is a 16-bit register that used for addressing stack segment of the
memory (64kb) where stack data is stored. SS register can be changed directly using POP
instruction.
iii. Data segment (DS)
Data Segment (DS) is a 16-bit register that points the data segment of the memory (64kb)
where the program data is stored. DS register can be changed directly using POP and LDS
instructions.
iv. Extra segment (ES):
Extra Segment (ES) is a 16-bit register that also points the data segment of the memory
(64kb) where the program data is stored. ES register can be changed directly using POP
and LES instructions.
f) Index Registers
The index registers can be used for arithmetic operations but their use is usually concerned
with the memory addressing modes of the 8086 microprocessor (indexed, base indexed and
relative base indexed addressing modes).
The index registers are particularly useful for string manipulation.
i. SI (Source Index):
SI is a 16-bit register. This register is used to store the offset of source data in data
segment. In other words the Source Index Register is used to point the memory locations
in the data segment.
ii. DI (Destination Index):
DI is a 16-bit register. This is destination index register performs the same function as SI.
There is a class of instructions called string operations that use DI to access the memory
locations in Data or Extra Segment.
g) Pointer Registers:
Pointer Registers contains the offset of data(variables, labels) and instructions from their base
segments (default segments).8086 microprocessor contains three pointer registers.
i. SP (Stack Pointer):
Stack Pointer register points the program stack that means SP stores the base address of
the Stack Segment.
ii. BP (Base Pointer):
Base Pointer register also points the same stack segment. Unlike SP, we can use BP to
access data in the other segments also.
iii. IP (Instruction Pointer):
The Instruction Pointer is a register that holds the address of the next instruction to be
fetched from memory.It contains the offset of the next word of instruction code instead of
its actual address
h) Status Register:
The status register also called as flag register. The 8086 flag register contents indicate the
results of computation in the ALU. It also contains some flag bits to control the CPU
operations.
Flag register is 16-bit register with only nine bits that are implemented. Six of these are status
flags. The complete bit configuration of 8086 is shown in the figure.

SF (Sign Flag): This flag represents sign of the result.

0-Result is Positive
1-Result is Negative
ZF (Zero Flag): ZF is set if the result produced by an instruction is zero. Otherwise, ZF is
reset.
PF (Parity Flag): This flag is set to 1, if the lower byte of the result contains even number of
1’s.
0- Odd parity
1- Even parity
CF (Carry Flag)
This flag is set, when there is a carry out of MSB in case of addition or borrow in case of
subtraction.
0- No Carry/ Barrow
1- Carry/ Barrow
TF (Trap Flag):
If this flag is set, the processor enters the single step execution mode. When in the single-step
mode, it executes an instruction and then jumps to a special service routine that may
determine the effect of executing the instruction. This type of operation is very useful for
debugging programs.
IF (Interrupt Flag):
If this flag is set, the maskable interrupts are recognized by the CPU, otherwise they are
ignored.
DF (Direction Flag):
This is used by string manipulation instructions.
0- The string is processed beginning from the lowest address to the highest address, i.e., auto
incrementing mode.
1- The string is processed from the highest address towards the lowest address, i.e., auto
incrementing mode.
AC (Auxiliary Carry Flag):
This is set when there is a carry from the lowest nibble (i.e, bit three during addition), or
borrow for the lowest nibble (i.e, bit three, during subtraction).
OF(Over flow Flag):
This flag is set, if an overflow occurs, i.e, if the result of a signed operation is large enough to
accommodate in a destination register.
MEMORY SEGMENTATION
The size of address bus of 8086 is 20 and is able to address 1 Mbytes ( ) of physical memory,
but all this memory is not active at one time. Actually, this 1Mbytes of memory are
partitioned into 16 parts named as segments. Size of the each segment is 64Kbytes (65,536).
Only four of these segments are active at a time:
 Code segment holds the program instruction codes
 Stack segment is used to store interrupt and subroutine return addresses
 Data segment stores data for the program
 Extra segment is an extra data segment (often used for shared data)
 Each of these segments are addressed by an address stored in corresponding segment
registers: CS(code segment), SS(stack segment), DS(data segment), and ES(extra
segment). These registers contain a 16-bit base address that points to the lowest addressed
byte of the segment. Because the segment registers cannot store 20 bits, they only store
the upper 16 bits. The BIU takes care of this problem by appending four 0's to the low-
order bits of the segment register. In effect, this multiplies the segment register contents
by 16.
The segment registers are user accessible, which means that the programmer can change
the content of segment registers through software.
PROGRAMMING MODEL:
How can a 20-bit address be obtained, if there are only 16-bit registers?
However, the largest register is only 16 bits (64k); so physical addresses have to be
calculated. These calculations are done in hardware within the microprocessor.
The 16-bit contents of segment register gives the starting/ base address of particular
segment. To address a specific memory location within a segment we need an offset
address. The offset address is also 16-bit wide and it is provided by one of the associated
pointer or index register.

To be able to program a microprocessor, one does not need to know all of its
hardware architectural features. What is important to the programmer is being aware of
the various registers within the device and to understand their purpose, functions,
operating capabilities, and limitations.
The above figure illustrates the software architecture of the 8086 microprocessor.
From this diagram, we see that it includes fourteenl6-bit internal registers: the instruction
pointer (IP), four data registers (AX, BX, CX, and DX), two pointer registers (BP and
SP), two index registers (SI and DI), four segment registers (CS, DS, SS, and ES) and
status register (SR), with nine of its bits implemented as status and control flags.
 The point to note is that the beginning segment address must begin at an address
divisible by 16.Also note that the four segments need not be defined separately. It is
allowable for all four segments to completely overlap (CS = DS = ES = SS).
Logical and Physical Address
Addresses within a segment can range from address 00000h to address 0FFFFh.
This corresponds to the 64K-bytelength of the segment. An address within a segment is
called an offset or logical address.
A logical address gives the displacement from the base address of the segment to
the desired location within it, as opposed to its "real" address, which maps directly
anywhere into the 1 MByte memory space. This "real" address is called the physical
address.
The physical address is 20 bits long and corresponds to the actual binary code
output by the BIU on the address bus lines. The logical address is an offset from location
0 of a given segment.

You should also be careful when writing addresses on paper to do so clearly. To specify
the logical address XXXX in the stack segment, use the convention SS:XXXX, which is
equal to [SS] * 16 + XXXX.

Logical address is in the form of: Base Address: Offset

Offset is the displacement of the memory location from the starting location of the
segment.
To calculate the physical address of the memory, BIU uses the following formula:

Physical Address = Base Address of Segment * 16 + Offset

Example:
 The value of Data Segment Register (DS) is 2222H.
To convert this 16-bit address into 20-bit, the BIU appends 0H to the LSB (by multiplying
with 16) of the address. After appending, the starting address of the Data Segment
becomes 22220H.
Data at any location has a logical address specified as:2222H: 0016H
Where 0016H is the offset, 2222 H is the value of DS
Therefore the physical address:22220H + 0016H: 22236 H
The following tables describes the default offset values to the corresponding memory
segments.

Some of the advantages of memory segmentation in the 8086 are as follows:

 With the help of memory segmentation a user is able to work with registers having only
16-bits.
 The data and the user’s code can be stored separately allowing for more flexibility.
 Also due to segmentation the logical address range is from 0000H to FFFFH the code can
be loaded at any location in the memory.
MEMORY ADDRESS
As far as we know 8086 is 16-bit processor that can supports 1Mbyte (i.e. 20-bit address bus:
220) of external memory over the address range 0000016 to FFFFF16. The 8086 organizes
memory as individual bytes of data. The 8086 can access any two consecutive bytes as a
word of data. The lower-addressed byte is the least significant byte of the word, and the
higher- addressed byte is its most significant byte.

The above figure represents: storage location of address 0000916 contains the value 716,
while the location of address 0001016 contains the value 7D16. The 16-bit word 225A16is
stored in the locations 0000C16 to 0000D16
The word of data is at an even-address boundary (i.e. address of least significant byte is even)
is called aligned word. The word of data is at an odd-address boundary is called misaligned
word, as shown in Figure below.
To store double word four locations are needed. The double word that it’s least significant
byte address is a multiple of 4 (e.g. 0 16, 416, 816 ...) is called aligned double word. The
double word at address of non-multiples of 4 is called misaligned double word shown in
Figure below.

PHYSICAL MEMORY ORGANIZATION:

The 8086’s 1Mbyte memory address space is divided in to two independent 512Kbyte banks:
the low (even) bank and the high (odd) bank. Data bytes associated with an even address
(0000016, 0000216, etc.) reside in the low bank, and those with odd addresses (0000116,
0000316, etc.) reside in the high bank.
Address bits A1 through A19 select the storage location that is to be accessed. They are
applied to both banks in parallel. A0and bank high enable (BHE) are used as bank-select
signals.
The four different cases that happen during accessing data:
Case 1: When a byte of data at an even address (such as X) is to be accessed:

 A0 is set to logic 0 to enable the low bank of memory.

 BHE is set to logic 1 to disable the high bank.
Case 2: When a byte of data at an odd address (such as X+1) is to be accessed:

 A0is set to logic 1 to disable the low bank of memory.

 BHE is set to logic 0 to enable the high bank.
Case 3: When a word of data at an even address (aligned word) is to be accessed:

 A0 is set to logic 0 to enable the low bank of memory.

 BHE is set to logic 0 to enable the high bank.
Case 4: When a word of data at an odd address (misaligned word) is to be accessed, then the
8086 need two bus cycles to access it:
a) During the first bus cycle, the odd byte of the word (in the high bank) is addressed

 A0 is set to logic 1 to disable the low bank of memory

 BHE is set to logic 0 to enable the high bank.
b) During the second bus cycle, the odd byte of the word (in the low bank) is addressed

 A0is set to logic 0 to enable the low bank of memory.

 BHE is set to logic 1 to disable the high bank.
SIGNAL DESCRIPTION OF 8086
Intel 8086 is a 16-bit HMOS microprocessor. It is available in 40 pin DIP chip. It uses a 5V
DC supply for its operation. The 8086 uses 20-line address bus. It has a 16-line data bus. The
20 lines of the address bus operate in multiplexed mode. The 16-low order address bus lines
have been multiplexed with data and 4 high-order address bus lines have been multiplexed
with status signals.

Power supply and frequency signals

It uses 5V DC supply at VCC pin 40, and uses ground at VSS pin 1 and 20 for its operation.
Clock signal
Clock signal is provided through Pin-19. It provides timing to the processor for operations.
Its frequency is different for different versions, i.e. 5MHz, 8MHz and 10MHz.
Address/data bus
AD0-AD15. These are 16 address/data bus. AD0-AD7 carries low order byte data and
AD8AD15 carries higher order byte data. During the first clock cycle, it carries 16-bit
address and after that it carries 16-bit data.
Address/status bus
A16-A19/S3-S6. These are the 4 address/status buses. During the first clock cycle, it carries
4-bit address and later it carries status signals.
 ___
S7/BHE
BHE stands for Bus High Enable. It is available at pin 34 and used to indicate the transfer of
data using data bus D8-D15. This signal is low during the first clock cycle, thereafter it is
active.
___
Read(RD)
It is available at pin 32 and is used to read signal for Read operation.
Ready
It is available at pin 32. It is an acknowledgement signal from I/O devices that data is
transferred. It is an active high signal. When it is high, it indicates that the device is ready to
transfer data. When it is low, it indicates wait state.
RESET
It is available at pin 21 and is used to restart the execution. It causes the processor to
immediately terminate its present activity. This signal is active high for the first 4 clock
cycles to RESET the microprocessor.
INTR
It is available at pin 18. It is an interrupt request signal, which is sampled during the last
clock cycle of each instruction to determine if the processor considered this as an interrupt
or not.
NMI
It stands for non-maskable interrupt and is available at pin 17. It is an edge triggered input,
which causes an interrupt request to the microprocessor.
_____
TEST
This signal is like wait state and is available at pin 23. When this signal is high, then the
processor has to wait for IDLE state, else the execution continues.
___
MN/MX
It stands for Minimum/Maximum and is available at pin 33. It indicates what mode the
processor is to operate in; when it is high, it works in the minimum mode and vice-aversa.
____
INTA
It is an interrupt acknowledgement signal and id available at pin 24. When the
microprocessor receives this signal, it acknowledges the interrupt.
ALE
It stands for address enable latch and is available at pin 25. A positive pulse is generated
each time the processor begins any operation. This signal indicates the availability of a valid
address on the address/data lines.
___
DEN
It stands for Data Enable and is available at pin 26. It is used to enable Transreceiver 8286.
The transreceiver is a device used to separate data from the address/data bus.
_
DT/R
It stands for Data Transmit/Receive signal and is available at pin 27. It decides the direction
of data flow through the transreceiver. When it is high, data is transmitted out and vice-a-
versa.
__
M/IO
This signal is used to distinguish between memory and I/O operations. When it is high, it
indicates I/O operation and when it is low indicates the memory operation. It is available at
pin 28.
__
WR
It stands for write signal and is available at pin 29. It is used to write the data into the
memory or the output device depending on the status of M/IO signal.
HLDA
It stands for Hold Acknowledgement signal and is available at pin 30. This signal
acknowledges the HOLD signal.
HOLD
This signal indicates to the processor that external devices are requesting to access the
address/data buses. It is available at pin 31.

QS1 and QS0

These are queue status signals and are available at pin 24 and 25. These signals provide the
status of instruction queue. Their conditions are shown in the following table −
QS0 QS1 Status

0 0 No operation

0 1 First byte of opcode from the queue

1 0 Empty the queue

1 1 Subsequent byte from the queue

__ __ __
S0, S1, S2
These are the status signals that provide the status of operation, which is used by the Bus
Controller 8288 to generate memory & I/O control signals. These are available at pin 26, 27,
and 28. Following is the table showing their status −
S2 S1 S0 Status

0 0 0 Interrupt acknowledgement

0 0 1 I/O Read

0 1 0 I/O Write

0 1 1 Halt

1 0 0 Opcode fetch

1 0 1 Memory read

1 1 0 Memory write

1 1 1 Passive
____
LOCK
When this signal is active, it indicates to the other processors not to ask the CPU to leave the
system bus. It is activated using the LOCK prefix on any instruction and is available at pin
29.
___ ___ ___ ___
RQ/GT1 and RQ/GT0
These are the Request/Grant signals used by the other processors requesting the CPU to
release the system bus. When the signal is received by CPU, then it sends acknowledgment.
RQ/GT0 has a higher priority than RQ/GT1.
 Comparison between Minimum & Maximum mode
Minimum mode Maximum mode

In minimum mode there can be only one In maximum mode there can be multiple processors
processor i.e. 8086. with 8086, like 8087 and 8089.

___ ___
MN/MX is 1 to indicate minimum mode. MN/MX is 0 to indicate maximum mode.

ALE for the latch is given by 8086 as it is the ALE for the latch is given by 8288 bus controller as
only processor in the circuit. there can be multiple processors in the circuit.

____ _ ____ _
DEN and DT/R for the trans-receivers are DEN and DT/R for the trans-receivers are given by
given by 8086 itself. 8288 bus controller.

__ __ ___ Instead of control signals, each processor generates

M/IO, RD and WR are given by 8086. status signal called __ __ __
S2, S1and S0.

__ __ ___ __ __ __
M/IO, RD and WR are decoded by a 3:8 Status signal called S2, S1and S0.are decoded by a
decoder like 74138. bus controller like 8288 to produce control signals.

____ ____
INTA is given by 8086 in response to an INTA is given by 8288 bus controller in response to
interrupt on INTR line. an interrupt on INTR line.

HOLD and HLDA signals are used for bus ___ __

request with a DMA controller like 8237. RQ/GT lines are used for bus requests by other
processors like 8087 or 8089.

The circuit is simpler. The circuit is more complex.

Multiprocessing cannot be performed hence As multiprocessing can be performed, it can give

performance is lower. very high performance.

TIMING DIAGRAM
Timing Diagram is a graphical representation. It represents the execution time taken
by each instruction in a graphical format. The execution time is represented in T-states.

Microprocessor performs an operation in a specific time period i.e. specific clock

cycles known as T-state
No. of T-state required to access a peripheral is called Machine Cycle Access a
peripheral means to perform a read or a write operation either from memory or an I/O In
8086 Memory read or memory write require 4 T-states.
Time taken by processor to execute an instruction is called Instruction Cycle
Timing diagram for general Minimum operation
For Write Cycle

For Read Cycle

Timing diagram for general Maximum operation

For Write cycle
INTERRUPT OF 8086:
Interrupt is the method of creating a temporary halt during program execution and
allows peripheral devices to access the microprocessor. An interrupt is a special condition
that arises during the working of a microprocessor. The microprocessor services it by
executing a subroutine called Interrupt Service Routine (ISR).
ISR is a short program to instruct the microprocessor on how to handle the interrupt.
The following image shows the types of interrupts we have in a 8086 microprocessor −

Hardware Interrupts
Hardware interrupt is caused by any peripheral device by sending a signal through a
specified pin to the microprocessor.
The 8086 has two hardware interrupt pins, i.e. NMI and INTR. NMI is a non-maskable
interrupt and INTR is a maskable interrupt having lower priority.
NMI
It is a single non-maskable interrupt pin (NMI) having higher priority than the maskable
interrupt request pin (INTR) and it is of type 2 interrupt.
When this interrupt is activated, these actions take place −
 Completes the current instruction that is in progress.
 Pushes the Flag register values on to the stack.
 Pushes the CS (code segment) value and IP (instruction pointer) value of the return
address on to the stack.
 IP is loaded from the contents of the word location 00008H.
 CS is loaded from the contents of the next word location 0000AH.
 Interrupt flag and trap flag are reset to 0.
INTR
The INTR is a maskable interrupt because the microprocessor will be interrupted only if
interrupts are enabled using set interrupt flag instruction. It should not be enabled using clear
interrupt Flag instruction.
The INTR interrupt is activated by an I/O port. If the interrupt is enabled and NMI is
disabled, then the microprocessor first completes the current execution and sends ‘0’ on
INTA pin twice. The first ‘0’ means INTA informs the external device to get ready and
during the second ‘0’ the microprocessor receives the 8 bit, say X, from the programmable
interrupt controller.
These actions are taken by the microprocessor −
 First completes the current instruction.
 Activates INTA output and receives the interrupt type, say X.
 Flag register value, CS value of the return address and IP value of the return address
are pushed on to the stack.
 IP value is loaded from the contents of word location X × 4
 CS is loaded from the contents of the next word location.
 Interrupt flag and trap flag is reset to 0
Software Interrupts
Some instructions are inserted at the desired position into the program to create interrupts.
These interrupt instructions can be used to test the working of various interrupt handlers. It
includes −

INT- Interrupt instruction with type number

It is 2-byte instruction. First byte provides the op-code and the second byte provides the
interrupt type number. There are 256 interrupt types under this group.
Its execution includes the following steps −
 Flag register value is pushed on to the stack.
 CS value of the return address and IP value of the return address are pushed on to the
stack.
 IP is loaded from the contents of the word location ‘type number’ × 4
 CS is loaded from the contents of the next word location.
 Interrupt Flag and Trap Flag are reset to 0
The starting address for type0 interrupt is 000000H, for type1 interrupt is 00004H similarly
for type2 is 00008H and ……so on. The first five pointers are dedicated interrupt pointers.
i.e. −
INT 0 (Divide Error)-
o This interrupt occurs whenever there is division error i.e. when the result of a
division is too large to be stored. This condition normally occurs when the
divisor is very small as compared to the dividend or the divisor is zero.
o Its ISR address is stored at location 0 x 4 = 00000H in the IVT.
INT 1 (Single Step)-
o The microprocessor executes this interrupt after every instruction if the TF is
set.
o It puts microprocessor in single stepping mode i.e. the microprocessor pauses
after executing every instruction. This is very useful during debugging.
o Its ISR generally displays contents of all registers. Its ISR address is stored at
location 1 x 4 = 00004H in the IVT.
INT 2 (Non mask-able Interrupt)-
o The microprocessor executes this ISR in response to an interrupt on the NMI
(Non mask-able Interrupt) line.
o Its ISR address is stored at location 2 x 4 = 00008H in the IVT.
INT 3 (Breakpoint Interrupt)-
o This interrupt is used to cause breakpoints in the program. It is caused by
writing the instruction INT 03H or simply INT.
o It is useful in debugging large programs where single stepping is efficient.
o Its ISR is used to display the contents of all registers on the screen. Its ISR
address is stored at location 3 x 4 = 0000CH in the IVT.
INT 4 (Overflow Interrupt)-
o This interrupt occurs if the overflow flag is set and the microprocessor
executes the INTO (Interrupt on Overflow) instruction.
o It is used to detect overflow error in signed arithmetic operations.
o Its ISR address is stored at location 4 x 4 = 00010H in the IVT.
Reserved interrupts (INT 5…..INT 31):
1. These levels are reserved by Intel to be used in higher processors like 80386, Pentium
etc. They are not available to the user.
Available interrupts (INT 32…..INT 225):
1. These are user defined, software interrupts.
2. ISRs for these interrupts are written by the users to service various user defined
conditions.
3. These interrupts are invoked by writing the instruction INT n. Its ISR address is
obtained by the microprocessor from location n x 4 in the IVT.
Its execution includes the following steps −
 Flag register value is pushed on to the stack.
 CS value of the return address and IP value of the return address are pushed on to the
stack.
 IP is loaded from the contents of the word location 3×4 = 0000CH
 CS is loaded from the contents of the next word location.
 Interrupt Flag and Trap Flag are reset to 0
INTO - Interrupt on overflow instruction
It is a 1-byte instruction and their mnemonic INTO. The op-code for this instruction is CEH.
As the name suggests it is a conditional interrupt instruction, i.e. it is active only when the
overflow flag is set to 1 and branches to the interrupt handler whose interrupt type number is
4. If the overflow flag is reset then, the execution continues to the next instruction.
Its execution includes the following steps −
 Flag register values are pushed on to the stack.
 CS value of the return address and IP value of the return address are pushed on to the
stack.
 IP is loaded from the contents of word location 4×4 = 00010H
 CS is loaded from the contents of the next word location.
 Interrupt flag and Trap flag are reset to 0