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8086 Microprocessor

The document discusses the features and specifications of the 8086 microprocessor. It was introduced in 1978 and had a maximum clock speed of 10MHz. It had a 16-bit architecture and could access up to 1MB of memory. The document describes the pinout of the 8086, including power, clock, address/data, and control signal pins. It also explains the differences between the minimum and maximum operating modes of the 8086.

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Achyut Tripathi
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351 views19 pages

8086 Microprocessor

The document discusses the features and specifications of the 8086 microprocessor. It was introduced in 1978 and had a maximum clock speed of 10MHz. It had a 16-bit architecture and could access up to 1MB of memory. The document describes the pinout of the 8086, including power, clock, address/data, and control signal pins. It also explains the differences between the minimum and maximum operating modes of the 8086.

Uploaded by

Achyut Tripathi
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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8086

MICROPROCESSOR
Dr.R.KUMARAVELU/Associate Professor
School of Computer Science and Engneering
VIT University - Vellore
Topics to be covered
 8086 Features
 8086 Pin Diagram
 8086 Package Types
 Common Signals
 Minimum Mode Signals
 Maximum Mode Signals
 Pin Description
 About Min and Max Mode
8086 Features
 Introduction period : 1978 to 1990
 Common Manufacturers : Intel, AMD, NEC, Fujitsu,
etc.,
 Max CPU Clock Speed : 5Mhz to 10 Mhz
 Instruction Set : x86 – 16
 Predecessor : 8080
 Successor : 80186 and 80286
 Package : 40 Pin DIP
 Variant : 8088
8086 Features – Cont…
 It has 20 bit address bus which can access up to 220
memory locations (1 MB)
 It can support up to 64KB I/O Ports
 It provides 14 nos. of 16-bit registers
 Its word size is 16 bit
 It has multiplexed address and data bus AD0-AD15
and A16-A19
 It is designed to operate in two modes, Max and Min
 It requires 5V power supply
 Memory is byte addressable
8086 Pin Diagram
Package Types – DIP, PLCC

DIP/DIL – Dual in-line Package, PLCC – Plastic Leaded Chip


Carriers
Common Signals
Minimum Mode Signals
Maximum Mode Signals
Pin Description
Power supply and frequency signals
It uses 5V DC supply at VCC pin 40, and uses ground at VSS pin 1 and 20 for its
operation.

Clock signal
Clock signal is provided through Pin-19. It provides timing to the processor for
operations. Its frequency is different for different versions, i.e. 5MHz, 8MHz and
10MHz.

Address/data bus
AD0-AD15. These are 16 address/data bus. AD0-AD7 carries low order byte
data and AD8AD15 carries higher order byte data. During the first clock cycle, it
carries 16-bit address and after that it carries 16-bit data.

Address/status bus
A16-A19/S3-S6. These are the 4 address/status buses. During the first clock
cycle, it carries 4-bit address and later it carries status signals.
Pin Description – Cont…
____
S7 / BHE

BHE stands for Bus High Enable. It is available at pin 34 and used to indicate
the transfer of data using data bus D8-D15. This signal is low during the first
clock cycle, thereafter it is active.

___
RD

It is available at pin 32 and is used to read signal for Read operation.

READY

It is available at pin 32. It is an acknowledgement signal from I/O devices that


data is transferred. It is an active high signal. When it is high, it indicates that
the device is ready to transfer data. When it is low, it indicates wait state.
Pin Description – Cont…
RESET
It is available at pin 21 and is used to restart the execution. It causes the
processor to immediately terminate its present activity. This signal is active
high for the first 4 clock cycles to RESET the microprocessor.

INTR
It is available at pin 18. It is an interrupt request signal, which is sampled
during the last clock cycle of each instruction to determine if the processor
considered this as an interrupt or not.

NMI
It stands for non-maskable interrupt and is available at pin 17. It is an edge
triggered input, which causes an interrupt request to the microprocessor.
Pin Description – Cont…
TEST
This signal is like wait state and is available at pin 23. When this signal is high,
then the processor has to wait for IDLE state, else the execution continues.

___
MN/MX
It stands for Minimum/Maximum and is available at pin 33. It indicates what
mode the processor is to operate in; when it is high, it works in the minimum
mode and vice-versa.
____
INTA
It is an interrupt acknowledgement signal and id available at pin 24. When the
microprocessor receives this signal, it acknowledges the interrupt.

ALE
It stands for address enable latch and is available at pin 25. A positive pulse is
generated each time the processor begins any operation. This signal indicates
the availability of a valid address on the address/data lines.
Pin Description – Cont…
____
DEN

It stands for Data Enable and is available at pin 26. It is used to enable
Transceiver 8286. The transceiver is a device used to separate data from
the address/data bus.
_
DT/R

It stands for Data Transmit/Receive signal and is available at pin 27. It


decides the direction of data flow through the transceiver. When it is high,
data is transmitted out and vice-a-versa.
Pin Description – Cont…
__
M/IO
This signal is used to distinguish between memory and I/O operations. When it
is high, it indicates memory operation and when it is low indicates the I/O
operation. It is available at pin 28.
___
WR
It stands for write signal and is available at pin 29. It is used to write the data
into the memory or the output device depending on the status of M/IO signal.

HLDA
It stands for Hold Acknowledgement signal and is available at pin 30. This signal
acknowledges the HOLD signal.

HOLD
This signal indicates to the processor that external devices are requesting to
access the address/data buses. It is available at pin 31.
Pin Description – Cont…
QS1 and QS0

These are queue status signals and are available at pin 24 and 25. These
signals provide the status of instruction queue. Their conditions are shown in
the following table −

QS0 QS1 Status


0 0 No Operation
0 1 First byte of
Opcode from the
queue
1 0 Empty the Queue
1 1 Subsequent byte
from the Queue
Pin Description – Cont…
S0, S1, S2

S2 S1 S0 Status
0 0 0 Interrupt
Acknowledge
0 0 1 I/O Read
0 1 0 I/O Write
0 1 1 Halt
1 0 0 Opcode Fetch
1 0 1 Memory Read
1 1 0 Memory Write
1 1 1 Passive
Pin Description – Cont…

_____
LOCK

When this signal is active, it indicates to the other processors not to ask the
CPU to leave the system bus. It is activated using the LOCK prefix on any
instruction and is available at pin 29.

___ ___ ___ ___


RQ/GT1 and RQ/GT0

These are the Request/Grant signals used by the other processors


requesting the CPU to release the system bus. When the signal is received
by CPU, then it sends acknowledgment. RQ/GT0 has a higher priority than
RQ/GT1.
About Min and Max Mode
Max Mode Min Mode
When MIN/MAX is low, When MIN/MAX is high,
8086 is in maximum mode. 8086 is in minimum mode.
In maximum mode there are
multiple processors in the In minimum mode only one
system. Whereas in 8086 processor is available.
maximum mode interfacing, In minimum mode no
master/slave and interfacing or master/slave
multiplexing and several signal is required.
such controls are required.
In Maximum mode bus
controller us required.

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