AMS Assignment Shivajee Gautam

Testability for VLSI Name: Shivajee Gautam
WILP ID: 2017HT80552

Assignment-2 Subject: MEL ZG531
 Topic: Analog and Mixed- signal testing
Contents
 Introduction
 AMS Testing methodologies
 Test List Selection and Simulation-Based
 DSP-Enabled Instruments and Automation
 BIST for Analog & Mixed Signal Circuits
 Other Methods
INTRODUCTION
Testing analog circuits very different from digital circuits. It requires determination
of output signal quality not just a simple logic 0-1 or high-low. Many variations are
expected in output signal waveforms due to acceptable component parameter
variation and environmental variations (temperature, voltage, noise, etc.). Analog
fault models not well defined for DFT which results Catastrophic (hard) faults such
as components missing, disconnected (open terminals) or shorted out or can be
Parametric (soft) faults such as components out of acceptable tolerance range.
Old approaches of testing includes the Ad-hoc testing and the new ones includes
even BIST testing.
Many robust method have been developed for the test and characterization of
analog and mixed-signal integrated circuits. The given method relies on a compact,
robust, and easily synthesized integrated test core capable of emulating the function
of extreme automatic test equipment. The core consists of a 2 x N memory whose
contents are periodically circulated, a coarse analog filter, and a voltage comparator.
First half of the circular memory is used to generate analog signals without the need
for multi-bit digital-to-analog converters. The second half is used to generate
extremely accurate DC levels, the latter being programmed using a dever software
encoding technique that relies on form of sigma-delta modulation. The DC levels, in
combination with the comparator, enable multi-bit digitization using a progressive
multiple conversion pass procedure. In order to accommodate broadband circuit
phenomena, a delayed-clock sub-sampling mechanism is also employed, in which
the digitizer sample dock is consistently delayed over multiple runs of the periodic
test signal. One method of delaying the dock is to use a voltage- controlled delay line
tuned by a delay-Iocked loop. The timing resolution of this approach is determined
by the value of the consistent dock delay and not its period.
A divide-and-conquer approach to the test of deeply embedded analog integrated
circuits using the proposed test core is described. Multiple test configurations are
presented that can span a wide range of phenomena to be tested both internally to
the integrated circuit and externally through 1/0 interfaces. The applicability of
these configurations to increasing test parallelism both at the core and die levels is
investigated. Performance limits of the proposed test core are also derived by
drawing a comparison to conventional circuits used for data-conversion
applications. The same fundamental limitations on integrated circuit performance
are shown to affect the test core electronics, although testspecifie requirements,
such as forcing periodicity and the reliance on software signal processing, help
further enhance on-chip measurement accuracy and repeatability. Finally, several
successful experimental prototypes that demonstrate the viability of the proposed
approach are presented. The prototypes range from concept proving test core
integrated circuits to ones containing multiple simultaneously operated test cores
and completely embedded circuits under test.
In this dissertation, we address the test of a class of semiconductor device that
integrates mixed technologies, such as digital and analog circuits. This class of
device continues to pose significant test challenges not only during production but
also during design validation and characterization. The main reasons for these
challenges are the conflicting test requirements for the analog and digital portions,
the complex interaction between the parts, and the access issues that arise with
increasing analog circuit integration. To tackle these challenges, we propose the use
of embedded mixed-signal test cores, which are integrated circuit macros that
emulate the functions of full-fledged automatic test equipment (ATE). Specifically,
the embedded test cores proposed in this thesis are designed to perform De curve-
tracing, oscilloscope, timing, and frequency domain measurements using compact
and mostly digital integrated electronics.
 AMS Testing methodologies

Two main ingredients contribute to a successful and economic production test plan
for analog and mixed-signal devices. The first is a collection of test strategies that
attempt to minimize the time it takes to measure a device without significantly
compromising the ability to screen faulty ones. The second is the collection of
instruments used to perform the measurements themselves. Following new
methodologies are being used for testing:
Test List Selection and Simulation-Based Methodologies

Much of the recent mixed-signal test research falls under the category of reducing
test time. The reason is that specification-based testing, although foolproof, can in
sorne cases be extremely time-consuming. A quick look at the data sheet of even the
simplest analog or mixed-mode le would reveal that specifications span a wide
range of input and environmental (such as power supply and operating
temperature) conditions. Testing all of these conditions during production would be
slow. The question then is whether a simplified set of signaIs or input conditions can
be used to excite the device under test (DUT) and uncover most of the possible
failures that could occur during fabrication.
Traditionally, this question has been answered through an empirical approach in
which a reasonably large number of fabricated devices are subjected to full
specification testing. The results of this procedure are then used to compile a short
list of tests that fail most of the defective parts. Over the rest of the product life for
the part, only this trimmed test list is used to screen the manufactured devices, and
redundant tests are simply omitted. Moreover, it is also conceivable that there be
significant correlation between tests and that more than one test can fail the same
faulty device. Recognizing this, early work in mixed-signal integrated circuit testing
consisted of methods for not only reducing the test list in the manner just described
but for also choosing an order in which tests are applied. As such, the test that is
most likely to fail is applied first, followed by less likely ones.
Generic Flow of Simulation Based test methodology
In these methods, the layout of the circuit under test is modified according to the
effects of these defects, the new extracted circuit is simulated, and the response of
this new "faulty" circuit is compared to the response of the original one. Depending
on the input conditions and the resulting response comparison, sorne test signaIs
can be found to be "useful" in detecting manufacturing defects, while others are
deemed not useful . As can be seen, the result of the above procedure is a short set of
test stimuli (DC, AC, or transient) that need to be applied to a DUT during the actual
test phase and a second set of expected "signatures" or circuit responses that enable
the distinction between a good part and a bad one.
DSP-Enabled Instruments and Automation

Regardless of how test list selection is performed or whether only defects should be
targeted as opposed to full specification testing, the ability to deliver signaIs reliably
to the DUT has never been under such scrutiny as it is right now. The physicallimits
of interconnections between instrument and DUT and the disparate nature of DUT
and instrument result in serious difficu1ties in modem-day test arrangements,
whether on design-validation benches or on production floors. As will be shown in
this thesis, the goal of this research is to demonstrate flexible test capability on-chip,
thus avoiding interconnect related difficu1ties, and to provide much improved
correlation between bench measurement and production testing. Improved
correlation cornes about, of course, because the same measurement instruments (in
our case, the proposed test cores) and input conditions are used during both design
validation and production testing.
A block-diagram illustration of a DSP-based spectrum analyzer is inc1uded in Fig.

which also includes an extension to higher-frequency signaIs. In such an extension,
the high-frequency signal is first transported to a lower frequency by passing it
through a mixer that is driven by spectrally pure local oscillator. The lower
frequency is chosen to fall within the range that the ND converter can tolerate
without compromising accuracy. Moving a bit higher in frequency, further
modifications to the basic block diagram are necessary.
BIST for Analog & Mixed Signal Circuits
LFSR sufficient for digital pseudorandom TPG, But analog circuits require different
test signals. Traditional signature and syndrome analysis work for digital BIST since
results are exact Analog circuit output response expected to vary which can prevent
reproducible results quantization noise in DACs and ADCs, Tolerances in analog
component parameters, Environmental variations (temp., voltage, noise), Expect
range of good circuit signature values for analog and mixed-signal test approaches.
 TPG generates 16 test waveforms:

 Counter (up, down, & up/down) : ramp, sawtooth & triangle waveforms
 LFSR (pseudo-random patterns) : white-noise-like waveforms
 Magnitude register : programmable amplitude DC, impulse, & step
response tests
 Frequency sweep : varying & programmable amplitudes
 Bit reversal (for most waveforms): noise & random
frequencies/amplitudes
OTHER Approaches
Oscillator BIST
 During test mode, circuit is converted to oscillator: Measure
frequency of oscillation to detect faults
 Works for most analog circuits: Automated synthesis for many
analog circuits, Developed by OpMaxx (now part of Fluence)
 Has been attempted in digital circuits: Results have been
promising
 Effect on system performance is not well known : Extra
capacitive & resistive loading on original circuit
Histogram-based Analog BIST (HABIST) (Fluence)
 Known good & CUT histograms are normalized
 Adjustments made for offset & gain variations
 The two are subtracted to obtain difference histogram
 Used to determine detection of faults

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Testability for VLSI Name: Shivajee Gautam

WILP ID: 2017HT80552

 Topic: Analog and Mixed- signal testing

 AMS Testing methodologies

Test List Selection and Simulation-Based Methodologies

DSP-Enabled Instruments and Automation

A block-diagram illustration of a DSP-based spectrum analyzer is inc1uded in Fig.

 TPG generates 16 test waveforms:

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