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Modelsim Installation Steps: Center of Advance Studies in Engineering, Islamabad

The document provides steps to install and use ModelSim software for digital logic design simulation. It describes downloading and activating the software, creating a new project, adding Verilog files to the project, compiling and simulating a sample AND gate code, and viewing the output waveform to verify the design works as intended. The steps allow a user to get started with creating, testing and debugging digital circuits using ModelSim.

Uploaded by

Usama Javid Mughal
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© © All Rights Reserved
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Download as DOC, PDF, TXT or read online on Scribd
37 views

Modelsim Installation Steps: Center of Advance Studies in Engineering, Islamabad

The document provides steps to install and use ModelSim software for digital logic design simulation. It describes downloading and activating the software, creating a new project, adding Verilog files to the project, compiling and simulating a sample AND gate code, and viewing the output waveform to verify the design works as intended. The steps allow a user to get started with creating, testing and debugging digital circuits using ModelSim.

Uploaded by

Usama Javid Mughal
Copyright
© © All Rights Reserved
Available Formats
Download as DOC, PDF, TXT or read online on Scribd
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Center of Advance Studies in Engineering, Islamabad

Modelsim Installation Steps

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Browse to license file from the crack.

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Now run the other file

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Verilog Start Up Program in ModelSim


ModelSim is a Model Technology’s excellent VHDL / Verilog simulator. In these brief steps we would
try to learn the how to operate Modelsim for simulation.

1. Double click on the ModelSim program icon on your desktop.


2. Now you can see that ModelSim window has opened.

3. We shall create a new project. Any kind of


project can be created in the similar way.
 Click on file.
 Come to new
 From here click on the Project.

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4. The create Project window would appear.


 Type the Project Name and Project Location
(You can type any name and can set any
location).
 Don’t change the Default Library name. At
this level it is too advanced to change it.
 Then Press Ok.

5. Now another window would appear.


 From here you can enter an existing file to the
project or you can create new file.
 As we are creating new file click on the “Create
new file.”

6. After that this window appears.


In it do the following things.
 In the “Add file as type”
field set Verilog.
 Write the file name in
the :file name” field.
 Click on OK

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7. Now there shall be this dialog box. If you want to enter more file then repeat the above
explained procedure otherwise click on close.

8. Now you can see that you entered file has been added in the workspace (as shown in the
above figure). As we are using pirated edition of the software, there is a small problem. That
problem is that we cannot compile our file at this
level. To do that you have to perform the following
steps as well.
 Right click on the file name in the workspace.
 Click on the “Remove from project”.
 Another dialogue box, shown on right shall appear.

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 Don’t check the delete file box, just press “OK”.


 The file shall be removed from your project.
 Now you have to add that file again into the project. For that perpose right click on the
workspace area. From the menu select
“Add to project”.

 Another menu shall open. Select from


here “Add existing file.”

 Now this dialogue box shall appear. By


using browse select your recently created
file.
 Check the box “Copy to project directory.”
Now click on OK.

 Now this dialogue box shall


appear. By using browse select
your recently created file. Check
the box “Copy to project
directory.” Now click on OK.

9. Now you can see a “?” mark coming in front of


the file name. This means that now the file can
be compiled.

10. Double click on the file name in the workspace a window shall be open in the work area. You
can enter your any verilog code here. For example I have entered the code of an AND gate.

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module my_and(a,b,c);
input a, b;
output c;

and a1 (c,a,b);

endmodule

Now you need to create stimulus/ test bench in order to simulate the main module, For this,
create another file and file and write the following code of test bench in it:

module test;
reg a, b;
wire c;

my_and m (c,a,b);

endmodule

For the sake of practice you can simply past this code in your program because it is error free.

11. After entering the code follow the following steps.


 Save the file.
 Right click on the file name in the workspace.
 Move your cursor to the compile.
 Another menu shall appear, from here select compile selected.
 If there is no error in your code then a green tick shall appear after the name of your file,
otherwise there shall be a red cross.

12. Now to see the graph of your code. Click on


“Library”.

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13. Here click at the “+” sign of work. A submenu shall


open.

14. In the submenu contacts on your computer can vary


from those shown in the above picture. Don’t worry
about it. In the items shown in the submenu there shall
be a link of the name of your test bench. Double click on
that. (In our example test bench is “Test”. This name
shall be there, double click on it).

15. Now the window like this shall appear there. Here right
click on the test, in the submenu go to add and click on
add to wave.

16. How to click on the add to wave is illustrated in this


picture.

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17. Window like this shall appear there.

In the above figure click on the encircled arrow. This will start simulation and you will get final
picture as shown bellow.

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Now try to do something yourself. All the steps for simulation are same only your logic shall be
different.

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