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    Memory Organization: Answer Keys and Explanations

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    Jay Rajput
    basics of linked li

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    Memory Organization: Answer Keys and Explanations

    Uploaded by

    Jay Rajput
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    basics of linked li

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    basics of linked li

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    13 views5 pages

    Memory Organization: Answer Keys and Explanations

    Uploaded by

    Jay Rajput
    basics of linked li

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    of 5

    Chapter Test COA

    Memory Organization
    Answer Keys and Explanations

    1. [Ans. *] Range: 8 to 8
    Cache memory size

    2. [Ans. *] Range: 5 to 5

    Number of decoders of size 2

    So that 4 16 Decoder (one) is required, number of 2 4 decoder = 4(first


    level)+1(second level) =5.

    3. [Ans. *] Range: 2 to 2
    Block size = 4 words

    Physical Address = 16 bit


    PA=16bit

    TAG (6) BO (8) 2 (word


    offset)
    TAG controller size = (6+2) N
    = 8 256
    = 2k bits

    4. [Ans. *] Range: 570 to 570


    Number of reference made ( ) of P for module 1
    80% of 3000 = 24,000.
    Number of reference made ( ) of P for module 2
    95% of 600 =570

    : 080-617 66 222, [email protected] ©Copyright reserved. Web:www.thegateacademy.com 1


    Chapter Test COA

    5. [Ans. C]
    1 Block size = 1KB (0-1023 word)
    Reference
    MM
    0, 8,16,24
    0
    1,9,17,25
    1
    2,10,18,2
    6 K(MOD)N
    3,11,19,2
    7 :
    4,12,20,2
    8
    5,13,21,2
    9
    6,14,22,3
    0 31
    7,15,23,3
    1 M=32Block
    N=8
    PA=15bit

    2-bit 3 10bit

    Option (A) TAG BO WO

    00 0 00 0 111 110 010


    Given word not matching with TAG

    Option (B) TAG BO WO

    00 0 00 1 111 000 010


    Given word not found in the cache

    TAG BO WO
    Option (C)
    01 0 00 1 100 011 010
    Given TAG and cache TAG is matching.
    is found in cache.

    : 080-617 66 222, [email protected] ©Copyright reserved. Web:www.thegateacademy.com 2


    Chapter Test COA

    TAG BO WO

    Option (D) 11 1 11 1 000 000 000

    Block 7
    In Block No: - ‘ ’ ag gv n n a ng ‘ ’
     Word not found in cache.

    6. [Ans. D]

    7. [Ans. *] Range: 5 to 5
    a a an a aa a
    n
    n
    5 Million word/second

    8. [Ans. C]
    OC795H
    BO: Block offset
    0000 11 00 0111 1 001 0 101 WO: Word offset
    TAG BO WO

    a
    TAG field = 000011

    9. [Ans. C]

    10. [Ans. *] Range: 69 to 69

    Conflict misses will not occurs in full associative cache.


    Hence Miss rate is 20%+30% = 50%
    AMAT = 19 ns 50%+50 %( 119)
    = 69 ns

    11. [Ans. *] Range: 72 to 72


    120 ns=20 80%+20% ( )
    120 ns=16 ns+0.2

    New Hit ratio


    n n
    H = 72%

    : 080-617 66 222, [email protected] ©Copyright reserved. Web:www.thegateacademy.com 3


    Chapter Test COA

    12. [Ans. *] Range:175 to 175


    AMAT = 85% 100 + 15% (600 ns)
    = 85 ns + 90 ns
    = 175ns

    13. [Ans. *] Range: 230 to 230


    ⏟ ⏟

    = 35 ns + 30% [210+440]
    =35 ns +195 ns
    =230 ns.

    14. [Ans. *] Range: 87.5 to 87.5


    ag
    Ref string 7 5 3 2 1 0 4 1 6 7 4 2 0 1 3 5
    F F F F F F F H F F H F F F F F
    0 7 1 2 5
    1 5 0 7 1
    2 3 4 3
    3 2 6 0
    ag a a
    = 87.5%

    15. [Ans. *] Range: 99.99 to 99.99


    n
    n
    n
    n
    n n n
    H = 99.99%

    16. [Ans. *] Range: 127.50 to 127.50


    Main memory size = 16 Mbytes
    Cache = 128 byte,
    Page size = 8 words, each word = 48.

    ag n a
    Ref string 0 1 2 3 0 1 2 4 0 1 2 3 0 1 2 4
    H H H H H H H F F H H H H H H F
    0 4 0
    1
    2
    3

    : 080-617 66 222, [email protected] ©Copyright reserved. Web:www.thegateacademy.com 4


    Chapter Test COA

    =75% (40 ns) + 25% (40+350)


    =30 ns +97.5
    =127.50ns

    17. [Ans. *] Range: 87.50 to 87.50

    = Second main memory access


    = main memory access time
    n
    n n n
    H = 87.50

    18. [Ans. *] Range: 2.12 to 2.12


    Average memory access time = Hit time +miss rate miss penalty
    Miss penalty = Hit time +miss rate miss penalty

    v ag a
    AMAT = 2.12 cycles

    19. [Ans. A]

    20. [Ans. *] Range: 1 to 1


    Cache
    0 0 0, 11, 4, 14, 9, 1, 8, 0
    1 9
    2 14
    3 11
    N=4
    No. of conflict miss = 1
    Block number ‘ ’ is mapped to block zero. Even though empty blocks are there in cache (The
    Direct Mapping).

    : 080-617 66 222, [email protected] ©Copyright reserved. Web:www.thegateacademy.com 5

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