Statistical Static Timing Analysis:

How simple can we get?

Chirayu Amin†, Noel Menezes*,
Kip Killpack*, Florentin Dartu*,
Umakanta Choudhury*, Nagib Hakim*,
Yehea Ismail†
†ECE Department * IntelCorporation,
Northwestern University Hillsboro, OR 97124, USA
Evanston, IL 60208, USA
Outline
„ Introduction
„ Process Variation Model
„ Distributions
„ Cell-library characterization
„ Methodology
„ Path-based
„ Add/Max Operations
„ Results
„ Conclusions

2
Variations and their impact
Probability(rank ≤ 50)
„ Sources of Timing Variations 1
„ Channel Length
„ Dopant Atom Count 0.8
„ Oxide Thickness
Critical path # 190
„ Dielectric Thickness 0.6
will be in top 50 paths
„ Vcc on 10% of the dies!
„ Temperature 0.4
„ Influence
„ Performance yield prediction 0.2

„ Optimization
0
„ Design convergence 0 100 200 300
Path Rank
„ Management (traditional) (from deterministic timing analysis)
„ ‘Corner’ based analysis 90 nm microprocessor block
„ Sub-optimum

3
Recent solutions
„ Categories
„ Block-based pdf propagation
„ Non-incremental
„ Incremental
„ Path-based pdf propagation
„ Bound calculation
„ Generic path analysis
„ Complexity
„ Non-gaussian pdf propagation
„ Statistical MAX operation
„ Correlations
„ Reconvergence

4
Factors influencing solutions
„ Predicting performance yield or optimizing
circuit?
„ Underlying process characteristics
„ How significant are the variation sources?
„ How significant is each component?
„ Die-to-die / Within-die
„ Channel length, Threshold voltage, etc
„ Architecuture and Layout
„ Number of stages between flip-flops
„ Spatial arrangement of gates

5
SSTA targets
„ Performance yield optimization
„ Die-to-die effects are more important
„ Can be handled using a different
methodology
„ Design convergence
„ Affected primarily by within-die effects
„ Gate’s delay w.r.t. others’ on the same die
Presented
Presented work
work addresses
addresses design
design convergence
convergence
6
Outline
„ Introduction
„ Process Variation Model
„ Distributions
„ Cell-library characterization
„ Methodology
„ Path-based
„ Add/Max Operations
„ Results
„ Conclusions

7
 Modeling variations
„ Only within-die effects considered

Variations

Channel Length (le) Threshold Voltage (vt)

Correlated or Systematic (les) Uncorrelated or Random (vtr)

Uncorrelated or Random (ler) vt=vtnom+vtr
le=lenom+les+ler

Main
Main variations
variations affecting
affecting delay: le and
delay: le and vt
vt
8
Parameter distributions
„ Gaussian distributions for les, ler, vtr
„ Characterized by σles, σler, σvtr

„ Systematic variation for les

„ Correlation is a function of distance
* 1 *
j Die
ρ (d)
i ρij =ρ (dij)
0 mm
d 9
*[16] S. Samaan, ICCAD ‘04
Cell-library characterization
„ Simulations similar as for deterministic STA
„ Plus extra simulations for measuring ∆delay

Gate
CL
tt
delay = delaynom(lenom,tt,CL)
+ ∆ delayles(les,tt,CL) + ∆ delayler(ler,tt,CL) + ∆ delayvtr(vtr,tt,CL)
effects of variations on delay
σ 2delay = σ 2delay,les(σ 2les,tt,CL) + σ 2
delay,ler (σ ler,tt,CL)
2 + σ 2delay,vtr (σ2vtr,tt,CL)

Overall
Overall delay
delay variance
variance is
is the
the sum
sum of
of variances
variances due
due to less,, le
to le lerr,, and
and vtvtrr
10
 Measuring σdelay
„ Characterization of σdelay,les
„ Vary le similarly for all transistors in the cell (ρ=1)
„ Measure delay change for each input to output arc
„ Characterization of σdelay,ler and σdelay,vtr
„ Sample using Monte Carlo method
„ Each transistor sampled independently
„ Measure delay change for each input to output arc

11
Outline
„ Introduction
„ Process Variation Model
„ Distributions
„ Cell-library characterization
„ Methodology
„ Path-based
„ Add/Max Operations
„ Results
„ Conclusions

12
Variation effects on a path
„ Systematic variations
„ Additive effect
„ (σ/µ)path-delay= (σ/µ)cell-delay
„ Spatial effect
„ Paths close together have very similar delay variation
„ Random variations
„ Cancellation effect
„ Variations die out as long as there are enough stages
„ (σ/µ)path-delay= (1/sqrt(n))*(σ/µ)cell-delay
„ ITRS projections: n~12 stages

13
Paths converging on a flip-flop

„ Distribution of delay for each path known

„ From simple path-based analysis
„ Distribution of overall margin at flip-flop?
„ Statistical MAX operation!
14
 Statistical MAX operation
1 Non-overlapping 3 Highly correlated, overlapping,
different sigmas
P1 P2
P2 P1

µ1 µ2 x1 µ1 x2 µ2 y2 y1

MAX is trivial, MAX is non-trivial, but

and situations observed on circuits situations not observed on circuits
Highly correlated, overlapping,
2 comparable sigmas 4 Random, overlapping

P1 P2

P1

P2

x1 y1 x2 y2 x1 µ1 y2 y1 µ2 x2
Comments about MAX

„ Path-delays are highly

correlated
„ Sigmas are similar
„ Random components
die out due to depth

No
No need
need for
for aa complicated
complicated MAX
MAX operation!!
operation!!

16
 Path-based SSTA methodology
Main Idea
Calculate the timing-margin distribution, for each path ending
at a flip-flop or a primary output (PO)

Clock-data path CGD

Typical path- Generating Sampling

based Flop Logic Logic
Flop
analysis Cell Cell

Clock buffers

clock
grid Clock sample path CS
17
 Calculating margin distribution
margin = tcs + T - t*CGD *includes tsetup
σ 2margin=σ 2CS +σ 2CGD - 2⋅ cov(tCS,tCGD)
path CGD
„ σCS – delay sigma for path CS
„ σCGD – delay sigma for path CGD
„ cov(tCS,tCGD) – covariance
between delays of CS and CGD
clock grid
path CS

Above analysis requires calculating delay variances and

covariances for paths Æ Statistical ADD operation
18
 Statistical ADD
„ Path delay variance is the sum of delay
variances due to les, ler, and vtr
σ 2path-delay = σ 2path-delay,les + σ 2
path-delay,ler + σ 2path-delay,vtr

Uncorrelated or Random Correlated or Systematic

Components Component
n
σ path
2
− delay ,ler = ∑ i,ler
σ 2
n n
i =1 σ 2
path − delay ,les = ∑σ 2
i ,les ∑ ij j ,les
ρ σ 2

n i =1 j =1

σ path
2
− delay ,vtr = ∑ i ,vtr
σ
i =1
2

19
Path-delay covariance
„ Easy to calculate based on pair-wise
covariances between individual gates

Gate i

ρij
Path 1
Path 2
Gate j

σ p1 , p 2 = ∑ ∑ cov(celli , cell j ) = ∑ ∑ ρ ijσ les ,iσ les , j

i∈ p1 j∈ p 2 i∈ p1 j∈ p 2

20
Outline
„ Introduction
„ Process Variation Model
„ Distributions
„ Cell-library characterization
„ Methodology
„ Path-based
„ Add/Max Operations
„ Results
„ Conclusions

21
Results
„ Methodology applied to a large microprocessor block
„ More than 100K cells
„ 90 nm technology
„ Fully extracted parasitics
„ Block-based (BFS) analysis to identify top N critical
end-nodes (flop inputs, POs)
„ Critical paths identified by back-tracking
„ Path-based SSTA performed on the critical paths
„ Comparison with Monte Carlo Analysis

22
Monte Carlo
*
„ 600 dies (profiles) for
varying les, ler, and vtr
„ Number depends on les
correlation distance,
block size, etc
„ Full block-based *
analysis (BFS)
„ Not just on critical paths
„ Deterministic STA on ler and vtr
each of the generated
600 dies

*[16] S. Samaan, ICCAD ‘04

23
Comparison with Monte Carlo
0.7

(data for top 492 end-nodes)

Path-based Margin Sigma

0.6

0.5

0.4

0.3

0.2

0.1

0
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7
Monte Carlo Margin Sigma
Good
Good correlation
correlation with
with Monte
Monte Carlo
Carlo Results!
Results! 24
Analysis
„ Error in predicting sigma
„ Maximum: 0.066 FO4 delay
„ Average: 0.19% of the path delay
„ Monte Carlo showed that distributions of
margins are Gaussian
„ No need for more complex distributions
„ At each end-node
„ Only one or two paths were clearly showing up as worst
paths on 80% of Monte Carlo samples
„ Relative ordering of paths ending up at a node does not
change

25
Outline
„ Introduction
„ Process Variation Model
„ Distributions
„ Cell-library characterization
„ Methodology
„ Path-based
„ Add/Max Operations
„ Results
„ Conclusions

26
Conclusions
„ Statistical timing is important
„ Simple path-based algorithm is
adequate
„ Justified based on design, variation profiles
„ Distributions are Gaussian
„ Errors in estimating sigma are
acceptable

27
Q&A