Practice 10:

Ratioed Logic

Digital Electronic Circuits – Semester A 2012

Ratioed vs. Non-Ratioed
 Standard CMOS is a non-Ratioed logic family, because:
 The logic function will be correctly implemented
regardless of device sizing.
 Device sizing will only affect the performance of the gate.

 A Ratioed gate is a circuit:

 That will only function properly if a certain ratio is
maintained between the drive strengths of its
components.
 If the required ratio is not met, the gate’s output may be
incorrect, the noise margins may become negative, or it
may lose its regenerative property.

2 Practice 10: Ratioed Logic February 15, 2018

Why use ratioed circuits?
 Historically, before CMOS technology was available, it was
hard to implement non-ratioed logic.

 Today, many techniques require ratioed circuits

 Such as SRAM design.
 Pseudo-nMOS is a ratioed logic family that requires less
transistors than CMOS and can optimize one transition.

3 Practice 10: Ratioed Logic February 15, 2018

Exercise 1: Pseudo nMOS
Exercise 1a
 For a pseudo-nMOS inverter with: VTn  VTp  0.4V VDSAT  VDD
 A. Draw the gate’s VTC and kn'  115 k p'  30  p  n  0.1
compute noise margins.

 Starting with Vin=0:

 M1 is cut-off
 M2 is in linear

VOH max  VDD  2.5V

5 Practice 10: Ratioed Logic February 15, 2018

 VTn  VTp  0.4V VDSAT  VDD
Exercise 1a kn'  115 k p'  30  p  n  0.1

 Raising Vin, M1 turns on in Saturation,

while M2 is still linear:
I SDp  lin   I DSn  sat 
 
Wp W
 VSGp  VTp VSDp  0.5VSDp
2 
 kn' n VGSn  VTn  1  nVDSn 
' 2
k
Lp  
p
2 Ln

k p  VDD  VTp
  VDD  Vout   0.5 VDD  Vout  2
  r  k p Vin  VTn 2


Vout  VT  VDD  Vin 

2
 r VT  Vin 
2
kn  rk p
dVout
 1 
d V  VDD  Vin 
2
 r VT  Vin  
2

dVin dVin  T 
Vin VIL

VDD  VT
VIL  VT 
r  r  1
6 Practice 10: Ratioed Logic February 15, 2018
 VTn  VTp  0.4V VDSAT  VDD
Exercise 1a kn'  115 k p'  30  p  n  0.1

VDD  VT
VIL  VT 
r  r  1

kn  rk p
 Substituting values gives us:
0.5 4 1840
k p  30   60 kn  115   1840 r  30.666
0.25 0.25 60
VDD  VT 2.5  0.4
VIL  VT   0.4   0.467V
r  r  1 971.11
VOH min  0.4   2.5  0.467   30.666  0.467  0.4   2.4V
2 2

7 Practice 10: Ratioed Logic February 15, 2018

 VTn  VTp  0.4V VDSAT  VDD
Exercise 1a kn'  115 k p'  30  p  n  0.1

 As Vin rises, Vout drops, causing M1 to

enter linear and M2 to saturate:

I SDp  sat   I DSn  lin  kn  rk p

  1   pVSDp   kn'
Wp Wn
VGSn  VTn VDSn  0.5VDSn
2
k '
p VSGp  VTp 2

2 Lp Ln

k p VDD  VT   r  k p Vin  VT Vout  0.5Vout

2 2


1
Vout  Vin  VT   Vin  VT    DD T 

2 2
V V
r

8 Practice 10: Ratioed Logic February 15, 2018

 VTn  VTp  0.4V VDSAT  VDD
Exercise 1a kn'  115 k p'  30  p  n  0.1

1
Vout  Vin  VT   Vin  VT   VDD  VT 
2 2

 Differentiating, we find:
dVout d  1 2
 1  Vin  VT   Vin  VT   VDD  VT  
2

dVin Vin VIH

dVin  r 
2VDD  VT 5  0.4
VIH  VT   0.4   0.88V
3r 92
VOL max   0.88  0.4    0.88  0.4   0.0326  2.5  0.4   0.18V
2 2

9 Practice 10: Ratioed Logic February 15, 2018

 VTn  VTp  0.4V VDSAT  VDD
Exercise 1a kn'  115 k p'  30  p  n  0.1

 Finally, we will find VOLmin by setting

Vin=VDD=2.5V
 M1 is still in linear and M2 is still saturated
 The equation we found before is still relevant:

1
Vout  Vin  VT   Vin  VT   VDD  VT 
2 2

r
 1
VOL min V
in VDD
 r 
 VDD  VT  1  1     2.5  0.4  1  0.9674  0.0345V 

10 Practice 10: Ratioed Logic February 15, 2018

 VTn  VTp  0.4V VDSAT  VDD
Exercise 1a kn'  115 k p'  30  p  n  0.1

 Now we can draw the VTC and find the

Noise Margins
NM H  VOH min  VIH  2.4  0.88  1.55V
NM L  VIL  VOL max  0.467  0.18  0.28V VOH max  2.5V
VIL  0.467V
VOH min  2.4V
VIH  0.88V
VOL max  0.18
VOL min  0.0345V

11 Practice 10: Ratioed Logic February 15, 2018

 VTn  VTp  0.4V VDSAT  VDD
Exercise 1b kn'  115 k p'  30  p  n  0.1

 B. Find the power dissipation with high

and low inputs. How is this different than
CMOS?

I static  k p VDD  VTp  1   VDD  VOL min    165 A

1 2

2
PAV  I static VDD  412.5W

12 Practice 10: Ratioed Logic February 15, 2018

 VTn  VTp  0.4V VDSAT  VDD
Exercise 1c kn'  115 k p'  30  p  n  0.1

 C. Find the high-to-low propagation delay of

the gate, with an ideal step at the input.
 Assume a 10pF load is connected.
 Use the average current approximation, but
differentiate between currents in different
operating modes.
 At t<0,
 Vin=0,
 Vout=VOHmax=VDD

 At t=0, VinVDD, and the output starts to discharge:

 M1 – saturation
 M2 – linear

 This continues until:

 Vout=VSGP-VT=VDD-VT
13 Practice 10: Ratioed Logic February 15, 2018
 VTn  VTp  0.4V VDSAT  VDD
Exercise 1c kn'  115 k p'  30  p  n  0.1

 Therefore we will find the current at:

 t=0  M1:sat, M2:lin
 t=t1 (Vout=VDD-VT)  M1:sat, M2:lin
 t=tpd (Vout=VDD/2)  M1:lin, M2: lin

 t=0
VGTn  VDD  VT VDSn  VDD  SAT
kn
I DSn  VDD  VT  1  VDD   920  2.1 1   2.5   5mA
2 2

2
VGTp  VDD  VT VDSp  0  LIN
I SDp  0
14 Practice 10: Ratioed Logic February 15, 2018
 VTn  VTp  0.4V VDSAT  VDD
Exercise 1c kn'  115 k p'  30  p  n  0.1

 t=t1
VGTn  VDD VT
 pinch off
VDSn  VDD  VT

 VDD  VT  1   VDD  VT    920  2.1 1   2.1  4.9mA

kn 2 2
I DSn
2

VGTp  VDD  VT VDSp  VT  LIN

I SDp  k p VDD  VT VT  0.5VT2   60  2.1 0.4  0.5  0.42   45.6 A

15 Practice 10: Ratioed Logic February 15, 2018

 VTn  VTp  0.4V VDSAT  VDD
Exercise 1c kn'  115 k p'  30  p  n  0.1

 t=tpd
VGTn  VDD VT
 LIN
VDSn  VDD 2
 VDD  VDD  
2

I DSn  kn VDD  VT   0.5     1840  2.11.25  0.5 1.252   3.4mA

 2  2  

VGTp  VDD  VT
 LIN
VDSp  VDD 2

 VDD  VDD  
2

I SDp  k p VDD  VT   0.5     60  

  2.1 1.25  0.5  1.25 2
  110.6 A
 2  2  
16 Practice 10: Ratioed Logic February 15, 2018
 VTn  VTp  0.4V VDSAT  VDD
Exercise 1c kn'  115 k p'  30  p  n  0.1

I t0  I n 0  5mA I t1  I n1  I p1  4.9m  45.6  4.85mA

I tpd  I tpd ,n  I tpd , p  3.4m  110.6  3.29mA

 Calculate t1-0:
VDD  VDD  VT  10 p  0.4
 t1  0   CL   812 ps

0.5 I to  I t1  4.925m

 Calculate tpd-t1:

VDD  VT   VDD 2 10 p  0.85

 t pd  t1   CL   2ns

0.5 I t1  I t pd  4.07m

17 Practice 10: Ratioed Logic February 15, 2018