EE141-Fall 2010 Ratioed Logic

Digital Integrated
Circuits Resistive
VDD

Depletion
VDD VDD

PMOS
Load RL Load VT < 0 Load
VSS
F F F
In1 In1 In1
In2 PDN In2 PDN In2 PDN
In3 In3 In3

Lecture 18 VSS VSS VSS

(a) resistive load (b) depletion load NMOS (c) pseudo-NMOS
Ratioed and Pass
Transistor Logic
Goal: build gates faster/smaller than static
complementary CMOS
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Announcements Ratioed Logic

‰ Project #1 due Thursday ‰ Spend power for speed
ƒ Use pseudo nMOS NOR gates, not NAND gates

‰ Midterm 2: Thurs. Nov. 4th, 6:30- W

8:00pm, Location TBD

ƒ Review session time/day TBA W W W

‰ DC characteristics:
ƒ VOH = VDD
ƒ VOL depends on PMOS to NMOS ratio

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Pseudo-NMOS VTC
3.0

2.5

Ratioed Logic
2.0 W/Lp = 4

1.5
Vout [V]

W/Lp = 2
1.0

W/Lp = 0.5 W/Lp = 1

0.5

W/Lp = 0.25
0.0
0.0 0.5 1.0 1.5 2.0 2.5
Vin [V]

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 Ratioed Logic LE Ratioed Logic Pull-down Delay
‰ Rising and falling delays aren’t the same ‰ Think in terms of the current driving Cload
ƒ Calculate LE for the two edges separately
‰ When you have a conflict between currents
ƒ Available current is the difference between the two
ƒ In pseudo-nMOS case:
1 Rn

( )
R drive = R drive =
1 - 1
Rn Rp 1 - Rn
Rp
‰ For tpLH:
ƒ (Works because Rp >> Rn for good noise margin)
ƒ Cgate = WCG Cinv = (3/2)WCG LELH =

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Ratioed Logic LE (pull-down edge) Ratioed Logic LE (pull-down edge)

W
2W

W
W W W

‰ For tpHL (assuming Rsqp = 2Rsqn):

‰ What is LE for tpHL? ƒ Rgate = Rn/(1-Rn/Rp) = 2Rn Rinv = Rn
‰ Switch model would predict Reff = Rn||Rp
ƒ Cgate = WCG Cinv = 3WCG
ƒ Would that give the right answer for LE? ƒ LEHL =
‰ LE is lower than an inverter!
ƒ But have static power dissipation…
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Improved Loads (2)

Response on Falling Edge
1 VDD VDD
Rp
vo(t)/VDD vo(t)
M1 M2
Rp=Rn Rn ⋅ Rp
0.5
Rn C τ= ⋅C
Rp=2Rn
Rn + Rp
Out Out
Rp=4Rn
vo (t ) Rn ⎛ Rn ⎞ −t /τ A
Rp=∞ = + ⎜1 − ⎟e
VDD Rn + Rp ⎜⎝ Rn + Rp ⎟⎠
A F F_b
B
0
0 1 2 3 4 B
t
‰ Time constant is smaller, but it takes more VSS VSS
time to complete 50% VDD transient.
ƒ Rp actually takes some current away from Differential Cascode Voltage Switch Logic (DCVSL)
discharging C
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 DCVSL Example1 Example: AND Gate
B

A
B
F = AB

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NMOS-Only Logic

3.0
In
In

Pass-Transistor 1.5µ m/0.25 µm 2.0

Out

Voltage [V]
VDD x x
Out

Logic
0.5 µ m/0.25µ m
0.5µ m/0.25 µm 1.0

0.0
0 0.5 1 1.5 2
Time [ns]

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Pass-Transistor Logic NMOS-only Switch

B C = 2.5V C = 2.5 V
M2
Out A A = 2.5 V A = 2.5 V B
Switch Out
Inputs

Mn
B
Network B
B CL M1

VB does not pull up to 2.5V, but 2.5V -VTN

• N transistors
Threshold voltage loss causes
• No static consumption
static power consumption
NMOS has higher threshold than PMOS (body effect)
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NMOS Only Logic:
Level Restoring Transistor Pass Transistor Logic LE
VDD ‰ In CMOS, a “gate” is defined only when trace a
Level Restorer
VDD connection all the way back to a supply
Mr ƒ Otherwise don’t know what drive resistance really is
B
M2
A X
Mn Out
M1

• Advantage: Full Swing

• Restorer adds capacitance, takes away pull down current at X
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Restorer Sizing Pass Transistor Logic LE

3.0
•Upper limit on restorer size
•Pass-transistor pull-down
2.0 can have several transistors in
Voltage [V]

W/Lr =1.75/0.25
W/L r =1.50/0.25 stack
1.0

W/Lr =1.0/0.25 W/L r =1.25/0.25

0.0
0 100 200 300 400 500
Time [ps]

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Pass Transistor Logic LE Restoring Full Swing: CPL

‰ What is LE of “gate” shown below for A and B A
Pass-Transistor
inputs? A
B Network F
B
ƒ Hint: Can you answer this question with only the (a)
information shown below? A
A
Inverse
Pass-Transistor F
B
B Network

B B B B B B

A A A

B F=AB B F=A+B A F=A⊕ΒÝ

A A A
(b)

B F=AB B F=A+B A F=A⊕ΒÝ

AND/NAND OR/NOR EXOR/NEXOR

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CPL Level Restore RC Model of Transmission Gate

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Solution 2: Transmission Gate Pass-

Pass-Transistor Based Multiplexer
C
C S S
VDD
A B A B
VDD
S

C
C A
M2

S F
C = 2.5 V
M1
A = 2.5 V B
B
CL
S

C=0V
GND
In1 S S In2
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Resistance of Transmission Gate

Next Lecture
30 ‰ Dynamic Logic
2. 5 V
Rn Rn
Resistance, ohms

20 Rp
2.5 V Vou t

Rp
0V
10
R n || R p

0
0.0 1.0 2.0
Vou t , V

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