Reg. No.

B.E. / B.Tech. ( Full Time) DEGREE END SEMESTER EXAMINATIONS, APRIL / MAY 2014

ELECTRONICS AND COMMUNICATION ENGINEERING

Fourth Semester

EC8452 - OPERATIONAL AMPLIFIERS AND ANALOG INTEGRATED CIRCUITS.

( Regulations :2008)

Duration: 3 Hrs. Maximum Marks: 100

Answer All QuestionsVV

Part A V'- ^.\<- 10 X 2 = 20 Marks

//

1 . A certain o p - a m p has an o p e n - l o o p v o l t a g e gain o f 1 0 0 , 0 0 0 a n d a c o m m o n m o d e gain o f 0.25.

D e t e r m i n e t h e CMRR a n d express it in decibels. ^
2. List f o u r c o m m o n t y p e s of t y p i c a l o p - a m p packages.
3. D e t e r m i n e t h e gain of an n o n i n v e r t i n g a m p l i f i e r if t h e o p e n l o o p v o l t a g e gain o f t h e o p - a m p is 1 5 0 , 0 0 0
and t h e Ri a n d Rf a r e 100K a n d 4.7K respectively. \ *r -
4. W h a t is a precision rectifier?
5. Draw t h e circuit d i a g r a m f o r c u r r e n t t o v o l t a g e c o n v e r s i o n using o p e r a t i o n a l a m p l i f i e r .
6. The basic s t e p o f a 9 bit DAC is 10.3 m V . If 0 0 0 0 0 0 0 0 0 r e p r e s e n t s 0V, w h a t o u t p u t is p r o d u c e d if t h e
input is 1 0 1 1 0 1 1 0 1 ? z a + o + ( , 4 9 ; ^ V ' ^ - 3 6\ x 10.3- ir'^ y
7. W h a t \i t h V n u m f e e r o f c o m p a r a t o r s r e q u i r e d t o design an 10 bit Flash ADC. Vr—"*
8. H o w w i l l y o u use PLL as a A M d e m o d u l a t o r ?
9. Give t h e a d v a n t a g e o f SMPS o v e r linear v o l t a g e r e g u l a t o r .
10. W h a t is a t u n e d a m p l i f i e r ?

PartB 5 X 1 6 = 80 Marks
***

1 1 . (i). Define slew r a t e . Give t h e m e t h o d f o r i m p r o v i n g s l e w rate? (8)

(ii). Explain W i d l a r c u r r e n t s o u r c e a n d d e r i v e t h e e q u a t i o n f o r t h e s a m e . (8)

12. (a)(i). Design a n a d d e r circuit using a n o p - a m p t o get t h e o u t p u t expression as f o l l o w s

Vo = - ( 0 . 1 V 1 + V 2 + 1 0 V 3 ) . „ L ^ / O V
> ^ Zftl H
%i ^

(ii). You are p r o v i d e d w i t h 8 LEDs a n d o p - a m p s . Design a s y s t e m t o f i n d o u t t h e w a t e r level in t h e

o v e r h e a d t a n k , d e p e n d i n g u p o n t h e w a t e r level in t h e t a n k t h e LEDs s h o u l d g l o w . A s s u m e all
o t h e r r e q u i r e d relevant d e t a i l s . (4)

(iii). Give t h e i m p o r t a n t f e a t u r e s o f an i n s t r u m e n t a t i o n a m p l i f i e r . Explain h o w t h e gain o f a n

i n s t r u m e n t a t i o n a m p l i f i e r can be set by t h e gain s e t t i n g resistor RG (8)

(OR)

P.T.O
 A

\ -
• f t

12(b)(i).With a n e a t d i a g r a m explain t h e w o r k f c g of i n v e r t i n g S c h m i t t t r i g g e r . Give its a p p l i c a t i o n . " (8)

(ii) .You are p r o v i d e d w i t h a (0-10)V a n a l o g V o l t m e t e r , o p e r a t i o n a l a m p l i f i e r a n d a t e m p e r a t u r e sensor

(linear) w h i c h gives 35 m V f o r e v e r y c h a n g e in degree c e n t i g r a d e . Design a s y s t e m t o m e a s u r e a n d
display t h e t e m p e r a t u r e f r o m (0-100) d e g r e e c e n t i g r a d e . A s s u m e all o t h e r r e l e v a n t details. (4)

(iii) . Derive t h e o u t p u t e q u a t i o n o f t h e o p - a m p based i n t e g r a t o r . (4)

13.(a)(i).Briefly explain t h e w o r k i n g of V o l t a g e c o n t r o l l e d oscillator. Give its o u t p u t e q u a t i o n . (8)

(ii) . W i t h a neat d i a g r a m e x p l a i n t h e c o n s t r u c t i o n of f r e q u e n c y synthesizer using PLL. (4)

(iii) . Briefly explain t h e r e l a t i o n s h i p b e t w e e n c a p t u r e range a n d lock range r e l a t i o n s h i p in PLL. (4)

(OR)

13.(b). W i t h a n e a t d i a g r a m e x p l a i n t h e w o r k i n g f o u r q u a d r a n t variable t r a n s c o n d u c t a n c e m u l t i p l i e r .
Derive t h e expression f o r t h e s a m e a n d give its various c o n d i t i o n o f o p e r a t i o n . (16)

14.(a) (i). Explain t h e w o r k i n g o f sample a n d h o l d IC. (8)

(ii). A d u a l slope ADC uses a 16-bit c o u n t e r a n d a 4 M H z clock r a t e . The m a x i m u m i n p u t v o l t a g e is

+10V. The m a x i m u m i n t e g r a t o r o u t p u t v o l t a g e s h o u l d be -8V w h e n t h e c o u n t e r has cycled
t h r o u g h 2 c o u n t s . The c a p a c i t o r used in t h e i n t e g r a t o r is 0.1u.F. Find t h e value o f t h e resistor
n

R of t h e i n t e g r a t o r . (8)

^-'^ ^ c TP (OR)
4, f
7. w

14.(b).(i). W i t h a n e a t d i a g r a m e x p l a i n t h e w o r k i n g o f Successive a p p r o x i m a t i o n ADC. (8)

(ii). W i t h a neat d i a g r a m e x p l a i n t h e w o r k i n g o f R-2R ladder DAC. (8)

15.(a). Briefly explain t h e design a n d w o r k i n g of Switch m o d e p o w e r supply. (16)

(OR)

15.(b)(i). D r a w a n d explain t h e a u d i o p o w e r a m p l i f i e r . Design an i n t e r c o m s y s t e m using t h e s a m e . (8)

(ii). Design a 555IC based s y s t e m t o r e p e a t e d l y t o g g l e an LED w i t h a p p r o x i m a t e l y 1 second O N t i m e

and 2 seconds OFF t i m e . A s s u m e all o t h e r r e q u i r e d d e t a i l s . (8)