Built-in Self-Calibration of On-chip DAC and ADC

Wei Jiang and Vishwani D. Agrawal

Electrical and Computer Engineering, Auburn University, Auburn, AL 36849
[email protected], [email protected]

Abstract—Linearity measurements are significant for assessing

D IG ITA L LO G IC
the performance of a modern mixed-signal system-on-chip. In
this paper a new built-in self-test (BIST) scheme is presented
for testing and calibration of on-chip high-resolution digital-
to-analog converters (DACs) and analog-to-digital converters
(ADCs) for better linearity using sigma-delta modulator and ADC LO G IC DAC
low-resolution dithering DAC. Ramp signals are used as testing B IST
stimuli and responses of DAC-under-test (DUT) are measured by C O N TR O L
a first-order 1-bit sigma-delta modulator with high oversampling
rate (OSR) and a low-pass digital filter for noise cancellation. A
polynomial fit algorithm is used to characterize DAC and to
obtain calibrating coefficients that determine whether the DUT
passes or fails the test. DUT output error is compensated for by a
dithering DAC with dynamic element matching (DEM) technique, Fig. 1. A typical BIST architecture for SoC with DAC and ADC.
which is controlled by the calibrating coefficients, to reduce the
integral non-linearity (INL) error. Simulation results show that
a sigma-delta modulator with effective number of bits (ENOB)
equivalent to 17-bit ADC and a 6-bit low-cost dithering DAC are still challenging and expensive to implement and to ap-
are sufficient to calibrate a 14-bit high-resolution on-chip DAC ply for production manufacturing, especially for high-speed
such that the maximum INL error is reduced from 3 LSB to devices. Automatic test equipment (ATE) for mixed-signal
approximate 0.25 LSB. Testing and calibration of on-chip ADC ICs is limited and costly, time for test is lengthy and test
using the same scheme is also discussed. process is inefficient partly because limited access and test
Index Terms—BIST, Self-Calibration, Mixed-Signal Circuits,
Sigma-Delta Modulator, ADC, DAC, SoC capability is provided by the external equipment. As mixed-
signal components play more and more important roles in
I. I NTRODUCTION digital SoC, testing for analog circuits becomes much more
With the rapid advancement in semiconductor technologies, difficult. Built-in-self-test (BIST) has been adopted to test
system-on-a-chip (SoC) is widely used in integrated-circuit digital circuits for a long time and many recent studies show
(IC) industry. The new technologies make it possible to build that BIST is also an ideal solution to test these converters.
complicated but low cost devices with lower power consump- The major challenge in developing a BIST scheme for a
tion and higher density of gates than before. Growing functions mixed-signal design is generation of accurate stimulus and
and gate density also require single IC to handle not only measurement of response from CUT. BIST must be capable
digital logic but also analog signals that were conventionally of on-chip stimulus generation and usually higher-resolution
kept on stand-alone chips. According to a recent report [10], devices are required to measure results. BIST circuitry has
global shipments of analog and mixed-signal ICs were $31.7 to be more accurate and faster than CUT and these factors
billion in 2005, increased to $37 billion in 2006, and may hit increase difficulties in implementation. To keep controllability
$67.8 billion by 2011. and observability of CUT, BIST must also work in various
Design-for-testability (DFT) architectures in mixed-signal environments and applications.
systems are widely studied. Sometimes, techniques for digital Sigma-delta modulators [13] have high-linearity and require
components can be used to test the analog components [5], only a low-resolution DAC to achieve much higher precision
[9], [16], [17]. High-resolution ADCs and DACs are among by oversampling and noise-shaping techniques. They are easy
the most basic parts on a mixed-signal chip and usually to design and implement and require little efforts to fine
their accuracy could determine the overall performance of tune for high linearity and resolution. With digital stimulus
the entire system. Analog signals are transformed into digital generation, sigma-delta technique is a promising solution for
signals before being fed to digital components and processors. testing high-resolution on-chip DAC at low cost and overhead.
Therefore, linearity and other characteristics of DAC become
II. BIST S OLUTIONS
a bottleneck for system performance and precision.
While design-for-testability (DFT) studies for digital circuit There were many well-studied BIST approaches proposed
are progressing, similar techniques for analog components for mixed-signal circuits, typically shown as in Figure. 1. A
Paper 32.2 INTERNATIONAL TEST CONFERENCE 1
1-4244-4203-0/08/$20.00 2008
c IEEE
sigma-delta modulation based BIST scheme was presented BIST scheme in which we introduce an additional low-cost
for mixed-signal circuits in [4]. Oversampling sigma-delta low-resolution dithering DAC to test and calibrate on-chip
modulation was employed for both stimulus generation and high-resolution DAC, and then use the calibrated high-linearity
response analysis to achieve high-quality stimuli and measure- DAC to test and calibrate the on-chip high-resolution ADC.
ment without stringent hardware requirement. This approach Such testing method is an efficient approach [20] to test both
also requires higher-resolution stimuli generator and multi-bit on-chip DAC and ADC.
digital streams to measure the function (approximately 6dB per The test and calibration processes begin with on-chip DAC,
bit). A software based multi-bit sigma-delta encoder is used as soon as the chip is powered up. When BIST is done the
to compensate for DAC imperfections. The approach depends two converters have been fine-tuned to achieve high-linearity.
on software to complete the BIST and compensation and its Only digital stimuli are required in the BIST process and
performance is a concern. The existence of multiple sigma- responses from DAC are converted to digital form by a sigma-
delta modulator in this approach is another concern, which delta modulator before being analyzed and characterized. The
may increase the design complexity and overhead of BIST same digital stimuli are used to generate linear ramp signals in
circuit. analog waveform by on-chip DAC, which has been calibrated
Lee et al. [8] proposed a sigma-delta modulation based in the previous step, for testing on-chip ADC and the response
BIST scheme to concurrently generate analog sinusoidal test of ADC is then analyzed and characterized as well. Thus,
stimuli and digital sinusoidal reference signals. CUT is sup- expensive analog signal generation and analysis are avoided
plied the analog stimuli and then four key parameters of ADC, by the use of the digital BIST circuitry, which is easier
namely, offset error, gain error, integral nonlinearity error to design and manufacture. The loop-back link connecting
and differential nonlinearity error, are measured against digital internal DAC and ADC only exists during BIST process. The
reference based on sinusoidal histogram of ADC output. This overall overhead is minimal because major components of the
approach can provide high accuracy and low chip area over- BIST scheme are a first-order 1-bit sigma-delta modulator, a
head for 8-bit ADCs. But for testing higher-resolution ADC, it low-resolution dithering DAC and a few binary computational
may be difficult to produce analog and digital signals simulta- units.
neously and sigma-delta modulator would require more clock
cycles leading to a reduce overall performance. The histogram III. BACKGROUND
method used in the scheme also requires much larger overhead
for additional memory space for storing data. Ong et al. [12] A. Linearity of Converters
give a second-order delta-sigma modulator based mixed-signal For both DAC and ADC, the minimum measurement unit is
BIST architecture capable of testing/characterizing itself using least significant bit (LSB) that is the average voltage increment
all digital stimulus. Test time of the architecture is shorter than for each digital code recognized by the converters. An LSB
the static linear ramp testing. However, it heavily depends on for N-bit converter is defined as
DSP processor for generating digital stimulus, filtering the
ν2N −1 − ν0
results from delta-sigma modulator, performing fast Fourier LSB = (1)
transform (FFT) and characterizing the modulator. 2N − 1
Histogram methods are also often used in some BIST where n = 2N − 1 is the number of such increments in total,
schemes for DAC/ADC. Wang et al. [18] present a low-cost ν0 and ν2N −1 are the two boundary analog value produced by
BIST based on linear histogram for testing on-chip ADC the converters.
with parallel time decomposition technique to minimize area High linearity is required by both DAC and ADC to produce
overhead and test time. Several authors [7], [19] use dithering high-resolution and accurate outputs. The linearity can be
techniques to obtain precise analog signals for high quality measured and characterized by specifications like differential
stimuli generation. non-linearity (DNL) and integral non-linearity (INL) [1]. For
As some previous papers indicate, an interdependence dead- each DAC input k, DNL is the incremental error between
lock exists in BIST schemes for DAC/ADC pair. On-chip BIST two consecutive codes k and k + 1, and INL is the difference
circuitry has to generate two stimuli, one of which is a digital between linear fit line and actual DAC output. From these
signal for DAC and the other is an analog waveform for ADC. definitions, DNL and INL for code k are as follows:
Output response produced by DAC requires verification from
ADC, and vice versa for ADC output response. Both DAC νk+1 − νk
DNLk = −1 (2)
and ADC need to be tested and verified by each other without LSB
νk − ν0
additional components or external ATE devices, and thus the INLk = −k (3)
LSB
results are unreliable. To break the deadlock while keeping the
design cost low, additional on-chip components to generate where νk is the analog value associated with code k. INL0 and
precise stimuli and to analyze the responses must exist. INLn−1 are both 0 as defined in (3). The overall DNL and INL
In this paper, we propose a sigma-delta modulator based are the maximum values of DNL and INL for each code k,

Paper 32.2 INTERNATIONAL TEST CONFERENCE 2

 S0 S1 S2 S3
O u tp ut

The input x is assumed to be a cosine waveform to relate the

four coefficients to harmonic distortion,
x = A · cos(ω t) (7)
y = c0 + c1 cos(ω t) + c2 cos(2ω t) + c3 cos(3ω t) (8)
where c0 , c1 , c2 , and c3 represent DC offset, gain, and 2nd and
0
Input 3rd harmonic distortions, respectively.
We assume the following four syndromes from combination
of sums:
B0 = S3 + S2 + S1 + S0 (9)
B1 = S3 + S2 − S1 − S0 (10)
B2 = S3 − S2 − S1 + S0 (11)
B3 = S3 − 3S2 + 3S1 − S0 (12)

Fig. 2. A typical best fit curve for transfer function of DAC. One can derive [15] four coefficients for the best fit polynomial
from the syndromes:
 
1 4
defined as b0 = B0 − B2 (13)
N 3
DNL = max {|DNLk |} (4)
 
4 4
k b1 = B1 − B3 (14)
INL = max {|INLk |} (5) N ·n 3
k 16
b2 = · B2 (15)
DNL and INL are usually calculated from the output of N · n2
DAC as in (2) and (3). Because DNLk can always be obtained 128
b3 = · B3 (16)
by differentiating the INLk , only INL measurements will be 3 · N · n3
discussed in the following section. The characteristics of converters are derived from the syn-
B. Third-Order Fitting Algorithm dromes as well:
B0
When histogram methods are used to test DAC and ADC c0 ≈ Offset (17)
n
to obtain DNL and INL figures, we require a huge amount 4B1
of memory for storing results in such BIST schemes. Sunter c1 ≈ Gain (18)
N ·n
and Nagi [15] proposed a simplified 3rd -order polynomial- B2
fitting algorithm for DAC and ADC BIST. Another paper [14] c2 ≈ 2nd harmonic (19)
B1
employed an algorithm to build a high accuracy stimulus 2B3
generator for ADC BIST. It is shown in these papers that c3 ≈ 3rd harmonic (20)
3B1
the four coefficients of a third-order polynomial that best fits
where N is the total number of samples and n is the range
the transfer function of DAC/ADC are mathematically related
of the converter (A = n/2, n = 2N ). The approximated equa-
to four key performance parameters, namely, offset, gain, and
tions are accurate if the number of samples is large enough
second and third order harmonic distortions. This solution,
(typically greater than 1000, i.e., equals or exceeds 10 bits).
claimed to be general, can be applied to various DAC/ADC
This solution is important because it provides a simple
devices, such as flash converters, delta-sigma converters and
method to determine the characteristics of converters and to
other analog circuits between DAC and ADC. Being mathe-
estimate the analog value for each code by a best-fitting
matically equivalent to the least-square fit it can produce the
3rd -order polynomial equation. By evaluation the harmonic
best unbiased (linear) estimates for the coefficients by feeding
coefficients that are calculated by accumulating samples of
converter with a linear ramp test stimulus covering the full
each segment, this technique allow us to quickly identify INL
range of conversion. The converter may work at full speed to
figures and determine whether or not the converter fails the
traverse the ramp stimulus and the output results are sampled
test. Furthermore, the coefficients give us a general idea of
by a measuring device. The full range of conversion is divided
actual linearity of the converter-under-test.
into four equal interval segments, as shown in Figure 2. The
In this paper, we apply a similar 3rd -order polynomial
samples at each segment are accumulated and the four sums
algorithm to evaluate INLk , the difference between linear
are S0 , S1 , S2 , and S3 . The general third-order polynomial
ideal value and the actual measurement for code k, rather
equation to fit converters is
than analyzing output measurement. Thus INL value for each
y = b0 + b1 x + b2 x2 + b3 x3 (6) digital code can be asserted immediately using the polynomial.

Paper 32.2 INTERNATIONAL TEST CONFERENCE 3

 ADC DAC

ADC P o ly n o m ia l DAC
F ix
u n d e r−te st u n d e r−te st

BIST
CONTROL
F ittin g c o e ffic ie n ts UNIT
P o ly n o m ia l Dithering
F ittin g DAC
Sigma−Delta LPF
d ig ita l
Modulator filte r
F ittin g c o e ffic ie n ts

DAC test outputs / Analog ramp signals for ADC test

Fig. 3. Proposed BIST scheme for test and calibration of DAC and ADC.

CLOCK
The limited range of INL magnitude makes it possible to
employ a low-resolution DAC to recover the INL value and x(t) y(t)
compensate for such error in a high-resolution on-chip DAC. S
IV. OVERVIEW OF P ROPOSED BIST S CHEME IN T E G R A T O R Q U A N T IZ A T IO N

Requirements for on-chip DAC and ADC in mixed-signal

SoC usually include resolution, linearity, and converting speed 1−bit DAC
at reasonable cost of design and manufacture. Converters with
higher performance may sharply increase the cost of produc-
tion, which depends on the design and process technology. The E (z)
proposed BIST scheme, as depicted in Figure 3, demonstrates X (z) Y (z)
−1
a feasible solution to achieve improved linearity using dynamic Z Q
compensation by a low-cost DAC without penalty on the
speed of operation. The BIST circuitry includes a measuring
ADC built from 1st -order 1-bit sigma-delta modulator, a low-
resolution dithering DAC, and some simple 3rd -order digital
Fig. 4. Principle of sigma-delta modulator and transfer function in z-domain.
function logic. A DSP-based BIST control logic provides the
core functionality of the scheme that generates test stimuli for
both on-chip DAC and ADC, gathers response from ADCs,
determines status of conversion and configures the dithering low-resolution DAC that do not have strict performance re-
DAC to calibrate the on-chip conversion to achieve higher quirements and therefore are easy to design and occupy small
linearity. chip area. The BIST circuitry itself is more fault-tolerant than
The sigma-delta modulator, shown in Figure 4 can achieve other mixed-signal parts due to less stringent requirements on
very high linearity through oversampling and noise shaping its operational performance.
techniques and it is inexpensive to design and manufac- Sometime following the system power up, the BIST cir-
ture [13]. The noise figure of this sigma-delta modulator is cuitry for DAC/ADC starts the test and calibration procedures.
basically 1-bit random quantization error that occurs during This can begin immediately upon completion of digital BIST
conversion of analog signals to digital signals. By oversam- which would have tested the digital components of the mixed-
pling and filtering, the signal-to-noise ratio (SNR) of such a signal chip. Loop-back interconnection between output of on-
modulator is increased to achieve a lower noise floor and wider chip DAC and input of two ADCs is established once the
dynamic range. Noise-shaping acts as a high-pass filter for the procedure begins and we keep the connection until the test is
quantization noise and thus further reduces the noise figure in completed.
the lower band, up to half of sampling frequency (Nyquist The on-chip DAC is tested first by test stimulus generated
frequency), further improving the SNR. by BIST control unit as consecutive digital codes covering the
The cost of the scheme is minimal, because only major full operating range with 2N codes for N-bit DAC. The output
overheads to the system are the sigma-delta modulator and response of DAC is sampled and converted by the sigma-delta

Paper 32.2 INTERNATIONAL TEST CONFERENCE 4

ADC to a digital code. Then, according to the least-square
fitting algorithm described above, the characteristics of DAC
is be obtained by calculating the four coefficients from an
DAC
accumulation of the digitalized responses. The four computed unde r−test
coefficients are compared to the pre-stored references in order BIST
to determine whether DAC passes or fails in terms of linearity.
CO N TRO L
A pass for DAC here means that the characteristics of the
DAC is in the predefined range within which a dithering DAC U N IT
LPF Sigm a−Delta
can be used to compensate its output for linearity. A fail for dig ita l
M odulator
filter
DAC means that the DAC cannot meet design requirements
according to the comparison results and is beyond the com-
pensating ability of the dithering DAC. If DAC passes the test,
a fitting curve of INL error using the calculated coefficients
can be obtained and DAC output can be determined as well as Fig. 5. Test circuitry of DAC.
the quantization error for each code introduced by DAC. The
INL and parameters for the quantization error are stored into
dithering DAC to generate proper compensation signal that calculate parameters that determine the performance of DAC
will be added into the output of the on-chip DAC to eliminate and control the dithering DAC for calibration. To test on-
the non-linearity. Since the value range of quantization error is chip DAC, as shown in Figure 5, BIST control unit generates
much narrower than the full range of DAC output, we can use a series of consecutive digital codes (corresponding analog
INL as the reference voltage for the dithering DAC to generate voltage νk ) from the lowest value (ν0 ) to the highest value
compensation signals with very fine granularity although the (νn−1 ) and uses sigma-delta modulator to sample the output
dithering DAC itself has low-resolution. For given on-chip of DAC (ν̂k ).
DAC and maximum INL error tolerance, the parameters of ν̂k = νk + qk + qˆk (21)
the sigma-delta modulator and resolution of dithering DAC
are determined. Typically, a 17-bit measuring ADC and a 6- where qk is the quantization error of the on-chip DAC and
bit dithering DAC are sufficient to calibrate a 14-bit DAC with qˆk that of sigma-delta ADC. k̂ is captured at the output of
maximum 3 LSB INL error. the sampling sigma-delta ADC for each input code k. For an
After on-chip DAC is tested and calibrated, BIST circuitry accurate measurement, k̂ must contain more effective number
then uses the calibrated DAC to test the on-chip ADC by again of bits (ENOB) than that in k. The ENOB of hatk is determined
feeding the same consecutive digital codes into DAC, trans- by the oversampling ratio K, and requires higher K to obtain
mitting analog signal output into the ADC input and, finally, larger ENOB and better resolution. Thus, the total quantization
reading conversion results from ADC. ADC is characterized error for each code k is
using the same fitting algorithm shown above and another set
of four coefficients is obtained to determine whether the ADC εk = ν̂k − νk = qk + qˆk (22)
passes or fails the test by comparing them to prespecified
coefficients. A 3rd -order best-fit curve can be obtained if INL qˆk is small enough to be ignored with high oversampling ratio
figures fall within the prespecified operational range. Then, K and thus the quantization error is mainly from the on-
INL error can be evaluated by the curve and removed from chip DAC. The dithering DAC will then eliminate εk from
ADC outputs to fix final digital codes. the DAC output for normal operation and output linearity
If both DAC and ADC pass tests and get calibrated by can be further improved by employing a dynamic element
their respective polynomial fit algorithms, the BIST procedure mismatching (DEM) technique. Because of large number of
is completed and therefore the internal connection between εk for each code k, (2N in total for N-bit DAC), it requires a
the output of the DAC and the input of ADC is eliminated huge amount of memory to store the compensation data for
and the sigma-delta modulator is disabled. The two sets of every code, thus the 3rd -order best fit algorithm shown above
coefficients calculated during BIST procedures are saved for is used to reduce memory consumption. On the other hand,
fitting polynomials to compensate the outputs in the normal the quantization error εk for each code k also satisfies the
operation. This compensation remains in effect until the circuit requirements for the polynomial fitting algorithm. Applying
is powered down. On subsequent power up the test and the fitting algorithm to INL error εk , rather than result ν̂k
calibration are again initiated. obtained from sigma-delta modulator as [15] proposed, will
make it easier for dithering DAC to generate compensation
V. T EST AND C ALIBRATION OF DAC signals. The consecutive codes from ν0 to νn−1 are divided
This section describes details of the proposed BIST scheme into four equal-size segments and quantization errors εk in
to generate digital stimulus, to measure DAC outputs and to each segment are summed up to get four fundamental sum

Paper 32.2 INTERNATIONAL TEST CONFERENCE 5

 250
values: st
1 −order
nd
2 −order
n/4−1 n/4−1 rd

∑ ∑
3 −order
S0 = εk = (ν̂k − νk ) (23)
k=0 k=0 200
n/2−1 n/2−1
S1 = ∑ εk = ∑ (ν̂k − νk ) (24)
k=n/4 k=n/4

SNR (dB)
3n/4−1 3n/4−1 150

S2 = ∑ εk = ∑ (ν̂k − νk ) (25)
k=n/2 k=n/2
n−1 n−1
∑ εk = ∑ (ν̂k − νk )
100
S3 = (26)
k=3n/4 k=3n/4

where n = 2N is the total value range for the N-bit on-

50
chip DAC. The syndromes and coefficients of the best fit 2
10 10
3 4
10
Oversampling ratio (OSR)
polynomial for ramp signal are calculate from these four
sum values using (9) through (12) and (13) through (16), Fig. 6. SNR vs. oversampling ratio (OSR) for sigma-delta modulator.
respectively. With these coefficients, representing offset, gain,
and 2nd and 3rd -order harmonic distortions by calculating
quantization error, we can construct a best fitting curve that a quantizer and a 1-bit DAC. Although higher order or
has least square error. We use (6) and (8) to replace the actual multi-bit sigma-delta modulators are faster and achieve higher
quantization errors by both DAC and sigma-delta ADC. To resolution, 1st -order 1-bit sigma-delta modulator is more stable
achieve even higher linearity of εk , the ENOB of sigma-delta and has better linearity [11]. Signal-noise-ratio (SNR) of
ADC shall be larger than number of bits in the DAC, usually at conventional N-bit DAC/ADC is calculated by:
least 3 more effective bits, though test time would be slightly  
RMS Signal
longer. The reference voltage of the dithering DAC can be SNR = 20 log
RMS Noise
the maximum INL error for the on-chip DAC in theory and
usually 3 LSB is used for this dithering range to guarantee the = 6.02N + 1.76 (27)
full compensation for a low quality on-chip DAC. Because of
The SNR is about 86dB for a 14-bit on-chip DAC and
spurious factor introduced by the dithering DAC to the final
the measuring ADC must be of higher resolution to attain
result of on-chip DAC, a low-pass filter must be used to filter
precision.
out any high frequency noise.
Since sigma-delta modulator has only 1-bit quantizer, the
A. Test Preparation signal to 1-bit quantization noise ratio is about 7.78dB as given
Digital components of SoC have their own BIST architec- by (27). Oversampling improves the overall SNR by using a
ture and all those parts are assume to have passed their tests much higher sampling frequency fs and distributing the white
before the proposed mixed-signal BIST scheme takes effect noise power over the range of the Nyquist frequency fs /2.
because the test and self-calibration procedures require digital Doubling the sampling frequency will decrease the in-band
control logic to generate digital code as test stimuli, measure quantization noise figure by 9dB for the first-order sigma-delta
ADC outputs and calculate parameters for the dithering DAC. modulator [2], i.e., 9dB per octave improvement for SNR. So
The digital BIST architecture is beyond the discussion of this we can estimate SNR of 1st -order 1-bit sigma-delta modulator
paper and may be found elsewhere [1]. After digital BIST is by its sampling frequency fs :
done, the proposed mixed-signal BIST scheme generates codes fs /2
for the on-chip DAC inputs in the form of a digitized ramp test SNR = 7.78 + 30 log10 (28)
f0
signal. Meanwhile, the dithering DAC is disabled and produces
no compensation signal for the on-chip DAC whose output is where f0 is the upper frequency or bandwidth of the input
measured by the 1st -order 1-bit sigma-delta modulator. Any signal and fs / f0 is defined as the oversampling ratio (OSR),
output from the on-chip ADC is not considered at this time as shown in Figure 6. If sampling frequency fs is much greater
because it will be tested only after the DAC test. than f0 , the total quantization noise will still be the same but
will be spread over a wider spectrum so that quantization noise
B. Sigma-Delta Modulator in signal band is significantly reduced.
A 1st -order 1-bit sigma-delta modulator is now used to The integrator in the sigma-delta modulator is also called
sample the on-chip DAC output. This provides a low-cost noise-shaping filter because it moves much of the quantization
measuring method with high linearity. As shown in Figure 4, noise to a higher band of frequencies such that a very low noise
the first order sigma-delta modulator consists of a integrator, figure is obtained in the band of interest. We can perform a

Paper 32.2 INTERNATIONAL TEST CONFERENCE 6

z-domain analysis as shown in Figure 4: or sometimes called sinc filter that will also eliminate the
unnecessary high frequency portions of the bit-stream. Ong
Y (z) = z−1U(z) + (1 − z−1 )E(z) (29) et al. [12] give an efficient implementation of a comb filter by
where E(z) is the z-domain transfer function of the quanti- cascading K stages of accumulators operating at the sampling
zation error e(k) introduced by 1-bit quantizer for code k. rate of the sigma-delta modulator, followed by K stages of
Equation (29) shows that the sigma-delta modulator acts as cascaded differentiators operating at the down-sampled rate.
a low-pass filter for the input signal and high-pass filter for The transfer function of the sinc filter with K stages and a
quantization error. Thus, the noise figure of the modulator down-sample ratio M has the form:
is shifted upwards to higher frequencies while the signals K
1 1 − z−M

remains at lower frequency. The sigma-delta modulator outputs H(z) = (32)
M 1 − z−1
a bit stream of 0s and 1s that contains all necessary information
with a frequency response:
from the on-chip DAC but needs filtering to eliminate high
1 sin(ω M/2)
 K
frequency noise and then conversion to digital data that could H e j ω  =


(33)
be processed and analyzed by the BIST control logic. M sin(ω /2)

C. Digital Filters The desired frequency components should be contained within

the first peak of the frequency response. We also observe
Since the oversampling technique distributes the overall that larger K yields larger attenuation to frequency response
quantization noise from bandwidth of f0 to fs /2 by the and larger M yields more and thinner peaks so proper K and
oversampling ratio fs / f0 and noise-shaping acts as a high- M should be chosen carefully to filter the desired frequency
pass filter for the quantization noise most which fall outside components to reconstruct the signal.
the signal passband, the digital filter is actually a low-pass
filter that eliminates the high frequency noise and keeps the D. Dithering DAC
low frequency signals. A deterministic dynamic element matching (DDEM) DAC
One simple method to implement the low-pass filter to is used to calibrate the on-chip DAC for even better linearity
extract signals is to use an accumulator that sums up the output because the DEM approach is able to provide high-resolution
bit-stream of the sigma-delta modulator. This accumulator acts DAC output using a low-resolution DAC, i.e., DDEM DAC
like a 1st − order low-pass filter with a z-domain transfer provides higher ENOB than its actual number of bits. The
function: outputs of both on-chip DAC and this dithering DAC are
1 combined together and serve as the final DAC output for
Y (z) = Y (z) (30) each input code of the normal operation. To eliminate the
1 − z−1
z−1 unexpected spurious frequencies generated from the dynamic
= U(z) + E(z) (31) matching mechanism, a low-pass filter must be used to process
1 − z−1
the combined DAC outputs and to remove aliasing distortion
Examining (31), we find that the signals in the bit-stream are
before transmitting the analog signal off chip. The calibration
extracted by the accumulator and the high frequency noise
method with dithering DAC is illustrated in Figure 3, which
shaped by sigma-delta modulator is very low in the band
consists of four major parts: digital 3rd -order function gener-
of interest and therefore almost eliminated. The remaining
ator for calculating dithering code from input code and four
noise in the accumulator output is only due to the 1-bit
fitting coefficients, DDEM DAC for converting dithering code
quantization error (1 LSB) while the signal is reinforced during
to analog dithering signal, and LPF to filter the final combined
accumulation to achieve much higher SNR.
signal.
The bit-stream generated by the sigma-delta modulator The input code k to digital 3rd -order function generator
requires a smoothing process called decimation that elimi- comes from the BIST control unit during self-testing step or
nates redundant output data by down-sampling the bit-stream normal DAC operation after test with N-bit width same as the
to reconstruct the input signal without distortion. A down- code to the on-chip DAC. The function generator calculates
sampling reduction ratio M means that the sampling rate of and outputs code k′ with N ′ -bit width for DDEM DAC which
the bit-stream is reduced by a factor M, equivalent to picking will in turn generate corresponding analog compensation sig-
up one of every M samples from the stream to reconstruct the nal to code k′ according to the four coefficients obtained from
input signal and discard the rest of the samples. No signal results of DAC BIST step using the best fitting algorithm
information will be lost during the down-sampling process discussed earlier. From equation (6), we get:
provided that decimation data rate is more than twice the signal
band width f0 . Digital filter using decimation will minimize ′ 2

2N ′
3
k = b0 + b1 k + b2 k + b3 k (34)
the requirements for a high speed parallel multiplier and a 2N
large memory to store every bit of the lengthy stream. A The newly generated compensation code k′ goes to DDEM
′
common implementation of such decimation is comb filter, DAC that consists of a total of 2N current sources for N ′ bit

Paper 32.2 INTERNATIONAL TEST CONFERENCE 7

DAC [6]. N ′ is much less than N and thus the N ′ -bit DAC alpha=1
alpha=2
10
5

22
is a low resolution converter. Let us define p as the DDEM alpha=3

Estimation resolution of Sigma−Delta modulator (bits)

Oversampling ratio (OSR) of Sigma−Delta modulator

iteration number, which represents the number of samples to
be generated for each DAC code k′ , and q = N/p as the
20

source element distance factor. A cyclic DDEM switching

18
scheme could be applied to the elements that DAC generates, 4
10
i.e., p samples of output for each input code k′ , by selecting
and switching k′ current sources such that the distance from 16

each other is q. DAC rotates the switches that control cur-

rent sources for one element clockwise after outputting each 14

sample, so for each input code all current sources are used
in certain output sample while always keeping k′ switched
3
10
12

sources to generate the desired total current. The output analog

0 1 2 3 4 5 6 7 8 9 10
signal is obtained in a load resistor driven by the total current Resolution of dithering DAC (bits)

from k′ rotating current sources. If the NOB of a DAC is N,

Fig. 7. Minimum oversampling ratio (OSR) of first-order sigma-delta
by this dynamic element matching scheme the DDEM DAC modulator, determined by resolution of dithering DAC, for a 14-bit on-chip
can achieve the performance comparable to an ideal DAC with DAC with various fault tolerance factors, (α ).
(N + log2 p)-bit resolution and the element mismatch is quite
tolerable so that minimum sized current elements are used and
the cost of manufacture is reduced. linear ramp signal for ADC test. During on-chip ADC test,
′
The reference voltage Vre f for the DDEM DAC is not the sigma-delta ADC is disabled and the BIST control unit
necessarily same as that of N-bit on-chip DAC Vre f . In fact, feeds ramp signals νk generated by DAC for consecutive
′
Vre f is much less than Vre f for a fine compensation of the DAC codes k into the ADC and obtain conversion results ν̂k at
output for better linearity. We have, the ADC output. Using a similar scheme as described in the
previous section, the best fit algorithm is used to process the
Vre f
VLSB = (35) quantization error ν̂k − νk and four coefficients are calculated
2N from the sum of four equally divided segments of all ramp
′ VLSB
Vre f = ±α · (36) codes. A digital function generator is used with these four
2
coefficients to calculate corrective number k − k̂ to fix the
where 2N is the total number of digital codes and α is a fault quantization error for each ADC output code k̂ corresponding
tolerance factor. α determines the maximum allowable INL to the analog signal ν̂k .
error in the on-chip DAC, i.e., the maximum deviation from an
ideal linear DAC output. A DAC with INL error no more than VII. S IMULATION R ESULTS
α /2-LSB will be considered “good” for calibration, otherwise,
The proposed testing and calibration approach is verified
the DAC will fail the test. Different values of α could be
by simulation in Matlab with a 14-bit on-chip DAC and ADC
assigned for different applications and to different SoCs to
model with various quantization noise levels. A 6-bit low-cost
satisfy varying requirements of fault tolerance. Greater fault
dithering DAC model is used in the simulation to generate the
tolerance factor α gives more tolerance to on-chip DAC but
compensating analog signal for DAC calibration. The fault
results in degraded linearity for the calibrated DAC.
tolerance factor is chosen 3 LSB, which is suitable for most
For a specified application and the corresponding factor α ,
kinds of DACs.
we make a tradeoff between the resolution of dithering DAC
and the OSR of sigma-delta modulator, as shown in Figure 7. To measure 14-bit DAC with 3 LSB fault tolerance and to
Higher the resolution of the dithering DAC, more complex require 0.25 LSB maximum INL error in the calibrated output,
will be the design. However, a low-resolution dithering DAC the sigma-delta modulator must have 17 bits of resolution
requires more SNR for the sigma-delta modulator and higher according to (37). From (27), SNR of this 17-bit ENOB sigma-
OSR, which takes more clock cycles to sample the DAC delta modulator is [3]:
output. Considering the tolerance factor α , LSB for N-bit on- SNR = 6.02ENOB + 1.76 = 104.1dB (38)
chip DAC and N ′ -bit dithering DAC, the minimum ENOB of
sigma-delta modulator is: We assume that the oversampling rate (OSR) for the mod-
′ ulator is M,
N̂ = N + N − α (37) fs /2 fs
M= = (39)
VI. T EST AND C ALIBRATION OF ADC f0 2 f0
After the DAC is tested and calibrated, it can be used as where fs is the sampling frequency of the modulator and f0 is
a precise analog test signal generator to generate a highly the upper signal frequency of the input signal. The SNR for

Paper 32.2 INTERNATIONAL TEST CONFERENCE 8

 1.5 1.5

Estimated INL (LSB)

1

1 0.5

−0.5
INL of 14−bit DAC (LSB)

0.5
−1

−1.5
0 0 2000 4000 6000 8000 10000 12000 14000 16000
Indices of 14−bit DAC−under−test

Estimated calibrating output (LSB)

−0.5 1.5

0.5
−1
0

−0.5
−1.5
0 2000 4000 6000 8000 10000 12000 14000 16000 −1
Indices of 14−bit DAC−under−test
−1.5
0 2000 4000 6000 8000 10000 12000 14000 16000
Indices of 14−bit DAC−under−test
Fig. 8. INL of simulated 14-bit DAC-under-test.

TABLE I Fig. 9. Least mean-square fit for third-order polynomial (top) and estimation
T HIRD - ORDER POLYNOMIAL FIT FOR INL OF F IGURE 8. error (bottom) for DAC-under-test INL data of Figure 8.

Sums Syndromes Coefficients

1.5
S0 = −0.4436 × 103 B0 = 9.0472 × 103 b0 = 0.7958
S1 = 1.5446 × 102 B1 = 6.8453 × 103 b1 = 1.9897 × 10−4 1
6−bit DAC INL

S2 = 4.4760 × 103 B2 = −2.9938 × 103 b2 = −1.0892 × 10−8 0.5

S3 = 3.4703 × 103 B3 = −4.8803 × 103 b3 = −2.8897 × 10−12 0

−0.5

−1

−1.5
the 1st -order sigma-delta modulator can be obtained as [13]: 0 10 20 30 40
Indices of 6−bit dithering DAC
50 60

π
 3/2
1 80
n0 = erms √ (40)
3 M
6−bit DAC output

60

1
SNR = √ (41) 40
n0 · 2 2
√ 3/2 20
3M
≈ √ (42)
2 2π
0
0 10 20 30 40 50 60
√ Indices of 6−bit dithering DAC

Assuming erms = 1, the input signal RMS value is 1/(2 2).

We get, Fig. 10. INL (top) of simulated 6-bit dithering DAC, and DAC outputs
√ !2/3
2 2π · SNR (bottom).
M= √ ≈ 8779 (43)
3
Thus we select 214 = 16384 as the OSR used in the sigma- B1 , B2 , and B4 from the sums. Finally, four coefficients, b0 ,
delta modulator, which is the closest value to satisfy 2n . b1 , b2 , and b3 , are obtained for the polynomial fitting curve in
OSR = 16384 is sufficient for the sampled data to be recovered Figure 9(a). Figure 9(b) shows about -39.3dB estimation error
from the 17-bit digital output and the quantization error of the for the fitting algorithm.
modulator can be omitted as compared to that of the on-chip Characteristics of a low-quality 6-bit dithering DAC are
DAC and dithering DAC. shown in Figure 10. The reference voltage of DAC is α /2,
Figure 8 depicts INL of a 14-bit DAC with maximum 1.4 typically, 1.5 LSB of DAC-under-test. Using a higher α ,
LSB quantization error from simulation. The maximum INL larger than 3 LSB, will provide large range of calibration and
magnitude is within a pre-defined range, e.g., 3 LSB in this therefore better fault-tolerance but less calibrating precision
case, so that this on-chip DAC could be calibrated. Otherwise, and worse linearity. On the other hand, using an α less than
if any INLk falls outside the specified range, the on-chip DAC 3 LSB will provide better calibration precision and better
would fail the test. linearity of outputs but worse fault-tolerance of DAC.
By dividing the INL figure into four segments of equal sizes, The final calibrated output of the 14-bit DAC-under-test us-
we obtain sums of elements for each segment: S0 , S1 , S2 and ing polynomial fitting curve is shown in Figure 11. Calibrating
S3 (shown in Table I). We then calculate four syndromes: B0 , signal is not as ideal as shown in Figure 9 and the estimation

Paper 32.2 INTERNATIONAL TEST CONFERENCE 9

 [4] J.-L. Huang and K.-T. Cheng, “A Sigma-Delta Modulation
1.5
Based BIST Scheme for Mixed-Signal Circuits,” in Proc. Asia
Estimated INL (LSB)

0.5 and South Pacific Design Automation Conf., Jan. 2000, pp. 605–
0 610.
−0.5 [5] R. Huertas, editor, Test and Design-for-Testibility in Mixed-
−1 Signal Integrated Circuits. Kluwer Academic Publishers, 2004.
−1.5 [6] H. Jiang, D. Chen, and R. L. Geiger, “Dither Incorporated
0 2000 4000 6000 8000 10000 12000 14000 16000
Indices of 14−bit calibrated DAC
Deterministic Dynamic Element Matching for High Resolution
1.5 ADC Test Using Extremely Low Resolution DACs,” in IEEE
Estimated DAC output (LSB)

1 International Symp. Circuits and Systems, May 2005, pp. 4285–

0.5
4288.
0
[7] L. Jin, H. Haggag, R. Geiger, and D. Chen, “Testing of Precision
−0.5
DACs Using Low-Resolution ADCs with Dithering,” in Proc.
−1
International Test Conf., 2006. Paper 13.1.
−1.5
0 2000 4000 6000 8000 10000 12000 14000 16000
Indices of 14−bit calibrated DAC
[8] K.-J. Lee, S.-J. Chang, and R.-S.Tzeng, “A Sigma-Delta Mod-
ulation Based BIST Scheme for A/D Converters,” in Proc. 12th
Asian Test Symp., 2003, pp. 124–127.
Fig. 11. INL (top) of calibrated 14-bit DAC-under-test using third-order
polynomial fit and 6-bit dithering DAC, and the corresponding estimated INL [9] R.-W. Liu, editor, Testing and Diagnosis of Analog Circuits and
error (bottom). Systems. Van Nostrand Reinhold, 1991.
[10] A. McWilliams, editor, Analog and Mixed Signal Devices:
Market Research Report. BCC, March 2007.
error is about -38.0dB. The INL of the calibrated DAC is not [11] I. Mehr and T. L. Sculley, “Oversampling Current Sample/Hold
larger than 0.25 LSB compared to an ideal DAC and is reduced Structure for Digital CMOS Process Implementation,” IEEE
from a maximum of 1.5 LSB in non-calibrated output. Trans. Circuits and Systems II: Analog and Digital Signal
Processing, vol. 45, no. 2, pp. 196–203, Feb. 1998.
VIII. C ONCLUSION [12] C.-K. Ong, K.-T. Cheng, and L.-C. Wang, “Delta-Sigma Modu-
A BIST scheme for testing and calibration of on-chip lator Based Mixed-Signal BIST Architecture for SoC,” in Proc.
DAC/ADC with a low-cost sigma-delta modulator and dither- Asia and South Pacific Design Automation Conf., Jan. 2003, pp.
ing DEM DAC is presented in this paper. A sigma-delta 669–674.
modulator with sufficient OSR for three or more bits of [13] J. Rogers, C. Plett, and F. Dai, Integrated Circuit Design for
resolution is used to sample the DAC output and a third- High-Speed Frequency Synthesis. Boston: Artech House, 2006.
order polynomial-fit algorithm is employed to characterize the [14] A. Roy, S. Sunter, A. Fudoli, and D. Appelo, “High Accuracy
Stimulus Generation for A/D Converter BIST,” in Proc. Inter-
DAC with four polynomial coefficients. Characteristics such
national Test Conf., 2002, pp. 1031–1039.
as offset, gain, and second-order and third-order harmonic
[15] S. Sunter and N. Nagi, “A Simplified Polynomial Fitting Al-
distortions are thus determined. The analog output of DAC is
gorithm for DAC and ADC BIST,” in Proc. International Test
calibrated for higher linearity by compensation signals from
Conf., 1997, pp. 389–395.
dithering DAC. Similar algorithm is also used to test and
[16] M. F. Toner and G. W. Roberts, “A BIST Scheme for a SNR,
calibrate the ADC for better linearity. The calibration method
Gain Tracking, and Frequency Response Test of a Sigma-Delta
has been verified by simulation, which shows that with the use
ADC,” IEEE Trans. Circuits and Systems II: Analog and Digital
of a dithering DAC we can achieve improved linearity for an
Signal Processing, vol. 42, no. 1, pp. 1–15, Jan. 1995.
on-chip DAC output.
[17] B. Vinnakota, editor, Analog and Mixed-Signal Test. Prentice-
Acknowledgment: This research was supported in part by Hall PTR, 1998.
the National Science Foundation Grant CNS-0708962. [18] Y.-S. Wang, J.-X. Wang, F.-C. Lai, and Y.-Z. Ye, “A Low-Cost
BIST Scheme for ADC Testing,” in Proc. 6th International Conf.
R EFERENCES on ASIC, volume 2, Oct. 2005, pp. 694–698.
[1] M. L. Bushnell and V. D. Agrawal, Essentials of Testing for Dig- [19] H. Xing, D. chen, and R. L. Geiger, “Linearity Test for High
ital, Memory & Mixed-Signal VLSI Circuits. Boston: Springer, Resolution DACs Using Low-Accuracy DDEM Flash ADCs,”
2000. in IEEE International Symp. Circuits and Systems, May 2006,
[2] J. C. Candy and G. C. Temes, Oversampling Methods for A/D pp. 2469–2472.
D/A Conversion, Oversampling Delta-Sigma Converters. New [20] H. Yu, J. A. Abraham, S. Hwang, and J. Roh, “Efficient Loop-
Jersey: IEEE Press, 1992. p.2-3. back Testing of On-Chip ADCs and DACs,” in Proc. Design
[3] S. Haykin, An Introduction to Analog and Digital Communica- Automation Conf., Asia and South Pacific, volume 21-24, Jan.
tion. New York: John Wiley & Sons, 1989. See pages 187-197 2003, pp. 651–656.
and 323-326.

Paper 32.2 INTERNATIONAL TEST CONFERENCE 10