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Practical File

The document is a practical file submitted by a student named Sumedh Chauhan for the subject Hardware Description Language Lab. It contains 20 experiments on designing various digital circuits like 2:1 Mux, Half Adder, 4:1 Multiplexer, Full Adder, Full Subtractor etc. using both data flow and behavioural simulation in Xilinx Vivado. For each experiment, the student has provided the simulation code, test bench, waveform and result.
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0% found this document useful (0 votes)
47 views82 pages

Practical File

The document is a practical file submitted by a student named Sumedh Chauhan for the subject Hardware Description Language Lab. It contains 20 experiments on designing various digital circuits like 2:1 Mux, Half Adder, 4:1 Multiplexer, Full Adder, Full Subtractor etc. using both data flow and behavioural simulation in Xilinx Vivado. For each experiment, the student has provided the simulation code, test bench, waveform and result.
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
You are on page 1/ 82

National Institute of Technology, Hamirpur

Department of Electronics and Communication Engineering


Jan-May 2019

Practical
PracticalFile
File

Subject Name: Subject Code:


Hardware Description Language ECD-326
Lab

Course: Semester:
ECE 6th

Submitted By: Submitted to:


Sumedh Chauhan Ms Tarun
Roll no: 16458

Faculty Signature

1|Page
S.No. Practical Page
N0.
1 To design a 2:1 Mux using Data Flow Simulation 4-7
and Behavioural Simulation.
2 To design a Half Adder Data Flow Simulation and 8-10
Behavioural Simulation.
3 To design a 4:1 Multiplexer Data Flow Simulation 11-13
and Behavioural Simulation.
4 To design a Full Adder Data Flow Simulation and 15-17
Behavioural Simulation.
5 To design a Full Subtractor Data Flow Simulation 18-21
and Behavioural Simulation.
6 To design a Half Subtractor Data Flow Simulation 22-24
and Behavioural Simulation.
7 To design a Full Subtractor using Half Subtractor 24-28
Data Flow Simulation and Behavioural
Simulation.
8 To design a Full Adder using Half Adder Data 29-32
Flow Simulation and Behavioural Simulation.
9 To design a 4:1 Mux using 2:1 Mux using Data 33-36
Flow Simulation and Behavioural Simulation.
10 To design a 3:8 Decoder using Data Flow 37-40
Simulation and Behavioural Simulation.
11 To design a 8:3 Encoder using Data Flow 41-43
Simulation and Behavioural Simulation.
12 To design a 8:3 Priority Encoder using Data Flow 44-48
Simulation and Behavioural Simulation.
13 To design a 1 Bit Multiplier using Data Flow 49-53
Simulation and Behavioural Simulation.
14 To design a 1 Bit Comparator using Data Flow 54-58
Simulation and Behavioural Simulation.
15 To design a Synchronous Reset D Flip-Flop using 59-62
Data Flow Simulation and Behavioural

2|Page
Simulation.
16 To design an Asynchronous Reset D Flip-Flop 63-66
using Data Flow Simulation and Behavioural
Simulation.
17 To design a Synchronous Preset D Flip-Flop using 67-70
Data Flow Simulation and Behavioural
Simulation.
18 To design an Asynchronous Preset D Flip-Flop 71-74
using Data Flow Simulation and Behavioural
Simulation.
19 To design and simulate Left to Right Shift 75-78
Register.
20 To design and simulate Right to Left Shift 79-82
Register.

3|Page
EXPERIMENT NO: 1
AIM: To design a 2:1 Mux using Data Flow Simulation and Behavioural
Simulation.
Tools: Xilinx Vivado 2017.4

DATA FLOW SIMULATION:


Simulation Code:
module two_to_one_mux_code(a,b,s,out);
input a;
input b;
input s;
output out;
assign out = (s&a)|((~s)&b);
endmodule

Test Bench:
module two_one_mux_code_tb();
reg a;
reg b;
reg s;
wire out;
two_to_one_mux_code res(a,b,s,out);
initial
begin
a=0; b=0; s=0; #100;
a=0; b=1; s=0; #100;
a=1; b=0; s=0; #100;
a=1; b=1; s=0; #100;
a=0; b=0; s=1; #100;

4|Page
a=0; b=1; s=1; #100;
a=1; b=0; s=1; #100;
a=1; b=1; s=1; #100;
$stop;
end
endmodule

WAVEFORM:

5|Page
RTL SCHEMATIC:

BEHAVIOURAL SIMULATION:
Simulation Code:
module twoTOoneMUX_behav_code(a,b,s,out);
input a;
input b;
input s;
output reg out;
always @(a,b,s)
begin
out = (s&a)|((~s)&b);
end

6|Page
endmodule

Test Bench:
module twoTOonebeh_tb_code();
reg a;
reg b;
reg s;
wire out;
twoTOoneMUX_behav_code res(a,b,s,out);
initial
begin
a=0; b=0; s=0; #100;
a=0; b=1; s=0; #100;
a=1; b=0; s=0; #100;
a=1; b=1; s=0; #100;
a=0; b=0; s=1; #100;
a=0; b=1; s=1; #100;
a=1; b=0; s=1; #100;
a=1; b=1; s=1; #100;
$stop;
end
endmodule

RESULT:

2:1 Multiplexer in Data Flow Simulation and Behavioural have been designed and
waveform has been obtained.

7|Page
EXPERIMENT NO: 2
AIM: To design a Half Adder Data Flow Simulation and Behavioural
Simulation.
Tools: Xilinx Vivado 2017.4

DATA FLOW SIMULATION:


Simulation Code:
module half_adder_code(a,b, sum, carry);
input a;
input b;
output sum;
output carry;
assign sum = a^b;
assign carry = a&b;
endmodule

Test Bench:
module half_adder_tb_code();
reg a;
reg b;
wire sum;
wire carry;
half_adder_code res(a,b, sum, carry);
initial
begin
a=0; b=0; #100;
a=1; b=1; #100;
$stop;
end

8|Page
endmodule

WAVEFORM:

RTL SCHEMATIC:

BEHAVIOURAL SIMULATION:
Simulation Code:
module half_adder_behav_code(a, b, sum, carry);
input a;

9|Page
input b;
output reg sum;
output reg carry;
always @(a,b)
begin
carry = a&b;
sum = a^b;
end
endmodule

Test Bench:
module half_adder_behav_tb();
reg a;
reg b;
wire sum;
wire carry;
half_adder_behav_code res(a, b, sum, carry);
initial
begin
a=0; b=0; #100;
a=0; b=1; #100;
a=1; b=0; #100;
a=1; b=1; #100;
$stop;
end
endmodule

RESULT:
Half Adder in Data Flow Simulation and Behavioural have been
designed and waveform has been obtained.

10 | P a g e
EXPERIMENT NO: 3
AIM: To design a 4:1 Multiplexer Data Flow Simulation and
Behavioural Simulation.
Tools: Xilinx Vivado 2017.4

DATA FLOW SIMULATION:


Simulation Code:
module fourTOone_mux_code(a,b,c,d,s0,s1,y);
input a,b,c,d,s0,s1;
output y;
assign y = (a&(~s0)&~(s1)) | (b&(~s0)&s1) | (c&s0&(~s1)) | (d&s0&s1);
endmodule

Test Bench:
module fourTO1_tb_code();
reg a,b,c,d,s0,s1;
wire y;
fourTOone_mux_code res(a,b,c,d,s0,s1,y);
initial
begin
a=0; b=0; c=0; d=0; s0=0; s1=1; #100;
a=0; b=1; c=0; d=0; s0=0; s1=1; #100;
a=0; b=1; c=0; d=0; s0=1; s1=1; #100;
a=1; b=0; c=0; d=1; s0=0; s1=1; #100;
a=0; b=0; c=0; d=0; s0=0; s1=0; #100;
a=1; b=0; c=0; d=0; s0=0; s1=0; #100;
a=1; b=0; c=1; d=0; s0=1; s1=0; #100;
end
endmodule

11 | P a g e
BEHAVIOURAL SIMULATION:

Simulation Code:
module fourTOone_mux_behav_code(a,b,c,d,s0,s1,y);
input a,b,c,d,s0,s1;
output reg y;
always @(a,b,c,d,s0,s1)
begin
y = (a&(~s0)&~(s1)) | (b&(~s0)&s1) | (c&s0&(~s1)) | (d&s0&s1);
end
endmodule

Test Bench:
module fourTO1_tb_behav_code();
reg a,b,c,d,s0,s1;
wire y;
fourTOone_mux_behav_code res(a,b,c,d,s0,s1,y);
initial
begin
a=0; b=0; c=0; d=0; s0=0; s1=1; #100;
a=0; b=1; c=0; d=0; s0=0; s1=1; #100;
a=0; b=1; c=0; d=0; s0=1; s1=1; #100;
a=1; b=0; c=0; d=1; s0=0; s1=1; #100;
a=0; b=0; c=0; d=0; s0=0; s1=0; #100;
a=1; b=0; c=0; d=0; s0=0; s1=0; #100;
a=1; b=0; c=1; d=0; s0=0; s1=0; #100;
a=1; b=0; c=0; d=0; s0=0; s1=0; #100;
a=1; b=0; c=1; d=0; s0=1; s1=0; #100;
end
endmodule
12 | P a g e
WAVEFORM:

RTL SCHEMATIC:

RESULT:
4:1 Multiplexer in Data Flow Simulation and Behavioural have been
designed and waveform has been obtained.
13 | P a g e
EXPERIMENT NO: 4
AIM: To design a Full Adder Data Flow Simulation and Behavioural
Simulation.
Tools: Xilinx Vivado 2017.4

DATA FLOW SIMULATION:


Simulation Code:
module full_adder(a,b,c, sum, carry);
input a,b,c;
output sum,carry;
assign sum=a^b^c;
assign carry=(a&b)|(b&c)|(c&a);
endmodule

Test Bench:
module full_add_tb();
reg a,b,c;
wire carry,sum;
full_adder res(a,b,c,sum, carry);
initial
begin
$monitor("a=%b, b=%b, c=%b, sum=%b, carry=%b, time=%d", a, b, c,
sum, carry, $time);
a=0; b=0; c=0; #100;
a=0; b=0; c=1; #100;
a=0; b=1; c=0; #100;
a=0; b=1; c=1; #100;
a=1; b=0; c=0; #100;
a=1; b=0; c=1; #100;

14 | P a g e
a=1; b=1; c=0; #100;
a=1; b=1; c=1; #100;
$stop;
end
endmodule

BEHAVIOURAL SIMULATION:
Simulation Code:
module full_adder_beha(a,b,c, sum, carry);
input a,b,c;
output reg sum,carry;
always @(a,b,c)
begin
sum=a^b^c;
carry=(a&b)|(b&c)|(c&a);
end
endmodule

Test Bench:
module full_add_tb_beha();
reg a,b,c;
wire carry,sum;
full_adder_beha res(a,b,c,sum, carry);
initial
begin
$monitor("a=%b, b=%b, c=%b, sum=%b, carry=%b, time=%d", a, b, c,
sum, carry, $time);
a=0; b=0; c=0; #100;
a=0; b=0; c=1; #100;

15 | P a g e
a=0; b=1; c=0; #100;
a=0; b=1; c=1; #100;
a=1; b=0; c=0; #100;
a=1; b=0; c=1; #100;
a=1; b=1; c=0; #100;
a=1; b=1; c=1; #100;
$stop;
end
endmodule

WAVEFORM:

16 | P a g e
RTL SCHEMATIC:

RESULT:
Full Adder in Data Flow Simulation and Behavioural have been designed
and waveform has been obtained.

17 | P a g e
EXPERIMENT NO: 5
AIM: To design a Full Subtractor Data Flow Simulation and
Behavioural Simulation.
Tools: Xilinx Vivado 2017.4

DATA FLOW SIMULATION:


Simulation Code:
module full_sub(a, b, c, diff, borrow);
input a, b, c;
output diff, borrow;
assign diff = a^b^c;
assign borrow = ((~a)&b) | ((~(a^b))&c);
endmodule

Test Bench:
module full_sub_tb();
reg a, b, c;
wire diff, borrow;
full_sub res(a, b, c, diff, borrow);
initial
begin
$monitor("a=%b, b=%b, c=%b, diff=%b, borrow=%b, time=%d", a, b, c,
diff, borrow, $time);
a=0; b=0; c=0; #100;
a=0; b=0; c=1; #100;
a=0; b=1; c=0; #100;
a=0; b=1; c=1; #100;
a=1; b=0; c=0; #100;
a=1; b=0; c=1; #100;

18 | P a g e
a=1; b=1; c=0; #100;
a=1; b=1; c=1; #100;
$stop;
end
endmodule

BEHAVIOURAL SIMULATION:

Simulation Code:
module full_sub_beha(a, b, c, diff, borrow);
input a, b, c;
output reg diff, borrow;
always @(a,b,c)
begin
diff = a^b^c;
borrow = ((~a)&b) | ((~(a^b))&c);
end
endmodule

Test Bench:
module full_sub_tb_beha();
reg a, b, c;
wire diff, borrow;
full_sub_beha res(a, b, c, diff, borrow);
initial
begin
$monitor("a=%b, b=%b, c=%b, diff=%b, borrow=%b, time=%d", a, b, c,
diff, borrow, $time);
a=0; b=0; c=0; #100;
a=0; b=0; c=1; #100;
19 | P a g e
a=0; b=1; c=0; #100;
a=0; b=1; c=1; #100;
a=1; b=0; c=0; #100;
a=1; b=0; c=1; #100;
a=1; b=1; c=0; #100;
a=1; b=1; c=1; #100;
$stop;
end
endmodule

WAVEFORM:

20 | P a g e
RTL SCHEMATIC:

RESULT:
Full Subtractor in Data Flow Simulation and Behavioural have been
designed and waveform has been obtained.

21 | P a g e
EXPERIMENT NO: 6
AIM: To design a Half Subtractor Data Flow Simulation and Behavioural
Simulation.
Tools: Xilinx Vivado 2017.4

DATA FLOW SIMULATION:


Simulation Code:
module half_sub(a, b, diff, borrow);
input a, b;
output diff, borrow;
assign diff = a^b;
assign borrow = (~a)&b;
endmodule

Test Bench:
module half_sub_tb();
reg a, b;
wire diff, borrow;
half_sub res(a, b, diff, borrow);
initial
begin
$monitor("a=%b, b=%b, diff=%b, borrow=%b, time=%d", a, b, diff,
borrow, $time);
a=0; b=0; #100;
a=0; b=1; #100;
a=1; b=0; #100;
a=1; b=1; #100;
$stop;
end

22 | P a g e
endmodule

BEHAVIOURAL SIMULATION:

Simulation Code:
module half_sub_beha(a, b, diff, borrow);
input a, b;
output reg diff, borrow;
always @(a,b)
begin
diff = a^b;
borrow = (~a)&b
end
endmodule

Test Bench:
module half_sub_tb();
reg a, b;
wire diff, borrow;
half_sub res(a, b, diff, borrow);
initial
begin
$monitor("a=%b, b=%b, diff=%b, borrow=%b, time=%d", a, b, diff,
borrow, $time);
a=0; b=0; #100;
a=0; b=1; #100;
a=1; b=0; #100;
a=1; b=1; #100;
$stop;
end
23 | P a g e
endmodule

WAVEFORM:

RTL SCHEMATIC:

RESULT:
Full Subtractor in Data Flow Simulation and Behavioural have been
designed and waveform has been obtained.

24 | P a g e
EXPERIMENT NO: 7
AIM: To design a Full Subtractor using Half Subtractor using Data Flow
Simulation and Behavioural Simulation.
Tools: Xilinx Vivado 2017.4

DATA FLOW SIMULATION:


Simulation Code:
module fs_using_hs(a, b, c, borrow, differ);
input a, b, c;
output differ, borrow;
wire borrow1, differ_1, borrow2;
half_subtractor a1(a, b, borrow1, differ_1);
half_subtractor a2(differ_1, c, borrow2, differ);
assign borrow = borrow1 | borrow2;
endmodule

module half_subtractor(a0, b0, borrow, differ);


input a0, b0;
output borrow, differ;
assign borrow = (~a0)&b0;
assign differ = a0^b0;
endmodule

Test Bench:
module fs_using_hs_tb();
reg a,b,c;
wire borrow,differ;
fs_using_hs res(a,b,c,borrow,differ);
initial
begin
25 | P a g e
a=0; b=0; c=0;
#100 a=0; b=0; c=1;
#100 a=0; b=1; c=0;
#100 a=0; b=1; c=1;
#100 a=1; b=0; c=0;
#100 a=1; b=0; c=1;
#100 a=1; b=1; c=0;
#100 a=1; b=1; c=1;
#100;
end
endmodule

BEHAVIOURAL SIMULATION:
module fs_using_hs_beha(a, b, c, borrow, differ);
input a, b, c;
output differ, borrow;
wire borrow1, differ_1, borrow2;
half_subtractor_beha a1(a, b, borrow1, differ_1);
half_subtractor_beha a2(differ_1, c, borrow2, differ);
assign borrow = borrow1 | borrow2;
endmodule
module half_subtractor_beha(a0, b0, borrow, differ);
input a0, b0;
output reg borrow, differ;
always @(a0,b0)
begin
borrow = (~a0)&b0;
differ = a0^b0;
end
endmodule

26 | P a g e
Test Bench:
module fs_using_hs_tb_beha();
reg a,b,c;
wire borrow,differ;
fs_using_hs_beha res(a,b,c,borrow,differ);
initial
begin
a=0; b=0; c=0;
#100 a=0; b=0; c=1;
#100 a=0; b=1; c=0;
#100 a=0; b=1; c=1;
#100 a=1; b=0; c=0;
#100 a=1; b=0; c=1;
#100 a=1; b=1; c=0;
#100 a=1; b=1; c=1;
#100;
end
endmodule

WAVEFORM:

27 | P a g e
RTL SCHEMATIC:

RESULT:
Full Subtractor using Half Subtractor in Data Flow Simulation and
Behavioural have been designed and waveform has been obtained.

28 | P a g e
EXPERIMENT: 8
AIM: To design a Full Adder using half Adder using Data Flow
Simulation and Behavioural Simulation.
Tools: Xilinx Vivado 2017.4

DATA FLOW SIMULATION:


Simulation Code:
module fa_using_ha(a, b, c, cy_final, sum);
input a, b, c;
output cy_final, sum;
wire cy1, sum_1, cy2;
half_adder a1(a, b, cy1, sum_1);
half_adder a2(c, sum_1, cy2, sum);
or go1(cy_final, cy1, cy2);
endmodule

module half_adder(a0, b0, cy, sum);


input a0, b0;
output cy, sum;
assign cy = a0^b0;
assign sum = a0&b0;
endmodule

Test Bench:
module fa_using_ha_tb();
reg a,b,c;
wire cy,sum;
fa_using_ha res(a,b,c,cy,sum);
initial
begin

29 | P a g e
a=0; b=0; c=0;
#100 a=0; b=0; c=1;
#100 a=0; b=1; c=0;
#100 a=0; b=1; c=1;
#100 a=1; b=0; c=0;
#100 a=1; b=0; c=1;
#100 a=1; b=1; c=0;
#100 a=1; b=1; c=1;
#100;
end
endmodule

BEHAVIOURAL SIMULATION:
Simulation Code:
module fa_using_ha_beha(a, b, c, cy_final, sum);
input a, b, c;
output cy_final, sum;
wire cy1, sum_1, cy2;
half_adder a1(a, b, cy1, sum_1);
half_adder a2(c, sum_1, cy2, sum);
assign cy_final = cy1 | cy2;
endmodule

module half_adder_beha(a0, b0, cy, sum);


input a0, b0;
output reg cy, sum;
always @(a0, b0)
begin
cy = a0^b0;
sum = a0&b0;
end
endmodule
30 | P a g e
Test Bench:
module fa_using_ha_tb();
reg a, b ,c;
wire cy, sum;
fa_using_ha res(a, b, c, cy, sum);
initial
begin
a=0; b=0; c=0;
#100 a=0; b=0; c=1;
#100 a=0; b=1; c=0;
#100 a=0; b=1; c=1;
#100 a=1; b=0; c=0;
#100 a=1; b=0; c=1;
#100 a=1; b=1; c=0;
#100 a=1; b=1; c=1;
#100;
end
endmodule

Waveform:

31 | P a g e
RTL SCHEMATIC:

RESULT:
Full Adder using Half Adder in Data Flow Simulation has been designed
and waveform has been obtained.

32 | P a g e
EXPERIMENT NO: 9
AIM: To design a 4:1 Mux using 2:1 Mux Data Flow Simulation and
Behavioural Simulation.
Tools: Xilinx Vivado 2017.4

DATA FLOW SIMULATION:


Simulation Code:
module mux4to1using2to1(a, b, c, d, s0, s1, y);
input a, b, c, d, s0, s1;
output y;
wire d1, d2;
mux2to1 mux1(a, b, s0, d1);
mux2to1 mux2(c, d, s0, d2);
mux2to1 mux3(d1, d2, s1, y);
endmodule

module mux2to1(a, b, s, y);


input a, b, s;
output y;
assign y = s?b:a;
endmodule

Test Bench:
module mux4to1using2to1_tb();
reg a, b, c, d, s0, s1;
wire y;
mux4to1using2to1 res(a, b, c, d, s0, s1, y);
initial
begin

33 | P a g e
a=0; b=0; c=0; d=0; s0=0; s1=1; #100;
a=0; b=1; c=0; d=0; s0=0; s1=1; #100;
a=0; b=1; c=0; d=0; s0=1; s1=1; #100;
a=1; b=0; c=0; d=1; s0=0; s1=1; #100;
a=0; b=0; c=0; d=0; s0=0; s1=0; #100;
a=1; b=0; c=0; d=0; s0=0; s1=0; #100;
a=1; b=0; c=1; d=0; s0=0; s1=0; #100;
a=1; b=0; c=0; d=0; s0=0; s1=0; #100;
a=1; b=0; c=1; d=0; s0=1; s1=0; #100;
end
endmodule

BEHAVIOURAL SIMULATION:
Simulation Code:
module mux4to1using2to1_beha(a, b, c, d, s0, s1, y);
input a, b, c, d, s0, s1;
output y;
wire d1, d2;
mux2to1_beha mux1(a, b, s0, d1);
mux2to1_beha mux2(c, d, s0, d2);
mux2to1_beha mux3(d1, d2, s1, y);
endmodule

module mux2to1_beha(a, b, s, y);


input a, b, s;
output reg y;
always @(a,b,s)
begin
y = s?b:a;
endmodule

34 | P a g e
Test Bench:
module mux4to1using2to1_tb_beha();
reg a, b, c, d, s0, s1;
wire y;
mux4to1using2to1_beha res(a, b, c, d, s0, s1, y);
initial
begin
a=0; b=0; c=0; d=0; s0=0; s1=1; #100;
a=0; b=1; c=0; d=0; s0=0; s1=1; #100;
a=0; b=1; c=0; d=0; s0=1; s1=1; #100;
a=1; b=0; c=0; d=1; s0=0; s1=1; #100;
a=0; b=0; c=0; d=0; s0=0; s1=0; #100;
a=1; b=0; c=0; d=0; s0=0; s1=0; #100;
a=1; b=0; c=1; d=0; s0=0; s1=0; #100;
a=1; b=0; c=0; d=0; s0=0; s1=0; #100;
a=1; b=0; c=1; d=0; s0=1; s1=0; #100;
end
endmodule

WAVEFORM:

35 | P a g e
RTL SCHEMATIC:

RESULT:
4:1 Mux using 2:1 Mux in Data Flow Simulation has been designed and
waveform has been obtained.

36 | P a g e
EXPERIMENT NO: 10
AIM: To design a 3:8 Decoder using Data Flow Simulation and
Behavioural Simulation.
Tools: Xilinx Vivado 2017.4

DATA FLOW SIMULATION:


Simulation Code:
module decoder3to8(x, y, z, out);
input x, y, z;
output [7:0]out;
assign out[7] = (~x)&(~y)&(~z);
assign out[6] = (~x)&(~y)&(z);
assign out[5] = (~x)&(y)&(~z);
assign out[4] = (~x)&(y)&(z);
assign out[3] = (x)&(~y)&(~z);
assign out[2] = (x)&(~y)&(z);
assign out[1] = (x)&(y)&(~z);
assign out[0] = (x)&(y)&(z);
endmodule

Test Bench:
module decoder3to8_tb();
reg x,y,z;
wire [7:0]out;
decoder3to8 res(x, y, z, out);
initial
begin
x=0; y=0; z=0; #100;
x=0; y=0; z=1; #100;

37 | P a g e
x=0; y=1; z=0; #100;
x=0; y=1; z=1; #100;
x=1; y=0; z=0; #100;
x=1; y=0; z=1; #100;
x=1; y=1; z=0; #100;
x=1; y=1; z=1; #100;
$stop;
end
endmodule

BEHAVIOURAL SIMULATION:

Simulation Code:
module decoder3to8_beha(x, y, z, out);
input x, y, z;
output reg [7:0]out;
always @(x, y, z)
begin
out[7] = (~x)&(~y)&(~z);
out[6] = (~x)&(~y)&(z);
out[5] = (~x)&(y)&(~z);
out[4] = (~x)&(y)&(z);
out[3] = (x)&(~y)&(~z);
out[2] = (x)&(~y)&(z);
out[1] = (x)&(y)&(~z);
out[0] = (x)&(y)&(z);
end
endmodule

Test Bench:
38 | P a g e
module decoder3to8_tb_beha();
reg x,y,z;
wire [7:0]out;
decoder3to8_beha res(x, y, z, out);
initial
begin
x=0; y=0; z=0; #100;
x=0; y=0; z=1; #100;
x=0; y=1; z=0; #100;
x=0; y=1; z=1; #100;
x=1; y=0; z=0; #100;
x=1; y=0; z=1; #100;
x=1; y=1; z=0; #100;
x=1; y=1; z=1; #100;
$stop;
end
endmodule

39 | P a g e
Waveform:

RTL SCHEMATIC:

RESULT:
Full Subtractor in Data Flow Simulation and Behavioural
have been designed and waveform has been obtained.

40 | P a g e
EXPERIMENT NO: 11
AIM: To design a 8:3 Encoder using Data Flow Simulation and
Behavioural Simulation.
Tools: Xilinx Vivado 2017.4

DATA FLOW SIMULATION:


Simulation Code:
module encoder8to3(a, x, y, z);
input [7:0]a;
output x, y, z;
assign x= a[7]|a[6]|a[5]|a[4];
assign y= a[2]|a[3]|a[6]|a[7];
assign z= a[1]|a[3]|a[5]|a[7];
endmodule

Test Bench:
module encoder8to3_tb();
reg [7:0]a;
wire x, y, z;
encoder8to3 RES(a, x, y, z);
initial
begin
a=8'b00000001; #100;
a=8'b00000010; #100;
a=8'b00010000; #100;
a=8'b00100000; #100;
a=8'b01000000; #100;
a=8'b10000000; #100;
a=8'b01001000; #100;

41 | P a g e
$stop;
end
endmodule

BEHAVIOURAL SIMULATION

Simulation Code:
module encoder8to3_beha(a, x, y, z);
input [7:0]a;
output reg x, y, z;
always @(a)
begin
assign x= a[7] | a[6] | a[5] | a[4];
assign y= a[2] | a[3] | a[6] | a[7];
assign z= a[1] | a[3] | a[5] | a[7];
end
endmodule

Test Bench:
module encoder8to3_tb_beha();
reg [7:0]a;
wire x, y, z;
encoder8to3_beha RES(a, x, y, z);
initial
begin
a=8'b00000001; #100;
a=8'b00000010; #100;
a=8'b00000100; #100;
a=8'b00001000; #100;
a=8'b10000000; #100;
a=8'b01001000; #100;
42 | P a g e
$stop;
end
endmodule

Waveform:

RTL SCHEMATIC:

RESULT:
8:3 Encoder in Data Flow Simulation and Behavioural have been
designed and waveform has been obtained.

43 | P a g e
EXPERIMENT NO: 12
AIM: To design a 8:3 Priority Encoder using Data Flow Simulation and
Behavioural Simulation.
Tools: Xilinx Vivado 2017.4

DATA FLOW SIMULATION:


Simulation Code:
module priorityencoder8to3(a, x, y, z);
input [7:0]a;
output x, y, z;
assign z =((~a[6])&(((~a[4])&(~a[2])&a[1])|((~a[4])&a[3])| a[5]))|a[7];
assign y = ((~a[5]) & (~a[4]) & (a[2] | a[3])) | a[6] | a[7];
assign x = a[4] | a[5] | a[6] | a[7];
endmodule

Test Bench:
module pe8to3_tb();
reg [7:0]a;
wire x, y, z;
priorityencoder8to3 RES(a, x, y, z);
initial
begin
a=8'b00000001; #100;
a=8'b00000010; #100;
a=8'b00000100; #100;
a=8'b00001000; #100;
a=8'b00010110; #100;
a=8'b00100000; #100;
a=8'b01000000; #100;
a=8'b10000000; #100;
44 | P a g e
a=8'b01001000; #100;
$stop;
end
endmodule

BEHAVIOURAL SIMULATION:
Simulation Code:
module priorityencoder8to3_beha(a, x, y, z);
input [7:0]a;
output reg x, y, z;
always @(a)
begin
z =((~a[6])&(((~a[4])&(~a[2])&a[1])|((~a[4])&a[3])| a[5]))|a[7];
y = ((~a[5]) & (~a[4]) & (a[2] | a[3])) | a[6] | a[7];
x = a[4] | a[5] | a[6] | a[7];
end
endmodule

Test Bench:
module pe8to3_tb_beha();
reg [7:0]a;
wire x, y, z;
priorityencoder8to3_beha RES(a, x, y, z);
initial
begin
a=8'b00000001; #100;
a=8'b00000010; #100;
a=8'b00000100; #100;
a=8'b00001000; #100;
a=8'b00010110; #100;
a=8'b00100000; #100;
45 | P a g e
a=8'b01000000; #100;
a=8'b10000000; #100;
a=8'b01001000; #100;
$stop;
end
endmodule

Waveform:

46 | P a g e
RTL SCHEMATIC:

47 | P a g e
POWER REPORT:

UTILIZATION REPORT:

RESULT:
8:3 Encoder in Data Flow Simulation and Behavioural have been
designed and waveform has been obtained.

48 | P a g e
EXPERIMENT:13
AIM: To design a 1bit multiplier using Data Flow Simulation and
Behavioural Simulation.
Tools: Xilinx Vivado 2017.4

DATA FLOW SIMULATION:


Simulation Code:
module multiplier_1_bit(a, b, p);
input a, b;
output p;
assign p=a*b;
endmodule

Test Bench:
module multiplier_tb();
reg a, b;
wire p;
multiplier_1_bit res(a, b, p);
initial
begin
$monitor("a=%b, b=%b, p=%b, time=%d", a, b, p, $time);
a=0; b=0; #200;
a=0; b=1; #200;
a=1; b=0; #200;
a=1; b=1; #200;
$stop;
end
endmodule

49 | P a g e
BEHAVIOURAL SIMULATION:

Simulation Code:
module multiplier_1_beh(a, b, p);
input a, b;
output reg p;
always @ (a, b)
begin
p=a*b;
end
endmodule

Test Bench:
module multiplier_tb();
reg a,b;
wire p;
multiplier_1_beh res(a,b,p);
initial
begin
$monitor("a=%b, b=%b, p=%b, time=%d",a,b,p,$time);
a=0;b=0;
#200 a=0;b=1;
#200 a=1;b=0;
#200 a=1;b=1;
#200 $stop;
end
endmodule

50 | P a g e
WAVEFORM:

51 | P a g e
RTL SCHEMATIC:

SYNTHESIS REPORT:

52 | P a g e
POWER REPORT:

UTILIZATION REPORT:

RESULT:
1bit Multiplier using Data Flow Simulation and Behavioural Simulation has been
designed and waveform has been obtained.

53 | P a g e
EXPERIMENT:14
AIM: To design a 1bit comparator using Data Flow Simulation and
Behavioural Simulation.
REQUIREMETS: Xilinx Vivado 2017.4

DATA FLOW SIMULATION:

Simulation Code:
module comparator_1_bit(a, b, e, g, l);
input a, b;
output e, g, l;
assign e=a ~^ b;
assign l=(~a) & b;
assign g=a & (~b);
endmodule

Test Bench:
module comparator_tb();
reg a, b;
wire e, g, l;
comparator_1_bit res(a, b, e, g, l);
initial
begin
$monitor("a=%b, b=%b, e=%b, g=%b, l=%b, time=%d", a, b, e, g, l,
$time);
a=0; b=0; #200;
a=0; b=1; #200;
a=1; b=0; #200;
a=1; b=1; #200;
$stop;
54 | P a g e
end
endmodule

BEHAVIOURAL SIMULATION:
Simulation Code:
module comparator_1_beh(a, b, e, g, l);
input a, b;
output reg e, g, l;
always @ (a, b)
begin
e=a ~^ b;
l=(~a) & b;
g=a & (~b);
end
endmodule

Test Bench:
module comparator_tb();
reg a, b;
wire e, g, l;
comparator_1_beh res(a, b, e, g, l);
initial
begin
$monitor("a=%b, b=%b, e=%b, g=%b, l=%b, time=%d", a, b, e, g, l,
$time);
55 | P a g e
a=0; b=0; #200;
a=0; b=1; #200;
a=1; b=0; #200;
a=1; b=1; #200;
$stop;
end
endmodule

WAVEFORM:

56 | P a g e
RTL SCHEMATIC:

SYNTHESIS REPORT:

57 | P a g e
POWER REPORT:

UTILIZATION REPORT:

RESULT:
1bit Comparator using Data Flow Simulation and Behavioural
Simulation has been designed and waveform has been
obtained.
58 | P a g e
EXPERIMENT:15
AIM: To design a Synchronous Reset D Flip-Flop using Data Flow
Behavioural Modelling.
REQUIREMETS: Xilinx Vivado 2017.4

Simulation Code
module sync_rst(output reg q, input d, clk, reset);
always @ (posedge clk)
begin
if(reset)
q=0;
else
q=d;
end
endmodule

Test Bench
module sync_rst_tb();
reg d, reset, clk;
wire q;
sync_rst res(q, d, clk, reset);
initial
begin
clk=0;
forever #8 clk=~clk;
end
initial
begin
reset=0; d=0;
#40 reset=0; d=1;

59 | P a g e
#40 reset=1; d=1;
#40 reset=1; d=0;
#40 $stop;
end
endmodule

WAVEFORM:

60 | P a g e
RTL SCHEMATIC:

SYNTHESIS REPORT:

61 | P a g e
POWER REPORT:

UTILIZATION REPORT:

RESULT:
Synchronous Reset D Flip-Flop using Behavioural Simulation has been
designed and waveform has been obtained.

62 | P a g e
EXPERIMENT:16
AIM: To design an Asynchronous Reset D Flip-Flop using Behavioural
Modeling.
TOOLS: Xilinx Vivado 2017.4

Simulation Code:
module async_rst(output reg q, input d, clk, reset);
always @ (posedge clk, posedge reset)
begin
if(reset)
q=0;
else
q=d;
end
endmodule

Test Bench:
module async_rst_tb();
reg d, reset, clk;
wire q;
async_rst res(q, d, clk, reset);
initial
begin
clk=0;
forever #8 clk=~clk;
end
initial
begin
reset=0; d=0;
#40 reset=0; d=1;

63 | P a g e
#40 reset=1; d=1;
#40 reset=1; d=0;
#40 $stop;
end
endmodule

WAVEFORM:

64 | P a g e
RTL SCHEMATIC:

SYNTHESIS REPORT:

65 | P a g e
POWER REPORT:

UTILIZATION REPORT:

RESULT:
Asynchronous Reset D Flip-Flop using Behavioural Simulation has been
designed and waveform has been obtained.

66 | P a g e
EXPERIMENT:17
AIM: To design a Synchronous Preset D Flip-Flop using Behavioural
Modeling.
TOOLS: Xilinx Vivado 2017.4

Simulation Code
module sync_preset(output reg q, input d, clk, preset);
always @ (posedge clk)
begin
if(preset)
q=1;
else
q=d;
end
endmodule

Test Bench
module sync_preset_tb();
reg d,preset,clk;
wire q;
sync_preset res(q,d,clk,preset);
initial
begin
clk=0;
forever #8 clk=~clk;
end
initial
begin
preset=0; d=0;
#40 preset=0; d=1;

67 | P a g e
#40 preset=1; d=1;
#40 preset=1; d=0;
#40 $stop;
end
endmodule

WAVEFORM:

68 | P a g e
RTL SCHEMATIC:

SYNTHESIS REPORT:

69 | P a g e
POWER REPORT:

UTILIZATION REPORT:

RESULT:

Synchronous Preset D Flip-Flop using Behavioural Simulation has been


designed and waveform has been obtained.

70 | P a g e
EXPERIMENT:18
AIM: To design an Asynchronous Preset D Flip-Flop using Behavioural
Modeling.
TOOLS: Xilinx Vivado 2017.4

Simulation Code
module async_preset(output reg q, input d, clk, preset);
always @ (posedge clk, posedge preset)
begin
if(preset)
q=1;
else
q=d;
end
endmodule

Test Bench
module async_preset_tb();
reg d,preset,clk;
wire q;
async_preset res(q,d,clk,preset);
initial
begin
clk=0;
forever #8 clk=~clk;
end
initial
begin
preset=0; d=0;
#40 preset=0; d=1;
71 | P a g e
#40 preset=1; d=1;
#40 preset=1; d=0;
#40 $stop;
end
endmodule

WAVEFORM:

72 | P a g e
RTL SCHEMATIC:

SYNTHESIS REPORT:

73 | P a g e
POWER REPORT:

UTILIZATION REPORT:

RESULT:

Asynchronous Preset D Flip-Flop using Behavioural Simulation has been


designed and waveform has been obtained.

74 | P a g e
EXPERIMENT:19
AIM: To design and simulate left to right shift register.
TOOLS: Xilinx Vivado 2017.4
Simulation Code
module lt_rt_shift(output reg so, input si,clk);
reg b,c,d;
always @ (posedge clk)
begin
b<=si;
c<=b;
d<=c;
so<=d;
end
endmodule

Test Bench
module shift_tb();
reg si,clk;
wire so;
lt_rt_shift res(so,si,clk);
initial
begin
clk=0;
forever #8 clk=~clk;
end
initial
begin
si=1;
#30 si=0;
#30 si=1;
75 | P a g e
#30 si=0;
#30 si=1;
#30 si=0;
#30 $stop;
end
endmodule

WAVEFORM:

76 | P a g e
RTL SCHEMATIC:

SYNTHESIS REPORT:

77 | P a g e
POWER REPORT:

UTILIZATION REPORT:

RESULT:
The left to right shift register has been implemented successfully and its
simulation output has been obtained.

78 | P a g e
EXPERIMENT:20
AIM: To design and simulate right to left shift register.
REQUIREMETS: Xilinx Vivado 2017.4

Simulation Code
module rt_lt_shift(output reg q0, input d3, clk);
reg q1, q2, q3;
always @ (posedge clk)
begin
q3<=d3;
q2<=q3;
q1<=q2;
q0<=q1;
end
endmodule

Test Bench
module shift_tb();
reg d3,clk;
wire q0;
rt_lt_shift res(q0,d3,clk);
initial
begin
clk=0;
forever #8 clk=~clk;
end
initial
begin
d3=1;
#30 d3=0;

79 | P a g e
#30 d3=1;
#30 d3=0;
#30 d3=1;
#30 d3=0;
#30 $stop;
end
endmodule

WAVEFORM:

80 | P a g e
RTL SCHEMATIC:

SYNTHESIS REPORT:

81 | P a g e
POWER REPORT:

UTILIZATION REPORT:

RESULT:
The right to left shift register has been implemented successfully and its
simulation output has been obtained.

82 | P a g e

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