Designer’s guide May 2001

Semiconductors for

Liquid Crystal Displays

LCD DISPLAY Designer’s Guide – MAY 2001
Contents

Section
1. INTRODUCTION AND SYSTEM SOLUTIONS ........................................................................................1-1
Introduction ..........................................................................................................................................................1-2
System solutions ..................................................................................................................................................1-3

2. SIGNAL PROCESSING AND CONTROL....................................................................................................2-1

TFT-display controllers .......................................................................................................................................2-2
RGB A-to-D conversion ..................................................................................................................................2-11
Video input processors....................................................................................................................................2-13
Memories ............................................................................................................................................................2-18
LCD graphic drivers .........................................................................................................................................2-20

3. RELATED SYSTEMS ............................................................................................................................................3-1

Audio amplifiers ...................................................................................................................................................3-2
Audio D-to-A conversion..................................................................................................................................3-6
USB interface......................................................................................................................................................3-17
SMPS.....................................................................................................................................................................3-20
LCD modules .....................................................................................................................................................3-24
Discretes .............................................................................................................................................................3-24

APPENDIX...................................................................................................................................................................A-1
Index of type numbers.......................................................................................................................................A-2

NOTE
Purchase of Philips I2C components
conveys a license under the Philips’ I2C
patent to use the components in the I2C
system provided the system conforms to
the I2C specifications defined by Philips.
This specification can be ordered using
the code 9398 393 40011.

LCD Displays i
ii LCD Displays
 1

INTRODUCTION
AND SYSTEM
SOLUTIONS

LCD Displays 1-1

 INTRODUCTION AND SYSTEM SOLUTIONS INTRODUCTION

1 LCD DISPLAY Designer’s Guide – MAY 2001

Seeing the World with LCD Technology large scale-factors. A fully programmable Polyphase filter allows
variable characteristics, from smoothing to sharpening,
In the world of multimedia, what we see has an immediate and to be applied to the background picture during upscaling.
powerful impact. That is why the display unit — the PC on our
desk, the TV in our house or the projected image on a screen — Several renowned Philips ICs have been optimally matched to
is typically the most significant technological interface we use. work with these graphic engines. They include:
As computing, telecommunications, home entertainment and
networking technologies converge, the display unit will continue • High-speed triple ADCs (TDA8752 and TDA8757) for gen-
to hold our attention. erating digital RGB signals
• Video input processors (SAA7113, SAA7114 and SAA7118E)
Today, LCD technology offers an exciting alternative to yester- for generating digital YUV signals
day's power-hungry CRT displays. LCD devices are light-
weight, economical to use and produce very low EMI emissions Display Drivers
— and that is only the beginning. From touch-sensitive screens, As the leading supplier of display drivers for mobile phone dis-
to highly integrated "intelligent" displays with pre-programma- plays, and a major supplier to the PDA market, Philips' active
ble personal preferences, LCD promises a new experience in matrix drivers have been designed for use in a-silicon
interactive displays. (amorphous Si) and high-yield Low Temperature Poly-Silicon
(LTPS) flat panels. Philips' family of LCD display drivers pro-
It is no surprise then, that consumer interest in LCD monitors, vides solutions for both passive and active LCDs. These source
TVs and projectors is rapidly growing, and that the LCD market and gate drivers have been designed for high-speed clock opera-
potential is expected to be immense. As we move away from tion with low power consumption.
the bulky CRT "box", the future clearly belongs to innovative,
versatile and visually appealing LCDs. • PCA8850Lxx: source driver for XGA/SXGA
• PCA8851Lxx: gate driver for XGA/SXGA
Introducing Philips LCD Solutions
To help designers reach this market, Philips Semiconductors has Complete LCD Solutions
developed a complete range of powerful dedicated-display LCD Philips Semiconductors is a complete-solution resource for the
Controllers and driver ICs. LCD designer, offering designs and ICs that ensure high-perfor-
mance, low component-count and complete system solutions for
Controllers today's LCD monitor designs. And because Philips components
Central to Philips' LCD reference designs are four circuits that are designed to work together, there is no need for hardware or
provide true multi-scan capabilities with minimal PLL jitter. software "glue".
These capabilities ensure faithful reproduction of high-resolu-
tion PC and video graphics. Philips' full-system solutions include hardware, all the associated
application and testing software and full documentation. Philips
• SAA6721 - TFT-display controller for SXGA displays customers also enjoy access to extensive application support
• SAA6712(A) - TFT-display controller for XGA displays from Philips System Laboratories. Finally, Philips Flat Display
• SAA6713 - dual-input TFT-display controller for Systems' wide range of advanced TFT-LCD panels completes
XGA displays this full-service approach — ensuring that Philips customers
• SAA6714 - triple-input TFT-display controller for have all the resources they require to succeed.
SXGA displays
Philips Semiconductors Reference Designs
The SAA6713 and SAA6714 are Philips' second-generation Philips reference designs have been developed in the world-
input TFT-display controllers with state-of-the-art ClearFont class Philips Semiconductors System Laboratories (PS-SLs).
text scaling to achieve high-contrast text output: A scaling Invaluable tools for the LCD designer, these designs help
engine isolates the text from the background picture, then evaluate a chip's functionality and performance. They can
enables different methods of "context-sensitive" scaling. provide a convenient starting point for a custom design or
ClearFont text scaling generates clear scaled-text, then a morpho- a complete turnkey solution for LCD monitor or projector
logical filter is applied to the text to reduce blocking caused by designs, significantly reducing time-to-market.

1-2 LCD Displays

INTRODUCTION AND SYSTEM SOLUTIONS INTRODUCTION

1
SXGA LCD Demo Monitor (Phoenix v3.0)

Key Components
• SAA6721 SXGA TFT-display controller (page 2-4) FRAME BUFFER
(SDRAM)
• TDA8757 170 MHz 3-channel ADC (page 2-12)
• SAA7118 video input processor (page 2-16)
• P87C695 USB microcontroller (OTP, 64 Kbytes; no USB dig RGB
functionality on first board) RGB TDA8757

• Frame buffer 4 Mbytes (3.932 Mbytes required) SAA6721

to TFT
panel
dig YUV
Video SAA7118

I2C

P87C695

USB
DDC

MSD545

SXGA LCD demo monitor (ver. 3.0)

XGA LCD Demo Monitor (Phoenix v1.0)

Key Components FRAME BUFFER

• SAA6712(A) XGA TFT-display controller* (pages 2-3, 4) (SDRAM)
optional
• TDA8752 100 MHz RGB 3-channel (R, G, and B) ADC
(pages 2-11)
• SAA7113 (for YUV input) RGB
dig RGB
TDA8752
• P87C695 microcontroller
to TFT
SAA6712(A) panel
dig YUV
* If the YUV function is not necessary, SAA6712 can be used Video SAA7113
instead. In this case, a frame buffer is not required.
I 2C

P8xC695

DDC

MSD544

XGA LCD Demo Monitor (Phoenix v1.0)

LCD Displays 1-3

 INTRODUCTION AND SYSTEM SOLUTIONS SYSTEM SOLUTIONS

1 Dual-Input XGA LCD Demo Monitor

Key Components
• SAA6713 XGA TFT-display controller (page 2-6)
• P89C664 microcontroller
RGB
to TFT
SAA6713 panel
DVI

I 2C

89C664

MSD546

Dual-Input XGA LCD Demo Monitor

Triple-Input SXGA LCD Demo Monitor

Key Components
FRAME BUFFER
• SAA6714 SXGA TFT-display controller (page 2-8) (DDR SDRAM)
• SAA7118 video input processor (page 2-16)
• P89C664 microcontroller
RGB

to TFT
DV1 SAA6714 panel

Video SAA7118

2
I C

P89C664

MSD544A

Triple-input SXGA LCD demo monitor

1-4 LCD Displays

 2

SIGNAL PROCESSING
AND CONTROL

LCD Displays 2-1

 SIGNAL PROCESSING AND CONTROL TFT-DISPLAY CONTROLLERS

SAA67xx LCD Scaler Family

TABLE 1 TFT-DISPLAY CONTROLLERS

Type number SAA6712 SAA6712A SAA6721 SAA6713 SAA6714
RGB graphical standard XGA XGA SXGA XGA SXGA
2 Integrated ADC PLL (clamp, AGC) – – – yes yes
Integrated DVI compliant TMDX Rx – – – yes yes
RGB digital input 24 or 48-bit 24 or 48-bit 24 or 48-bit – –
YUV digital input – 24 or 48-bit 24 or 48-bit – –
Pixel frequency (MHz) 110 110 200 110 135(160)
Max. resolution 1024x768 1024x768 1280x1024 1024x768 1280x1024
Color adjustment yes (8-bit) yes (8-bit) yes (8-bit) yes (10-bit) yes (10-bit)
Automatic adjustment for clock, phase,
horizontal/vertical-offset, and video mode yes yes yes yes yes
I2C interface yes yes yes yes yes
Horizontal and vertical scaling up/down scaling up/down scaling up/down scaling up/down scaling up/down scaling
Built-in OSD (character matrix) 24×24 or 12×16 24×24 or 12×16 24×24, 16×16 or 12×16 8x8 up to 32x32 8x8 up to 32x32
Built-in memory control yes yes yes no no
Package BGA292 BGA292 BGA292 PQFP160 BGA292

Advantages of SAA6712/12A/21 TFT-Display Controllers

■ Three different de-interlacing algorithms: static ■ Independent horizontal and vertical up/down
mash, spatial- and motion-compensated scaling with programmable transition curve for
■ Fully programmable scaling characteristic, making each upscaler and additional programmable
adaptive scaling possible sharpening filter
■ Fully programmable memory and panel clock, ■ Full programming of panning, color look-up table
giving flexible adaptation to panel/memory and border colors
■ Full programming of RAM-based OSD ■ SAA6712/12A/21 are pin- and software-compatible
■ Auto-adjustment out of data stream

Free programmable transition function

pixel repetition MSC948
100% A,
Input frame 0% B

A B intensity

linear interpolation

A1 A2 B1 B2

40% 60% S-curve

A B 0% A,
100% B
Scaled output
100% A, phase 0% A,
0% B 64 values 100% B
40% A, 60% B

Scaling algorithm of SAA6712/12A/21 series TFT-display controllers

With the SAA6712/12A/21 series, the scaling ratios and the (see graph above), and makes it possible to program for every
scaler characteristics are fully programmable. To determine the function expressible by the 64 values. The I2C bus can be used
scaling transition curve, each circuit uses two sets of 64 registers, for quick re-programming of the register set, making it easy to
one each for horizontal and vertical scaling. This makes pixel optimize the scaler characteristic according to the input picture
repetition, linear interpolation and S-curve functions possible and/or scaling ratio.

2-2 LCD Displays

SIGNAL PROCESSING AND CONTROL TFT-DISPLAY CONTROLLERS

SAA6712
RGB input Video output
■ Digital 24- or 48-bit RGB input ■ Single-pixel/clock (24-bit) or double-pixel/clock
■ Maximum pixel frequency of 110 MHz (48-bit) digital RGB output
■ Maximum resolution to 1024x768 pixels for ■ Supports Panel Link and LVDS technology 2
interlaced or non-interlaced video ■ Generates synchronization and validation signals
■ Detection of present or non-present sync signals for the TFT display
and their polarities ■ Frame-rate control for displaying true-color
■ Programmable pulses for ADC-clamping and graphics on high-color displays
ADC-gain control
■ Extra functions to ease and enhance the automatic The SAA6712 is a single-chip XGA RGB-to-TFT-display
adjustment of clock, phase, horizontal/vertical controller. It accepts the digital RGB data stream, along with
offset, and color correction the horizontal and vertical sync pulses, of a standard graphics
■ Measurement of incoming horizontal/ card, and converts them into a format suitable for TFT displays.
vertical frequency All configuration settings are controllable via an I2C bus, and
all standard resolutions (up to the resolution of the connected
display) are supported.
Video processing
■ Color correction look-up table
The SAA6712 accepts 24- or 48-bit resolution RGB inputs.
■ Fully programmable scaling ratios with adaptable
It also offers automatic adjustment for the following: clock,
scaling characteristics phase, horizontal/vertical offset and video mode sync, horizon-
■ Built-in frame memory interface for full tal/vertical up/down scaling and color correction. An external
multi-sync support microcontroller supports detection of resolution and timing.

On-screen display (OSD) As a low-cost version of the SAA6721, the SAA6712 has no
■ Character-based internal OSD YUV input and is optimized for XGA. (The SAA6712 can
■ Programmable character matrix sizes of 24x24 support SXGA, but data processing is not available.) The
or 12x16 SAA6712 is pin-compatible with the SAA6712A and
■ Programmable width and height of OSD window SAA6721 and is housed in a space-saving BGA292 package.
■ Overlay port for external OSD controller

SAA6712 EXTERNAL
MEMORY

RGB FRAME to TFT

MEMORY COLOR OSD CTRL/ OUTPUT
INPUT SCALER RATE panel
CTRL CORRECTION OV PORT INTERFACE
INTERFACE CTRL

GLOBAL CONTROL UNIT

MODE/ AUTO
SYNC. ADJUSTMENT I 2C
DETECTION CTRL SLAVE
SAA6712

MSC885

LCD Displays 2-3

 SIGNAL PROCESSING AND CONTROL TFT-DISPLAY CONTROLLERS

SAA6712A

XGA RGB/YUV to TFT-Display Controller

The SAA6712A is a single-chip XGA TFT-display controller
2 that converts digital RGB and YUV data into TFT-compatible
video signals. It has the same specifications as the SAA6712 XGA
controller with the addition of YUV circuitry identical to that of
the SAA6721 SXGA controller. The IC is housed in a space-
saving BGA292 package, making it pin-compatible with both
the SAA6712 and SAA6721. Its Block Diagram is the same as
the SAA6721.

SAA6721

SXGA RGB/YUV to TFT-Display Controller Video processing

■ Color correction look-up table
RGB input ■ Fully programmable scaling ratios with adaptable
■ Digital 24- or 48-bit RGB input scaling characteristics
■ Maximum pixel frequency of 200 MHz ■ Built-in frame memory interface for full
■ Maximum resolution to 1280x1024 pixels for multi-sync support
interlaced or non-interlaced video
■ Detection of present or non-present sync signals On-screen display (OSD)
and their polarities ■ Character-based internal OSD
■ Programmable pulses for ADC-clamping and ■ Programmable character matrix sizes of 24x24
ADC-gain control or 12x16
■ Extra functions to ease and enhance the automatic ■ Programmable width and height of OSD window
adjustment of clock, phase, horizontal/vertical ■ Overlay port for external OSD controller
offset, and color correction
■ Measurement of incoming horizontal/
Video output
vertical frequency ■ Single-pixel/clock (24-bit) or double pixel/clock (48-
bit) digital RGB output
YUV video input ■ Supports Panel Link and LVDS technology
■ Pin sharing between YUV and RGB input port
■ Generates synchronization and validation signals
■ YUV to RGB color space conversion for the TFT display
■ YUV 4:4:4 and YUV 4:2:2 with CCIR-656 codes, ■ Frame-rate control for displaying true-color
YUV 4:1:1 interlaced digital video data graphics on high-color displays
■ Maximum video input data of 50 MHz

2-4 LCD Displays

SIGNAL PROCESSING AND CONTROL TFT-DISPLAY CONTROLLERS

The SAA6721 is an advanced single-chip SXGA TFT-display The chip's multi-sync capability allows detection of the applied
controller that converts digital RGB and YUV data into TFT- graphics mode. Overlay signals can be generated via the overlay
compatible video signals. It accepts either digitized RGB with port from an external OSD controller or they can be supplied by
a color depth of 24-bit per pixel from one ADC or 48-bit per the internal OSD generator, which offers a 24x24 or 12x16 char-
double-pixel from one ADC (e.g. TDA8752/TDA8757. acter matrix and 42 (24x24) or 128 (12x16) character memory.
(See pages 2-11, 12)
The frame-rate controller allows the display of true-color
2
Alternatively, the input interface, which is compatible with pictures on high-color panels and the output interface provides
the SAA711x series of digital video decoder/capture front-end all required timing and control signals. An internal auto-
ICs, can sample both interlaced and non-interlaced YUV data, adjustment controller gives the number of black pixels after the
including CCIR-656 compatible YUV 4:2:2. horizontal sync, the number of black lines after the vertical sync,
the number of active pixels after horizontal blanking and the
Besides converting RGB and YUV signals, the SAA6721 number of active lines after vertical blanking. A mode-detection
also offers several advanced features. There are three different circuit gives the polarity of the horizontal sync, the polarity of the
de-interlacing algorithms: static mash, spatial-compensated vertical sync, the number of clocks-per-line, the number of lines-
and motion- compensated. The chip provides independent per-frame and the presence of the horizontal and vertical sync.
horizontal and vertical up/down scaling with a programmable
transition curve for each upscaler, and offers an additional Controlled via the I2C bus, the SAA6721 also has an SDRAM
sharpening filter that is fully programmable. The panning, interface to support an optional external frame buffer for full
color look-up table and border colors are also fully programmable. multi-sync capabilities. The IC is housed in a space-saving
BGA292 package and is pin-compatible with the SAA6712/12A.

SAA6721 EXTERNAL
MEMORY

RGB/YUV MEMORY FRAME to TFT

COLOR OSD CTRL/ OUTPUT
INPUT INTERFACE/ SCALER RATE panel
CORRECTION OV PORT INTERFACE
INTERFACE DE-INTERLACER CONTROLLER

YUV-TO-RGB

GLOBAL CONTROL UNIT

MODE/ AUTO
SYNC. ADJUSTMENT I 2C
DETECTION CONTROLLER SLAVE
SAA6721
MSC886

LCD Displays 2-5

 SIGNAL PROCESSING AND CONTROL TFT-DISPLAY CONTROLLERS

SAA6713
XGA Dual-Input TFT-Display Controller

Input interfaces On-screen display (OSD)

2 ■ DVI single-channel input ■ Programmable character matrix sizes from 8x8
■ Analog input, 8-bit resolution, clamp and to 32x32
automatic gain control ■ Predefined character ROM (icons etc.), including
■ Maximum resolution to1280x1024 pixels 256 characters
■ 144 built-in character-size independent generators
Input auto detection for borders and sliders
■ Detection of presence and polarities of sync signals ■ Built-in 4 Kbyte memory, for up to 512 additional
■ Measurement of horizontal and vertical update user definable/downloadable characters up to 4
frequencies colors
■ Statistical measurements to assist adjustment of ■ Freely selectable true-color sets for characters
sample clock frequency, vertical and horizontal and bit-mapped OSD
sample-offset and ADC parameters ■ 4 Kbyte bit-mapped image RAM, 2 to 16 colors
(e.g. back-drop or company logo)
Input processing ■ Programmable Alpha blending, for OSD window
■ Advanced color processing for luminance, as well as image window
separate color saturation and R, G and B ■ Cursor/pointer RAM, (enables M/S Windows-like
contrast and brightness cursor) double-buffered for animation
■ Phase-correct downscaling of any input data ■ Text attributes, i.e. shadowing, blinking, inversion,
foreground/background-transparency
Output processing
■ Upscaler with independent vertical/horizontal Output Interface
parameters ■ Single-pixel/clock (24-bit) or double-pixel/clock
■ Arbitrary upscale ratio from 1 to 64 (48-bit) digital RGB output
■ Programmable Polyphase filter supporting vari- ■ Selectable 6-bit or 8-bit per color mode
able characteristics, from smoothing to sharpening ■ Generation of synchronization and validation
■ Context-sensitive scaling via Text-Detection and signals for the TFT displays
extraction for ClearFont scaling ■ Fully programmable output timing supporting
■ Color-correction look-up table (256x10-bit, e.g. displays from virtually any manufacturer
for gamma correction) ■ Directly interfaces row and column drivers (TCON)
■ Temporal dithering for 10-bit virtual precision ■ Adjustable output timing per-port for EMI reduction
on 8- and 6-bit displays ■ Maximum resolution to 1024x768 pixels

SAA6713
HS/
VS
LLPLL
RGB
analog 3x
ADC OUTPUT
INPUT COLOR DOWN DECOUPLING UP OSD COLOR
TMDS DITHER INTERFACE
INTERFACE PROC. SCALER FIFO SCALER CTRL PROC.
DVI & TIMING
CONTROL

GLOBAL CONTROL UNIT

MODE/ AUTO
SYNC. ADJUSTMENT SAA6713 I 2C
DETECTION CONTROLLER SLAVE

2-6 LCD Displays

SIGNAL PROCESSING AND CONTROL TFT-DISPLAY CONTROLLERS

The SAA6713 is an advanced single-chip XGA TFT-display The panel interface of the SAA6713 allows adjustable port and
controller that converts analog RGB or digital RGB data, via pin ordering to minimize PCB-design and EMI issues. It sup-
a built-in DVI receiver, into TFT-compatible video signals. ports 6- and 8-bit panels and generates perfect true-color images
2
The SAA6713 is a full stand-alone TFT-display controller that via the 10-bit gamma-correction look-up table and dithering
features dual-input capability and a new scaling engine. This unit. To reduce distortion, a single pulse-width modulation
scaling engine is based on our new ClearFont technology, which output drives the back-light engine of the panel in a line-syn-
offers context-sensitive scaling for sharp and clear reproduction chronized mode.
of text, as well as a freely programmable multi-tap scaling kernal
for standard picture/video input. The IC is controlled via an I2C bus, which also supports the
new 3.4 Mbit standard. The SAA6713 comes in an easy-to-use
The on-screen displays are supported via three parts of the PQFP160 package.
built-in OSD generator (Bitmap-OSD, character-based OSD
and Icon), and there are several selectable styles and colors.
The Bitmap can be used from 2-to-16 colors per pixel. The Icon
or HW cursor supports animation. For ease of use, the charac-
ter-based portion contains 256 predefined characters and 144
generators, with the option of downloading an additional user-
definable character set.

LCD Displays 2-7

 SIGNAL PROCESSING AND CONTROL TFT-DISPLAY CONTROLLERS

SAA6714

SXGA Triple-Input TFT-Display Controller

Input interfaces ■ Nonlinear scaling to map different screen ratios
2 ■ DVI single-channel input, including High-Bandwidth (16:9 to 4:3), panorama scale, waterglass scale
Digital Content Protection (HDCP) ■ Context-sensitive scaling via Text-Detection and
■ Analog input, 8-bit resolution, clamp and automatic extraction for ClearFont scaling
gain control ■ Vertical keystone correction for projection systems
■ Parallel digital video input (YUV, CCIR656) ■ Picture in Picture display (PIP)
■ Maximum resolution to 1280x1024 pixels ■ Color-correction look-up table (256x10-bit, e.g. for
gamma correction)
Input auto detection ■ Temporal dithering for 10-bit virtual precision on
■ Detection of presence and polarities of sync signals 8- and 6-bit displays
■ Measurement of horizontal and vertical update
frequencies On-screen display (OSD)
■ Statistical measurements to assist adjustment of ■ Programmable character matrix sizes from 8x8
sample clock frequency, vertical and horizontal to 32x32
sample-offset and ADC parameters ■ Predefined character ROM (icons etc.), including
256 characters
Input processing ■ 144 built-in character-size independent generators
■ Fully programmable color matrix for borders and sliders
■ Phase-correct downscaling of any input data ■ Built-in 4 kByte memory for up to 512 additional
■ Tearing-control and frame-rate conversion user-definable/downloadable characters of up to
■ Deinterlacing with motion-adaptive filtering 4 colors.
■ Movie-detection for optimal deinterlacing ■ Freely selectable true-color sets for characters and
bit-mapped OSD
■ 4 kByte bit-mapped image RAM, 2 to 6 colors
Output processing
■ Upscaler with independent vertical/horizontal
(e.g. back-drop or company logo)
parameters ■ Programmable Alpha blending, for OSD window

■ Arbitrary upscale ratio from 1 to 64

as well as image window
■ Cursor/pointer RAM (enables M/S Windows-like
■ Programmable Polyphase filter supporting variable
characteristics, from smoothing to sharpening cursor) double-buffered for animation
■ Text-attributes, i.e. shadowing, blinking, inversion,
foreground/background-transparency

SAA6714 I 2C port

Parallel PARALLEL OUTPUT Panel

GLOBAL CONTROL COLOR
video VIDEO I 2C SLAVE DITHER TIMING port
port INTERFACE REGISTER FILES LUT
CONTROLLER

CONTENT
PROTECTION MEMORY COLOR
AUTO OSD
ADJUST TESTER MATRIX

DVI TMDS
port RECEIVER
& DLL STREAM
HORZ DYN. VERT
INPUT COLOR DEINTER- CONTROLLER
DOWN NOISE DOWN
SELECT MATRIX LACER AND
VIDEO SCALER RED. SCALER
ARBITER
INPUT PANNING
PLL AND
OVERLAY
HORZ VERT
COLOR PRE- UP
Analog 3× ADC DOWN DOWN
video MATRIX PANNING SCALER
& SYNC SCALER SCALER
port

TEST PANEL/
IMAGE POWER DDR SGRAM SAA6714
JTAG MEMORY
GENERATOR MANAGER CONTROLLER
PLL

MSD548

Memory port

2-8 LCD Displays

SIGNAL PROCESSING AND CONTROL TFT-DISPLAY CONTROLLERS

Output interface Particular attention is paid to the quality of up and down scaling.
■ Single-pixel/clock (30-bit) or double-pixel/clock A fully programmable Polyphase Filter allows for variable charac- 2
(48-bit) digital RGB output teristics, from smoothing to sharpening, during the upscale. For
■ Selectable 6-bit or 8-bit per color mode high-contrast text scaling, a sophisticated algorithm has been
■ Generates synchronization and validation signals implemented that first isolates the text from the background,
for the TFT displays enabling different methods of scaling (context-sensitive) for the
■ Freely programmable output timing, supporting
text and the background. After scaling both data sources, they
displays of virtually any manufacturer are merged together, resulting in a perfect text contrast in front
of the background. (See figure below.)
■ Directly interfaces row and column drivers
(TCON)
For video applications, the SAA6714 offers a dedicated parallel
■ Adjustable output timing per-port for
YUV input and sophisticated deinterlacing algorithms. The user
EMI reduction can choose between several modes of deinterlacing - pure tempo-
■ Maximum resolution to 1280x1024 pixels ral, pure spatial or motion adaptive filtering. A Dynamic Noise
Reduction (DNR) filter additionally improves the picture quality
Memory interface compared to other solutions in the market. The Picture in Picture
■ Frame-rate conversion with single or double (PIP) capability of the SAA6714 allows display of a second video
buffering stream within a scalable window on top of the primary data
■ 32-bit wide DDR SDRAM/SGRAM interface sources. This can be used to display TV applications, such as
enabling up to 1.14 GB/s bandwidth news, within a window on top of the working display area.
■ Supports 1 Mx32, 2 Mx32 and 4 Mx32 devices Sophisticated color management, including a 10-bit gamma-
with DLL correction function and temporal dithering for 10-bit virtual
■ SSTL-2 input/output drivers precision on 8- and 6-bit displays, further improve visual quality.
■ Operation without external memory if frame
A vertical keystone correction allows projector manufacturers to
rate conversion is abandoned
upgrade their solutions. An integrated feature-rich OSD function-
ality adds another way for differentiation. Character-based OSD
The SAA6714 is a highly-integrated triple-input LCD controller
with predefined (256 Byte) and programmable font (4 kByte),
IC, which incorporates an analog VGA input, a parallel YUV
along with a bit-mapped graphical OSD (4 kByte), allow the
input and a Digital Video Input (DVI 1.0 compliant). The
implementation of a smart and user-friendly graphical interface.
SAA6714 includes all the functions necessary for processing
and measuring the incoming data of an SXGA LCD monitor
Besides single-pixel/clock (30-bit) or double-pixel/clock (48-bit)
or projector.
digital RGB output, the SAA6714 can directly interface to row
and column drivers from virtually any manufacturer by integrat-
ing a fully programmable output timing controller (TCON).

Graphic
Graphic
Scaling
Detection
& FIR

What a beautiful
Flower What a beautiful
Flower

Text Text
What a beautiful
Detection Flower Scaling
& Filer MSD549

Example of context sensitive scaling

LCD Displays 2-9

 SIGNAL PROCESSING AND CONTROL TFT-DISPLAY CONTROLLERS

Summary of SAA6713/14 Special Features

Scaling Algorithm Motion-adaptive De-interlacer

The SAA6713 and SAA6714, Philips provides state-of-the-art (SAA6714 only)
ClearFont text scaling for high-context text output. The scaling In SAA6714, there are 3 different de-interlacing algorithms
2 engine first isolates the text from the background picture, then implemented:
enables different methods of scaling (context-sensitive). For ■ Spatial de-interlacer (ideally suited for
the background picture, a fully programmable Polyphase filter motion pictures)
allows for variable characteristics, from smoothing to sharpen- ■ Temporal de-interlacer (ideally suited for
ing, to be applied during upscaling. For text, ClearFont text still pictures)
scaling is applied to generate clear scaled text output. A morpho- ■ Motion-adaptive de-interlacer
logical filter is also applied to the scaled text to reduce blocking
caused by large scale-factors. At the final stage, both the text and
The motion-adaptive de-interlacer employs filters ideally suited
background picture are combined to generate the final output
for motion and stationary content and switches/blends between
(See figure on page 2-9.)
them based on motion detection.
Fancy OSD Movie Detection (SAA6714 only)
Key Features of the OSD in SAA6713/14
If the video contents come from a movie title, there will be some
■ Freely programmable character matrix sizes from
repetitive pattern when observing a few consecutive fields. The
8x8 to 32x32 de-interlacer in SAA6714 can detect this kind of characteristic
■ Predefined character ROM (icons etc.), including and can switch to field insertion for better de-interlacing.
256 characters
■ 144 built-in character-size independent generators Built-in TCON (Timing CONtrol)
for borders and sliders Besides the general TTL panel-interface, the SAA6713/14 also
■ 4 kByte memory for up to 512 additional user integrate TCON to allow direct drive of the row and column
definable/downloadable characters drivers in the panel. The output interface has 10 programmable
■ Freely selectable true-color sets for characters and control-signal ports to the panel (CGS0, CGS1, … CGS9).
bit-mapped OSD These control signals are generated via Configurable Signal
■ 4 kByte bit-mapped image RAM, 2 to 16 colors Generators (CSG). By programming these CSGs, one can easily
(e.g. back-drop or company logo) generate the timing signals required for driving the row and
■ Freely programmable Alpha blending, for OSD
column drivers of almost any LCD panel.
window as well as image window
■ Cursor/pointer RAM enables M/S Windows-like
cursor
■ Text attributes, i.e. shadowing, blinking, inversion,
foreground/background-transparency

The OSD block diagram is shown below.

WINDOW OSD FONT

RAM 1024 CTRL RAM
CHARACTER 4k BYTE

CHARACTER POINTER/ IMAGE

ROM CURSOR RAM
512 BYTE RAM 2k BYTE

I 2C

OSD block diagram

2-10 LCD Displays

SIGNAL PROCESSING AND CONTROL RGB A-TO-D CONVERSION

TDA8752

Triple High-Speed Analog-to-Digital

Converter (ADC)

■ Triple 8-bit ADC This triple high-speed 8-bit ADC is designed to convert RGB 2
■ Sampling rate up to 110 MHz signals received from a PC or workstation into data used by an
■ 100 MSPS peak-to-peak jitter at 2 ns LCD driver (with pixel clock up to 110 MHz). All the IC set-
tings, including the clamp level and gain, are controlled via either
■ Controllable via serial interface: either I2C bus or
an I2C bus or a 3-wire serial bus, selected via a logic input.
3-wire, selected via a TTL input pin
■ Analog voltage input from 0.4 V to 1.2 V (p-p) giving
If several TDA8752 ICs are used in a system, its serial-bus address
full-scale ADC input
can be set between four fixed values using the I2C-interface (e.g.
■ Three independent clamps for programming a clamp- two ICs used in an odd/even configuration). The IC includes a
ing code between -63.5 and +64 in steps of 1/2 LSB PLL that can be locked on the horizontal line frequency to gener-
■ Three controllable amplifiers, gain controlled via ate the ADC clock, thus minimizing PLL jitter for high-resolution
serial interface, giving a full-scale resolution of 1/2 PC graphics applications. An external clock can also be applied to
LSB peak-to-peak the ADC.
■ 250 MHz amplifier bandwidth
■ Low gain variation with temperature
■ PLL, controllable via serial interface to generate the QUICK REFERENCE DATA
ADC clock, which can be locked to a line frequency
Power supply 5V
from 15 kHz to 280 kHz
Analog supply current 120 mA
■ Integrated PLL divider
■ Programmable phase clock adjustment cells Digital supply current 40 mA
■ Internal voltage regulators Total power dissipation 1W
■ TTL-compatible digital inputs and outputs Amplifier bandwidth 250 MHz
■ Chip-enabled high-impedance ADC output Maximum clock frequency TDA8752H/6 60 MHz
■ Power-down mode TDA8752H/8 110 MHz
■ Possibility of using up to four ICs in the same Package QFP100
system using the I2C-bus interface, or more,
using the 3-wire serial interface

CLP

TDA8752
RAGC RCLP
RGAINC RBOT

RIN CLAMP R0 to R7
RDEC
MUX OUTPUTS
ADC
Vref ROR
RED CHANNEL
GAGC GCLP
GGAINC GBOT

GIN G0 to G7
GREEN CHANNEL
GDEC GOR

OE
BAGC BCLP
BGAINC BBOT

BIN B0 to B7
BLUE CHANNEL
BDEC BOR

TDO
CKADCO
TCK HSYNCI TDA8752 CKBO
ADD2
ADD1 SERIAL CKAO
INTERFACE
SEN I2C-BUS CKREFO
REGULATOR
SCL OR
3-WIRE CKEXT
SDA PLL
I2C-bus; 1-bit INV
DIS
(H level)
I2C/3W COAST
CKREF

MGG363
HSYNC DEC1 DEC2 PWDWN CP CZ

LCD Displays 2-11

 SIGNAL PROCESSING AND CONTROL RGB A-TO-D CONVERSION

TDA8757

Triple 8-bit ADC 170 Msps ■ TLL-compatible digital inputs and outputs
■ Outputs on one port or demultiplexed on two
■ Triple 8-bit ADC ports, selectable via serial interface
2 ■ Sampling rate to 170 Msps ■ Chip-enable, high-impedance ADC output
■ IC-controllable via a serial interface, which can be ■ Power-down mode
either I2C bus or 3-wire serial bus, selected via a
TTL input pin The TDA8757 is a high-speed triple 8-bit ADC designed to
■ Three clamps for programming a clamping code convert large bandwidth RGB signals received from an analog
from -63.5 to +64 by steps of 1/2 LSB and from source into digital data used by an LCD driver. It supports dis-
+120 to +136 by steps of 1/2 LSB play resolutions up to 1600x1200 (VGA to UXGA) at 60 Hz.
■ Three controllable amplifiers, gain controlled via
serial interface to produce a full-scale resolution The IC also includes a PLL that can be locked on the
of 1/2 LSB peak-to-peak horizontal line frequency and that generates the ADC clock.
■ Amplifier bandwidth of 250 MHz This ensures PLL jitter is minimized for high-resolution PC
■ Low gain variation with temperature graphics applications.
■ PLL controllable via serial interface, to generate
the ADC clock, which can be locked on any line Outputs are available on one port up to 110 Msps, or on two
frequency from 15 kHz to 150 kHz ports up to 170 Msps. The operating mode is selectable via the
■ Integrated PLL divider serial interface (either I2C bus or 3-wire serial bus) using a logic
input. The clamp level, gain and other settings are controllable
■ Programmable phase-clock adjustment cells
via serial interface. An external clock signal can be used to clock
■ Internal voltage regulators the ADC.

TDA8757
AGCR CLP CLPR

GAINCR BOTR

INR CLAMP O 8
DECR U A0R-A7R
T 8
MUX ADC B0R-B7R
P
U ORR
VREF RED CHANNEL T

OE
AGCG CLPG
GAINCG BOTG
8
A0G-A7G
ING 8
GREEN CHANNEL B0G-B7G
DECG
ORG

AGCB CLPB
GAINCB BOTB
8
A0B-A7B
INB 8
BLUE CHANNEL B0B-B7B
DECB
ORB

HSYNCI
CKADCO

A1 TDA8757 CKDATA
A2 1-bit CKREFO
SEN SERIAL (H level)
SCL INTERFACE PLL CKEXT
SDA (I2C- 3W) REGULATOR INV
DIS COAST
2
I C/3W I2C-bus CKREF

FCE694

HSYNC DEC1 DEC2 PD CZ CP

2-12 LCD Displays

SIGNAL PROCESSING AND CONTROL VIDEO INPUT PROCESSORS

SAA7113
Video Input Processor

■ Four analog inputs, internal analog source selec- ■ User-programmable luminance peaking or

■
tors (e.g. 4xCVBS or 2xY/C or 1xY/C and 2xCVBS)
Two analog pre-processing channels ■
aperture correction
Cross-color reduction for NTSC by chrominance
2
■ Fully programmable static gain or automatic gain comb filtering
control for the selected CVBS or Y/C channel ■ PAL delay line for correcting PAL phase errors
■ Switchable white peak control ■ On-chip Brightness Contrast Saturation (BCS)
■ Two built-in analog anti-aliasing filters and Hue control
■ Two 9-bit video CMOS ADCs, digitized CVBS or
Y/C signals available on the VPO-port via I control The SAA713 combines a two-channel analog pre-processing
■ On-chip clock generator circuit (with source selection, anti-aliasing filter and ADC), an
■ Line-locked system clock frequencies automatic clamp and gain control, a Clock Generation Circuit
(CGC), a digital multi-standard decoder, a brightness
■ Digital PLL for horizontal sync processing and
contrast/saturation control circuit, a multi-standard VBI data
clock generation
slicer and a 27 MHz VBI-data bypass. The decoder is based on
■ Horizontal and vertical sync detection
the line-locked clock decoding principle and can decode PAL,
■ Requires only one crystal (24.576 MHz) for SECAM and NTSC color signals into CCIR-601-compatible
all standards color component values. The SAA7113 accepts CVBS or S-
■ Automatic detection of 50/60 Hz field frequency video (Y/C) from TV or VTR sources.
and automatic switching between PAL and NTSC
standards QUICK REFERENCE DATA
■ Luminance and chrominance signal-processing for Analog and digital supply voltage 3.3 V (5 V compatible)
PAL BGHI, PAL N, Combination-PAL N, PAL M, Analog and digital power 0.5 W
NTSC M, NTSC N, NTSC 4.43, NTSC-Japan and
I2C-bus controlled Yes
SECAM
Package QFP44

SAA7113
MULTI-STANDARD DATA SLICER

4
AI11 VBI-DATA BYPASS 12, 13,
5 ANALOG UPSAMPLING FILTER 14, 15,
AI1D PROCESSING
7 19, 20,
AI12 AND 21, 22 VPO7
bypass OUTPUT
9 to
AOUT ANALOG TO FORMATTER
43 VPO0
AI21 DIGITAL
UV
44 CONVERSION CHROMINANCE
AI2D CIRCUIT Y
1
AI22 C/CVBS
AD2 AD1 AND
6 BRIGHTNESS CONTRAST
AGND SATURATION CONTROL
SAA7113

CON

ANALOG Y I2C-CONTROL
PROCESSING
CONTROL Y/CVBS I2C-BUS 23
LUMINANCE SDA
INTERFACE
CIRCUIT 24
SCL
2, 41
VSSA1, VSSA2
Y
3, 42
VDDA1, VDDA2

38 31
TDI TEST CLOCKS
37 XTAL
CONTROL BLOCK CLOCK 32
TCK
39 FOR GENERATION XTALI
SYNCHRONIZATION
TMS BOUNDARY CIRCUIT
8 CIRCUIT
TRST SCAN TEST
AND POWER-ON 17
36 LFCO LLC
TDO SCANTEST CONTROL

18, 29, 33, 34 16, 28, 30, 35 26 27 25 10 11 40

MSC947

VDDDE, VDDDI, VSSDE, VSSDI, RTS0 RTS1 RTCO VDDA0 VSSA0 CE

VDDDA VSSDA

LCD Displays 2-13

 SIGNAL PROCESSING AND CONTROL VIDEO INPUT PROCESSORS

SAA7114

Video Decoder with Comb Filter and

High-performance Scaler
2 ■ Six analog inputs, internal analog source selectors The SAA7114 captures and scales video images and outputs a
(e.g. 6xCVBS or (2xYC and 2xCVBS) or (1xYC digital video stream to the image port of a VGA controller. The
and 4xCVBS) video stream can be displayed via a VGA frame buffer or can be
■ Two analog pre-processing channels captured by system memory.
■ Fully programmable static gain or automatic-gain
control for the selected CVBS or Y/C channel The decoder is based on the line-locked clock decoding principle
and is able to decode the color of PAL, SECAM and NTSC
■ Switchable white peak control
signals into ITU-601-compatible color component values.
■ Automatic Clamp Control (ACC) for CVBS, Y & C
The IC accepts analog CVBS or S-video (Y-C) inputs from
■ Two 9-bit video CMOS ADCs, digitized CVBS or TV or VCR sources, even weak and distorted signals. An
Y/C signals available on the expansion port expansion port, for digital video (bi-directional half duplex,
■ On-chip Line-Locked Clock Generator according DI compatible), is also supported for connection to an MPEG
to ITU-601 or video-phone CODEC. The SAA7114 supports 8-bit (16-bit)
■ Requires only one crystal (32.11 MHz or 24.576 wide output data at the image port, with auxiliary reference data
MHz) for all standards for interfacing to VGA controllers.
■ Automatic detection of 50/60 Hz field frequency
and automatic switching between PAL and NTSC The SAA7114 also incorporates a field-locked audio clock
standards generator, which ensures there is always the same number
■ Adaptive 2/4-line comb filter for two-dimensional of audio samples associated with a field or set of fields. This
chrominance/luminance separation prevents the loss of synchronization between video and audio
– Increased luminance and chrominance band during capture or playback.
width for all PAL and NTSC standards
– Reduced cross-color and cross-luminance The circuit can be controlled via the I2C bus with full write/read
artifacts capability for all programming registers.
■ Luminance and chrominance signal-processing
for PAL BGDHIN, Combination-PAL N, PAL M,
NTSC M, NTSC-Japan, NTSC 4.43 and SECAM QUICK REFERENCE DATA
■ Digital PLL for synchronization and clock Analog and digital supply voltage 3.6 V
generation from all standard and non-standard I2C-bus controlled Yes
video sources Package LQFP100
■ Horizontal and vertical up and down video scaling
to randomly-sized windows
■ Versatile VBI-data decoder, slicer, clock
regeneration and byte synchronization, e.g.
for WST, NABST, Close Caption, WSS, etc.
■ Anti-alias and accumulating filter for
horizontal scaling
■ Two independent programming sets for scaler
part to define two "ranges" per field or sequence
over frames
■ Best-in-class video scaler

2-14 LCD Displays

 SAA7114

Note:

LCD Displays
The pins RTCO and ALRCLK
XPD7 to are used for configuration
LLC RTCO RTS1 XCLK XPD0 XRV XTRI TEST4 TEST2 TEST0 of the I2C interface and the
definition of the crystal
LLC2 RTS0 XDQ XRH XRDY HPD7 to HPD0 SDA SCL TEST5 TEST3 TEST1 oscillator frequency at RESET.

RT OUT EXPANSION PORT PIN MAPPING I/O CONTROL I 2C

D1 OUT D1 IN chroma of 16 bit out

chroma of 16 bit input

from event controller
R/W CONTROL

PROGRAMMING A/B
X PORT REGISTER REG.
INPUT FORMATTER ARRAY MUX
(SELECT)
RESON CLOCK
CE GENERATION
data, clock, H, V, FID SLEEP MODE REGISTER to clock generation
XOUT AND
and qualifier
SIGNAL PROCESSING AND CONTROL

XTALI POWER ON
XTAL CONTROL SET_RAW
SET_VBI VERTICAL
SCALING
AI11 HORIZONTAL
DIGITAL INPUT FIR-PREFILTER BCS LINE PROCESSOR
AI12 FINE
DECODER 4:2:2 ACQ. AND CONTROL FIFO INCLUDING
AI21 ANALOG (PHASE)
WITH OUTPUT CONTROL PRESCALER SCALER BUFFER LINE
AI22 DUAL SCALING
ADAPTIVE INTER- MEMORY
AI23 ADC
COMB FACE 1H * 16 BIT
AI24
FILTER
AOUT to
A/B IPD7 to
TRSTN Reg. IPD0
TCK BOUNDARY DATA MUX IDQ
TMS SCAN TYPE OUTPUT YUV
EVENT VIDEO IGPH
TDI TEST ACQ. OUTPUT
CONTROLLER FIFO
TDO CONTROL FORMATTER 32 IMAGE IGPV
TO PORT
IGP0
AUDIO 8(16) PIN
MASTER GENERAL MUX
AMCLK V ref. int TEXT MAPPING IGP1
PURPOSE TXT
CLOCK
VBI DATA INTERFACE FIFO ICLK
GENERATION V ref. ext
SLICER
raw ADC data, ITRDY
clock, H, V
ALRCLK AUDIO and qualifier ITRI
BIT CLOCK VIDEO/TEXT
ASCLK line control ARBITER
WORD SELECT registers
AXMCLK GENERATION

MSC949
VIDEO INPUT PROCESSORS

2-15
2
 SIGNAL PROCESSING AND CONTROL VIDEO INPUT PROCESSORS

SAA7118

Multi-standard Video Decoder with

Adaptive Comb Filter and Component
2 Video Input

■ Sixteen analog CVBS, split as desired (all of the Designed for desktop video and similar VGA-based applications,
CVBS inputs can optionally be used to convert, the SAA7118 is a highly integrated circuit that combines a
e.g. Vestigial Side Band (VSB) signals) four-channel analog processing circuit with a high-performance
■ Eight analog Y + C inputs, split as desired scaler. The preprocessing circuit offers a source selector, an anti-
■ Four analog component inputs, with embedded aliasing filter and ADC, automatic clamp and gain control, a
or separate sync, split as desired Clock Generation Circuit (CGC) and a digital multi-standard
■ Four on-chip anti-aliasing filters in front of the decoder. The decoder provides two-dimensional chrominance/
Analog-to-Digital Converters (ADCs) luminance separation through an adaptive comb filter. The
higher-performance scaler offers variable horizontal and vertical
■ Digital PLL for synchronization and clock
up/down scaling and a control circuit for brightness, contrast
generation from all standard and non-standard
and saturation.
video sources, e.g. consumer-grade VTR
■ Automatic detection of any supported The decoder is based on the principle of line-locked clock
color standard decoding and is able to decode the color of PAL, SECAM and
■ Luminance and chrominance signal-processing NTSC signals into ITU 601-compatible color component val-
for PAL BGDHN, Combination PAL N, PAL M, ues. The SAA7118 accepts, as analog inputs, CVBS or S-video
NTSC M, NTSC-Japan, NTSC 4.43 and SECAM (Y/C) from TV or VCR sources, (even weak and distorted sig-
■ Adaptive 2/4-line comb filter for two-dimensional nals), as well as baseband component signals Y-PB-PR or RGB.
chrominance/luminance separation, also with An expansion port (X port) for digital video (bi-directional half
VTR signals duplex, DI compatible) is also supported, for connection to an
■ RGB component inputs MPEG or video-phone CODEC. At the image port (1 port),
■ Y-PB -PR component inputs the SAA7118 supports 8- or 16-bit wide output data, with
■ Digital RGB-to-Y-CB -CR matrix auxiliary reference data for interfacing to VGA controllers.
■ Horizontal and vertical down-scaling and
up-scaling to randomly sized widows
■ Anti-alias and accumulating filter for horizontal
QUICK REFERENCE DATA
scaling
Analog and digital supply voltage 3.3 V (5 V compatible)
■ Two independent programming sets for scaler
part, to define two "ranges" per field or sequences I2C-bus controlled Yes
over frames Package BGA156, QFP 160
■ Brightness, contrast and saturation controls for
scaled outputs
■ Software-controlled power saving standby
modes supported

2-16 LCD Displays

SIGNAL PROCESSING AND CONTROL VIDEO INPUT PROCESSORS

SAA7118
CLKEXT RES

ADP[8:0] CE TEST SDA SCL INT_A

CONTROL
AD PORT

FSW
IIC REGISTER MAP

SAA7118
FIRST TASK IIC REGISTER MAP SCALER

SECOND TASK IIC REGISTER MAP SCALER

2
AI11
FAST SWITCH DELAY SCALER EVENT CONTROLLER
AI12
ANALOG1
AI13 +
AI14 R Y
ADC1 COMPONENTS
G CB
AI1D
B PROCESSING CR IGP1
AI21

LINE FIFO BUFFER

(PHASE) SCALING

VERTICAL SCALING
HORIZONTAL FINE
DECODER OUTPUT CONTROL
IGP0

BCS-SCALER

FIR-PREFILTER

OUTPUT FORMATTER I PORT

AI22 S
ANALOG INPUT CONTROL

PRESCALER
RAW

VIDEO FIFO
ANALOG2 IGPV
AI23
+ IGPH
AI24 ADC2 CHROMINANCE CB Y-CB-CR
IPD[7:0]
AI2D C PROCESSING CR
AI31
ICLK
AI32
ANALOG3 COMB FILTER IDQ
AI33
+ ITRDY
AI34 ADC3 Y
LUMINANCE Y ITRI
AI3D S
AI41 PROCESSING RAW TEXT
AI42 S Y-CB-CR VBI-DATA SLICER FIFO
ANALOG4
AI43 + S S
AI44 ADC4 SYNCHRONIZATION
VIDEO/TEXT ARBITER
AI4D CB-CR CB-CR
AOUT Y-CB-CRS
AGND POWER-ON CONTROL VIDEO AUDIO
GPO CRYSTAL X PORT H PORT BOUNDARY SCAN
AGNDA POWER SUPPLY CLOCK CLOCK

VSSA VSSD VDD(xtal) LLC RTS0 RTCO XTALI XRDY XCLK XRH XTRI HPD[7:0] AMCLK ASCLK TDI TCK
VSS(xtal)
AMXCLK
VDDA VDDD LLC2 RTS1 XTAL XTOUT XPD[7:0] XDQ XRV TDO TRST TMS
ALRCLK

LCD Displays 2-17

 SIGNAL PROCESSING AND CONTROL MEMORIES

Philips Semiconductors offers a wide range of EEPROMs.

The two types featured here are ideal as frame buffers for
the SAA6721 TFT-display controllers. They are pin- and
address-compatible and can be used in the SXGA LCD
monitor reference designs shown on pages 1-3 and 1-4.
2
PCF8598C-2/PCF85116-3

CMOS EEPROMs with I2C Interface

■ Non-volatile storage of: The PCF8598C-2 and the PCF85116-3 are low-power
CMOS EEPROMs offering non-volatile storage of 8 kbits
– 8 kbits organized as 1024x 8-bit (PCF8598C-2)
(1024 x 8-bit) and 16 kbits (2048 x 8-bit), respectively.
– 16 kbits organized as eight blocks of 256 x 8-bit
each (PCF85116-3)
Both devices keep power consumption to a minimum by
■ Maximum operating current: making full use of CMOS technology. Chip count is also
– 4.0 mA (PCF8598C-2) kept to a minimum, because the Erase/Write cycle is performed
– 1.0 mA (PCF85116-3) internally, and the programming voltage is generated on-chip.
■ Typical standby current 4 mA Both devices offer excellent reliability because redundant storage
■ Single supply with full operation down to: cells are made fault-tolerate to single-bit errors.
– 2.5 V (PCF8598C-2)
– 2.7 V (PCF85116-3) Innovative use of redundant storage cells gives these EEPROMs
excellent reliability. In the PCF8598C-2, redundant storage cells
■ On-chip voltage multiplier
are made fault-tolerant to single-bit errors. In the PCF85116-3,
■ Serial input/output I2C the cells are, in most cases, fault-tolerant to multi-bit errors as well.
■ Sequential and random read operations
■ Write operations: The PCF8598C-2 and PCF85116-3 are pin- and address-
– byte write-mode and 8-byte page write mode compatible.
(PCF8598C-2)
– multi-byte write-mode up to 32 bytes
(PCF85116-3)
■ Power-on reset
■ High reliability by using redundant storage cells
■ Endurance: 1000000 Erase/Write cycles at
Tamb = 22°C
■ Internal timer for writing (no external
components)
■ Both pin- and address-compatible

QUICK REFERENCE DATA PCF8598C-2 PCF85116-3

Non-volatile storage 8 kbits (1024 × 8-bit) 16 kbits (2048 × 8-bit)
Supply voltage 2.5 to 6.0 V 2.7 to 5.5 V
Supply current (read) 200 µA @ 6.0 V 1.0 mA @ 5.5 V
Supply current (E/W) 4 mA @ 6.0 V 1.0 mA @ 5.5 V
Standby current 3.5 µA @ 6.0 V 10 µA @ 5.5 V
10 µA @ 6.0 V, typical 4 µA 6 µA @ 2.7 V
Package DIP 8 (SOT-97-1), SO8 (SOT-176-1) DIP 8 (SOT97-1), SO8 (SOT96-1)

2-18 LCD Displays

SIGNAL PROCESSING AND CONTROL MEMORIES

PCF8598C-2
SCL INPUT
FILTER I2C-BUS CONTROL LOGIC
SDA

n 2
BYTE ADDRESS DIVIDER
HIGH SEQUENCER
COUNTER ( 128)
REGISTER

ADDRESS SHIFT BYTE ADDRESS 4 EE

LATCH 8 EEPROM
SWITCH REGISTER POINTER CONTROL
(8 bytes)

A2
TIMER
A1 TEST MODE DECODER PTC
( 16)
A0

PCF8598C-2
POWER-ON-RESET OSCILLATOR

MGD927

PCF85116-3 WP

SCL INPUT
I2C-BUS CONTROL LOGIC
SDA FILTER

TEST MODE ADDRESS SHIFT ADDRESS

SEQUENCER
REGISTER COMPARATOR REGISTER POINTER

COLUMN DECODER HV
PCF85116-3 GENERATOR

PAGE REGISTER
DIVIDER

EEPROM ARRAY ROW

POWER-ON-RESET (8 × 256 × 8) DEC
OSCILLATOR

MBH922

LCD Displays 2-19

 SIGNAL PROCESSING AND CONTROL LCD GRAPHIC DRIVERS

PCA8848/PCA8849/PCA8850

TFT-LCD Source Driver for XGA and

SXGA Applications
2 ■ 384 output channels The two-stage latch allows simultaneous writing of data, while
■ 6-bit D/A converter with gamma correction the previous data stored in the second stage is converted to the
(26,2144 colors) analog output signal and drives the display source lines. With
■ 2x5 gamma-reference inputs the shift-register extension lines (PRSL and PLSR), devices can
be cascaded to accommodate various displays standards (e.g. 8
■ Dot-by-dot inversion drive
drivers for XGA, 10 drivers for SXGA or QVGA). Each device
■ Supports n line inversion (column inversion)
has a complete bi-directional data path, selectable by the RL
■ CMOS-compatible inputs input, which gives additional flexibility for the wiring of the
■ 2 x (6x3) bit high-speed parallel-input data bus panel PCB. The maximum output voltage is 9.7 V, while the
(dual-pixel bus) logic level can be as low as 2.7 V.
■ Separate data inversion control for each pixel bus
■ Selectable shift direction (L/R) With the slim-chip layout, the PCA8848/49/50 series is very
■ Cascadable device suitable for COG and Tape Carrier Package (TCP) applications.
■ Low power consumption, suitable for battery-
operated systems QUICK REFERENCE DATA
■ Fine-pitch TCP Logic supply voltage range VDD1 -VSS1 2.7 to 3.6 V
Display supply voltage range VDDH1 -VSSH1 6.5 to 9.7 V
The PCA8848, 49 and 50 is a family of high-voltage CMOS Output voltage deviation (typ) ±5 mV
ICs designed to drive up to 384 source lines of an active matrix
Maximum clock frequency 55 MHz
TFT display. The three ICs have different gamma-correction
curves. Each device consists of a 64-bit analog output buffer. Package Fine pitch TCP: 45 µm

PCA8848/PCA8849/PCA8850
Y1 Y2 Y3 Y384

POL OUTPUT BUFFER

10
VGMA10-1 D/A CONVERTER

LD DATA LATCH

6 6
R10-R15
6 6
G10-G15
6 6
LATCH/DATA

B10-B15
INVERSION

INV1
6 6
R20-R25
6 6
G20-G25
6 6
B20-B25
INV2
1 6 4
PLSR 64 bit BI-DIRECTIONAL SHIFT REGISTER PRSL

RL CLK

2-20 LCD Displays

SIGNAL PROCESSING AND CONTROL LCD GRAPHIC DRIVERS

PCA8840

TFT-LCD Gate Driver for VGA and

XGA Applications

■ Selectable 120/128 output channels with 2 levels The outputs can be switched off in three groups using 2
(VH = on/VL = off) DIS1,…DIS3. This function is used to fine-tune the gate non-
■ Drive voltage high VH up to 43 V overlapping time, as well as the sampling point of the selected
■ Drive voltage low VL down to -25 V line. All outputs can be activated simultaneously by EN="L".
The device is manufactured using n-well CMOS technology.
■ Bi-directional shift register (DIR)
Available in a slim-chip layout, the PCA8840 is well suited to
■ Fine-tuning of non-overlapping & sampling point
COG and Tape Carrier Package (TCP) applications.
with separate control lines (DIS1 to DIS3)
■ Enable-all function (EN), this pin is only available
in TCP version L1
■ Cascadable device QUICK REFERENCE DATA
Gate line driver voltage high 10 V to VVEE +43 V
The PCA8840 is a high-voltage CMOS IC designed to drive Gate line drive voltage low VVEE to VVEE +10 V
120 or 128 gate lines of a TFT-LCD display with voltages up to Power supply voltage for logic 2.4 V to 5.5 V
43 V. The device is essentially a selectable 120- or 128-bit shift Ground level voltage for logic (VVEE) –25 V to –5 V
register with high-voltage output stages. The length of the shift
Maximum operating frequency 100 kHz
register can be set with the MODE input (e.g. 4 drivers at 120
Package Fine pitch TCP: 45 µm
outputs for VGA, 6 drivers at 128 outputs for XGA).

PCA8840
OUT 126
OUT 127
OUT 128
OUT 1
OUT 2
OUT 3

VH
OUTPUT DRIVERS
VL

OUTPUT CONTROL LOGIC

VDD
GND
VEE

256-bit SHIFT REGISTER DIO2

DIR CLK MODE

LCD Displays 2-21

 SIGNAL PROCESSING AND CONTROL LCD GRAPHIC DRIVERS

PCA8851

TFT-LCD Gate Driver for XGA and

SXGA Applications
2 ■ 256 output channels OUT1 to OUT256 with The outputs can be switched off in three groups using
2 levels (VH = on/VL = off) DIS1...DIS3. This function is used to fine-tune the gate non-
■ Drive voltage high VH up to 43 V overlapping time, as well as the sampling point of the selected
■ Drive voltage low VL down to -25 V line. All outputs can be activated simultaneously by EN="L".
The device is manufactured in n-well CMOS technology.
■ Bi-directional shift register (DIR)
Available in a slim-chip layout, the PCA8851 is well suited
■ Fine-tuning of non-overlapping & sampling point
to COG and Tape Carrier Package (TCP) applications.
with separate control lines (DIS1 to DIS3)
■ Enable-all function (EN), this pin is only available
in TCP version L1
■ Cascadable device
QUICK REFERENCE DATA
The PC8851 is a high-voltage CMOS IC designed to drive 256 Gate line driver voltage high 10 V to VVEE +43 V
gate lines of a TFT-LCD display with voltages up to 43 V. Gate line drive voltage low VVEE to VVEE +10 V
The device is essentially a 256-bit shift register with high-voltage Power supply voltage for logic 2.4 V to 5.5 V
output stages. The direction of the shift register can be controlled Ground level voltage for logic (VVEE) –25 V to –5 V
by DIR. To accommodate various display standards, several Maximum operating frequency 100 kHz
devices can be cascaded with the extension lines DIO1 and DIO2
Package Fine pitch TCP: 45 µm
(e.g. 3 drivers for XGA, 4 drivers for SXGA, 6 drivers for QXGA).
OUT 254
OUT 255
OUT 256
OUT 1
OUT 2
OUT 3

PCA8851

VH
OUTPUT DRIVERS
VL

OUTPUT CONTROL LOGIC

VDD
GND
VEE

256-bit SHIFT REGISTER DIO2

MSD573
DIR CLK

Overview of TFT-LCD Display Drivers

Philips Semiconductors offers source and gate drivers for various

resolutions. These devices are available for sampling either now
or in the near future.

Resolutions Source Drivers Gate Drivers

XGA: 1024 × 768 384 channel, 6-bit, 8-bit 256 channel
SXGA: 1280 × 1024 384 channel, 6-bit, 8-bit 256 channel
SXGA+: 1400 × 1050 420 channel, 6-bit 263 channel
UXGA: 1600 × 1200 480 channel, 6-bit, 8-bit 300 channel

2-22 LCD Displays

SIGNAL PROCESSING AND CONTROL LCD GRAPHIC DRIVERS

Family of Black & White LCD Graphics Drivers

Type Display size/ Mux rates 1:n Interface bus VDD IDD VLCD
number feature (V) (V) (µA)
PCF853134x128 34, 26, 17.2 I, 400 kbps 1.5 - 5.5 200 3.0 - 9.0
PCF8558 40x101 40 I, 400 kbps 2.5 - 6.0 130 3.5 - 9.0
2
OM6211 48x84 48 / OTP serial, 4 Mbps 1.7 - 2.3 100 4.5 - 9.0
OM6213 48x84 48 / OTP serial, 4 Mbps 2.5 - 3.3 100 4.5 - 9.0
PCF8549 65x102 65 I, 400 kbps 1.5 -6.0 630 7.1 - 14.7
PCF8548 65x102 65 I, 400 kbps 1.5 - 5.5 200 4.5 - 8.5
OM6212 65x102 65 parallel, 8-bit 2.5 - 5.5 200 4.5 - 9.0
PCF8812 65x102 65 serial, 4 Mbps 2.5 - 4.5 200 4.5 - 9.0
PCF8813 68x102 9…68/OTP I, serial, parallel 1.5 - 3.3 200 max 9.0
PCF8535 65x133 65, 49, 2617 I, 400 kbps 4.5 - 5.5 160 8.0 - 16.0
PCF8811 80x128 16…80/OTP, MRA I, serial, parallel 1.5 - 4.5 150 max 9.0
PCF8820 67x101 67.8/Grey scale I, 400 kbps 2.5 - 5.5 400 4.5 - 16
PCF2113 2 lines of 12 characters I, 400 kbps 2.2 - 5.5 200 max 6.5
+ 120 icons
PCF2119 2 lines of 16 characters I, 400 kbps 2.2 - 5.5 190 max 6.5
+ 160 icons

■ Delivery form: the LCD driver-chips are available ■ Grey-scale drivers can display black and white
with gold bumps for Chip-On-Glass (COG) applica- pixels, as well as two shades of grey. This is useful
tions and are ready to package on tape like for high- or low-lighting information, or when
TCP/COF displaying pictures used in various games.
■ One Time Programmable (OTP) cells are used to ■ The character drivers PCF2113 and PCF2119 have
calibrate module parameters such as Vop, to allow an on-chip ROM with 240 different characters.
"plug-and-display", thus eliminating any tuning Sixteen additional characters can be downloaded
when inserting the display module from the equip- into RAM. The control software is minimal — since
ment manufacturer only the address of the character to be displayed is
■ Multiple Row Addressing (MRA) is an enhanced sent to the display controller/driver.
driving technology resulting in improved optical
performance, allowing use of fast-responding liquid
crystals, while reducing maximum driving voltage
and power consumption

Display sizes e.g.:

34 × 128, 48 × 84
65 × 102, 65 × 133
Data I/O 80 × 128
CONTROL
LOGIC
RAM ROW
DRIVER 09 / 02 / 01
Power SEQUENCER
supplies BIAS
VOLTAGE
VOLTAGE
MULTIPLIER COLUMN DRIVER
GENERATOR

MSD621

LCD Displays 2-23

2

2-24 LCD Displays

 3

RELATED
SYSTEMS

LCD Displays 3-1

 RELATED SYSTEMS AUDIO AMPLIFIERS

Philips offers a wide range of audio amplifiers suitable for LCD USB-controlled audio can be implemented with the UDA1321
monitor-applications, only a selection of which are given here. and the UDA1325, both of which bring the benefits of USB
From a 2x35 mW headphone driver to a 2x7 W multi-media connectivity to the digital audio module within LCD monitors.
amplifier, the ICs are designed for efficient, easy mounting The UDA1321 is a USB audio DAC, while the UDA1325 is a
and effective supply voltage ripple-rejection. The emphasis is combined ADC/DAC with DSP features and the necessary analog
on THD, S/N ratio, low DC offsets, crossover distortion, and digital functions for high-quality audio over USB.
intermodulation and effective channel separation. An overview
is provided below, with related Block Diagrams provided on
the following pages.

3
Audio Output Amplifiers

Type number TDA8559(T) TDA8542TS TDA8541(T) TDA8551T

Output power (W) 2×0.035 2×0.7 1 1.4
BTL output configuration no yes yes yes
Voltage gain (dB) 26 6 to 30 6 to 30 –60 to +20
Volume control - - - digital control
Mute mode yes yes yes yes
Standby yes yes - yes
Thermal protection yes yes yes yes
Short-circuit protection yes yes yes yes
Supply voltage (V) 1.9 to 30 2.2 to 18 2.2 to 18 2.7 to 5.5
Package DIP16 (SO16) SSOP20 DIP8 (SO8) DIP8 (SO8)

Audio Output Amplifiers (continued)

Type number TDA8552T(TS) TDA8542AT TDA8941 TDA8942
Output power (W) 2×1.4 2×1.5 1.5 2×1.5
BTL output configuration yes yes yes yes
Voltage gain (dB) –60 to +30 6 to 30 –50 to +30 –50 to +30
Volume control digital control - no no
Mute mode yes yes yes yes
Standby - yes yes yes
Thermal protection yes yes yes yes
Short-circuit protection yes yes yes yes
Supply voltage (V) 2.7 to 5.5 2.2 to 18 6 to 18 6 to 18
Package SO20 (SSOP20) SO20 DIP8 DIP16

Audio Output Amplifiers (continued)

Type number TDA8543(T) TDA1517P TDA8943 TDA8944
Output power (W) 2 2×4 6 2x7
BTL output configuration yes yes yes yes
Voltage gain (dB) 6 to 30 40 –50 to +30 –50 to +30
Volume control - - no no
Mute mode yes yes yes yes
Standby yes yes yes yes
Thermal protection yes yes yes yes
Short-circuit protection yes yes yes yes
Supply voltage (V) 2.2 to 18 2.2 to 18 6 to 18 6 to 18
Package DIP16(SO16) HDIP18 SIL9MP SIL17P (HTSSOP20)

3-2 LCD Displays

RELATED SYSTEMS AUDIO AMPLIFIERS

TDA8542TS OUTL−
VCCL VCCR
100 100
16 9 nF µF
50 kΩ
−
10 kΩ INL− 14 15 OUTL−
input L −
1 µF INL+ 13
+
47 R
VCCL
µF R

−
20 kΩ − 2 OUTL+ 3
+

20 kΩ

OUTR−
STANDBY/MUTE LOGIC

50 kΩ
− TDA8542
10 kΩ INR− 11 10 OUTR−
input R −
1 µF INR+ 12
+
R
VCCR
R

−
7 OUTR+
20 kΩ −
SVR 4 +

20 kΩ

MODE 3
BTL/SE 5 STANDBY/MUTE LOGIC

1 8
LGND RGND

MSC905

TDA1517(P)
stand-by switch
VP
100
100 nF
µF
2200
µF

input
reference internal
voltage 1/2 V P

TDA1517
60 kΩ 60 kΩ
220 nF 220 nF
input 1 input 2

MSB261 - 1
1000 µF 1000 µF

LCD Displays 3-3

 RELATED SYSTEMS AUDIO AMPLIFIERS

TDA8552(TS)

VDD = 5 V

VDD1, 2 VDD3, 4 100

C3 nF C4 220 µF
3, 8 13, 18
C1 IN1 17
VOLUME
330 nF CONTROL
20 C5
VIN1 kΩ 12 OUT1+
MASTER
220 µF
0.5VDD 15 kΩ R1

3 20 dB
3.4 kΩ 20 kΩ
1 kΩ

UP/DOWN 8Ω
COUNTER 30 dB
VDD VDD 20 kΩ

up down 1.6 kΩ
up
volume R5 UP/DOWN1 6 0.5VDD
INTERFACE 19 OUT1−
control 2.2 kΩ SLAVE
100 15 kΩ 0.5VDD headphone jack
down C7 nF C3 SVR 16 tip
0.5VDD
220 µF
TDA8552T ring
C2 IN2 15 15 kΩ
sleeve
VOLUME
330 nF CONTROL
20 C6
VIN2 kΩ 2 OUT2+
MASTER
220 µF

0.5VDD 15 kΩ R4
20 dB 1 kΩ

3.4 kΩ 20 kΩ
UP/DOWN VDD 8Ω
COUNTER 30 dB
VDD 20 kΩ

up down 1.6 kΩ
up
volume R6 UP/DOWN2 7 0.5VDD 9 OUT2−
INTERFACE 15 kΩ
control 2.2 kΩ SLAVE
down C8 0.5VDD
100 nF 0.5VDD

15 kΩ
VDD

standby
MODE 5
mute
STANDBY/MUTE GAIN
HPS 4 AND OPERATING SELECTION
operating

14 1, 10, 11, 20 VDD

GAINSEL GND1 to GND4
R2
820 kΩ
R3

100 kΩ
ground
VDD
MGM609

3-4 LCD Displays

RELATED SYSTEMS AUDIO AMPLIFIERS

TDA8559
VP2 VP1 100
100
15 16 nF µF

1
STANDBY REFERENCE
VP
+IN1 2
+ 50 kΩ
Left V/I − 14 OUT1
− OA
−IN1 3 +
50 kΩ 50 kΩ

MUTE
7
INPUT
DQC 3
8 LOGIC
MODE
+ 11 OUT2
+IN2 5
+ OA
Right V/I −
− 50 kΩ
−IN2 6
50 50
kΩ kΩ

VP

100 kΩ
4 12 BUFFER
SVRR BUFFER
100
kΩ TDA8559

9,10 13
MSC901

n.c. GND

LCD Displays 3-5

 RELATED SYSTEMS AUDIO D-TO-A CONVERSION

UDA1321

USB-DAC

■ Complete stereo USB-DAC system with Sound-processing features are in line with the USB audio-device
integrated filtering and line-output drivers class-specification and include digital de-emphasis, separate digi-
■ Supports all USB-compliant audio tal volume control for left and right channels via USB or direct
multimedia devices control, digital bass and treble tone control, and separate soft
■ On-board DSP complies with USB audio-device mute for left and right channels. Additional features can be
class specification and provides extensive sound included with the use of an external DSP IC, connected via the
3 processing I2S bus.
■ Supports 12 Mbits/s "full speed" serial
data transmission QUICK REFERENCE DATA
■ Fully automatic "Hot Plug-and-Play" operation Power supply 3.3 V
■ Supports multiple audio data I/O formats I2C-bus controlled yes
■ Asynchronous and isochronous support Digital supply current 85 mA
■ High SNR with low total-harmonic distortion Audio-input sample frequency range 5 - 55 kHz (continuous)
■ High linearity and wide dynamic range Typical THD + N at 0 dB -90 dB
■ Digital PLL-based asynchronous master clock SNR 95 dB
■ Low power consumption and power management Total power dissipation (max.) 330 mW
■ On-chip timing reference recovery system, Package QFP60, SO28, SDIL32
including oscillator circuitry, using an external
crystal for clock regeneration

The UDA1321 is a stereo CMOS DAC and USB interface. It

UDA1321
is specially designed for USB-compliant audio devices and for D+ D−

multi-media audio applications such as USB-equipped monitors,

TC
telephony devices and digital audio speakers. It incorporates an RTCB TEST ANALOG FRONT-END SCL
CONTROL
analog front-end, a USB processor, an embedded microcontroller SHTCB BLOCK
SDA
EA
and an Asynchronous DAC (ADAC). The USB processor forms USB-PROCESSOR PSEN

the interface between the USB bus, the ADAC and the micro- ALE
P2.0
controller, and consists of a Serial Interface Engine (SIE), a GP4/BCKO P2.1
GP3/WSO
P2.2
Memory Management Unit (MMU) and an Audio Sample GP2/DO
P2.3
DIGITAL I/O
Redistribution (ASR) module. GP1/DI
GP0/BCKI
P2.4
MICRO- P2.5
GP5/WSI CONTROLLER P2.6

The ADAC includes a Sample Frequency Generator (SFG), P2.7

P0.0
which reconstructs the sample clock, digital up-sampling filters, FIFO REGISTERS P0.1

a noise shaper, a Filter Stream DAC (FSDAC) and a unique fs

P0.2
P0.3
sound-processing DSP to handle feature processing. Audio SAMPLE
FREQUENCY AUDIO FEATURE P0.4
GENERATOR PROCESSING DSP
information can be applied to the ADAC via the USB interface, P0.5
P0.6
directly as I2S input data, or as LSB-justified data with word
fs
P0.7

lengths of 16-, 18- or 20-bits. Two up-sample filters, along with UP-SAMPLE FILTERS

64fs
a variable sample-and-hold function, increase the oversampling VDDE
VSSE
VSSX
rate from 1 fs to 128 fx, after which a third-order noise-shaper XTAL1
VARIABLE HOLD REGISTER
UDA1321H
VSSI
VDDI
converts oversampled data to a bit stream for the FSDAC. XTAL2 OSC TIMING 128fs UDA1321T
UDA1321PS VDDO
VDDX
Finally, on-board amplifiers convert the FSDAC output 3rd-ORDER
NOISE SHAPER
VSSO
VDDA
current to a voltage-output signal for driving a line output. VSSA

LEFT RIGHT
DAC DAC
VOUTL VOUTR

REFERENCE
VOLTAGE

Vref MGM839

3-6 LCD Displays

RELATED SYSTEMS AUDIO D-TO-A CONVERSION

UDA1325

Audio CODEC

■ Single-chip USB audio CODEC with playback and

record functionality
■ Integrated microcontroller with on-chip ROM
supports a variety of topologies and configurations
by editing the USB descriptor set held in EEPROM
■ Fully compliant with USB Specification Rev 1.0,
USB Audio Device Class 1.0, USB HID Device 3
Class and HID Usage Table final specifications QUICK REFERENCE DATA
■ Supports full-speed 12 Mbit/s USB, all USB- Power supply 3.3 V
compliant audio devices and HID connectivity I2C-bus controlled Yes
with two general I/O pins
Digital supply current t.b.f.
■ Adaptive Sample Rate Conversion supporting
Audio input sample frequency range 5 - 55 kHz (continuous)
5 and 55 kHz frequencies for playback
Typical THD + N at 0 dB input –85 dB
■ Input sample rate supports 5.5125, 6, 8, 11.025, 12,
16, 22.05, 24, 32, 44.1, 48 kHz with integrated PLL, output –90 dB
and other frequencies with external crystal SNR 95 dB
■ High linearity, dynamic range and SNR (95 dB) Total power dissipation (max.) t.b.f.
■ Low THD (90 dB on output and 85 dB on input) Package QFP64, SDIP42
■ Extensive DSP features (separate left/right volume
control, soft mute, treble and bass tone control,
dynamic bass boost, selectable clipping UDA1325
detection/prevention and de-emphasis) D+ D−

■ Multiple input/output data formats (8-, 16-,

18- and 24-bit) TC
ANALOG FRONTEND
RTCB TCB
■ I2S and Japanese digital audio format I/O for SHTCB

external digital audio processing, separate I2S USB-PROCESSOR

input can be directly connected to an ADC or PGA

used as DSP interface for AEC

■ Can operate in Bus- and Self-powered modes GP4/BCK
GP3/WS
I2S I/O
GP2/DO

The UDA1325 is a single-chip stereo-audio USB playback GP1/DI

GP0
and record solution. It has an analog audio input, with a MICRO- GP5
I2S CONTROLLER
Programmable Gain Amplifier supporting gain selection in GP6/SCL

FIFO GP7/SDA
small steps, which can be used to support line and microphone
inputs. It also has a digital (I2S) audio input. Host-based and fs_in

SAMPLE
local (directly communicating with UDA1325) DSP-based FREQUENCY AUDIO FEATURE
PROCESSING DSP
GENERATOR
Acoustic Echo Cancellation (AEC) can be implemented.
fs_in

UPSAMPLE FILTERS
All USB control and HID class-support functions are handled
by the integrated microcontroller, with the USB-compliant 64fs_in

firmware stored in 12 kB on-chip ROM. Offering fully VSSX VARIABLE HOLD REGISTER

automatic “hot plug and play”, the UDA1325H is simple XTAL1

OSC TIMING 128fs UDA1325
XTAL2
and inexpensive to design-in, for a variety of applications. VDDX 3th ORDER

The QFP64 version is pin-compatible with the first NOISE SHAPER

generation devices. RconvL RconvR

LEFT RIGHT
DAC DAC
VOUTL VOUTR

REFERENCE
VOLTAGES
MSC786

LCD Displays 3-7

 RELATED SYSTEMS AUDIO D-TO-A CONVERSION

UDA1339TS

USB Stereo Microphone ADC The UDA1339TS is a single-chip USB microphone ADC-
solution. This device is specifically designed for dictation or
■ Single-chip USB stereo-microphone solution for field-microphone applications. It has integrated low-noise
bus-powered applications microphone pre-amps with programmable gain amplifiers.
■ Integrated microphone pre-amps With the gain-trim feature, matching the gain of the micro-
■ Volume control from 28 to -58 dB in steps of 2 dB phone elements is simplified. The use of OTP technology
provides flexibility for VID, PID, strings, and topology
■ Gain-matching for microphone elements
changes during production.
■ Bus-powered with internal 3.3 V LDO regulator
3 ■ OTP ROM for configuration of topology, VID and
PID, etc.
■ Low THD (70 dB typ.)
■ Selection of seven sampling frequencies
■ Three input topologies for different USB
microphone applications
■ On-chip clock oscillator, 12 MHz crystal required
■ Supports 12 Mbits/s serial data transmission

UDA1339TS
VDDA
VRP
VREFAD VUSB
LNAout

VREG
VINL LNA VGA ADC
(CORE & PADS)

Vinvgal
Vinvgar WS
I2S DO
VINR LNA VGA ADC BCK

LNAout
VSSA
VRN
V3.3V
VREG RAM
VUSB 392B
PSIE
Suspend MMU
DP ATX FSM
DM
OTP
ROM
PLL PLL 338B Prog
256fs x4
SDA
IIC
SCL
Vddx
XTAL1 SHTCB
OSC UDA1339TS
XTAL2 TCB RTCB
VSSX TC

MSD579

3-8 LCD Displays

RELATED SYSTEMS AUDIO D-TO-A CONVERSION

Low-voltage Low-power Stereo Audio ADCs

Type number UDA1360TS UDA1361TS

Bitstream conversion ADC ✔ ✔
Stereo, single-ended inputs ✔ ✔
Decimation filter ✔ ✔
Integrated high-pass filter ✔ ✔
Serial output Up to 20 bits I2S and MSB justified Up to 24 bits I2S and MSB justified
Selectable system clock 256 fs and 384 fs 256 fs, 384 fs, 512 fs and 768 fs
Digital de-emphasis filter sampling rates
Sampling rate
32, 44.1 and 48 kHz
18 to 53 kHz
32, 44.1, 48 and 96 kHz
8 to 100 kHz
3
Typical SNR 97 dB 100 dB
Typical THD + N at 0 dB –85 dB –90 dB
Supports 2 Vrms input signals ✔ ✔
Standby mode ✔ ✔
Power supply 2.4 to 3.6 V 2.4 to 3.6 V
Power dissipation 38 mW 42 mW
Package SSOP16 SSOP16

UDA1361

VDDA VSSA VRP VRN VREF SYSCLK

UDA1361TS VDDD

VSSD
VINL ADC
(Σ∆)

MSSEL
DECIMATION CLOCK
FILTER CONTROL
PWON

VINR ADC
(Σ∆)

DATAO
DIGITAL DC-CANCELLATION
BCK SFOR
INTERFACE FILTER
WS

MSD478

LCD Displays 3-9

 RELATED SYSTEMS AUDIO D-TO-A CONVERSION

Audio Digital-to-Analog Converters

Type number UDA1320 UDA1328T

Digital filter ✔ ✔
Volume Digital linear Digital logarithmic
Soft mute ✔ ✔
Noise shaping ✔ ✔
No zero crossing distortion – –
Digital de-emphasis filter sampling rates 32, 44.1 and 48 kHz 32, 44.1, 48 and 96 kHz
Input formats I2S I2S
3 LSB + MSB justified LSB + MSB justified
Oversampling rate – –
Selectable system clock 256 fs 256 fs
384 fs 384 fs
512 fs 512 fs
768 fs
No analog post-filtering required ✔ ✔
Asynchronous and isochronous support – –
On-chip timing reference recovery – –
Selectable IEC 956 line inputs – –
On-chip amplifier – –
Interpolating filter ✔ ✔
Master-mode DATA output/
input interface – –
Power supply 2.7 to 3.6 V 2.7 to 3.6 V
I2C-bus controlled No No
Digital supply current 3 mA 11 mA
DAC supply current 5 mA –
Audio input sample frequency range – 5-100 kHz
Typical THD at 0 dB –90 dB –95 dB (diff. mode), –90 dB (non-diff. mode)
Typical SNR 100 dB 106 dB (diff. mode), 103 dB (non-diff. mode)
Output 1.0 V 1.0 V
Power dissipation 32 mW 129 mW
Package SSOP16 SO32

3-10 LCD Displays

RELATED SYSTEMS AUDIO D-TO-A CONVERSION

UDA1320 VDDD VSSD

4 5

7
APPSEL
1 11
BCK APPL0
2 CONTROL 10
WS DIGITAL INTERFACE APPL1
3 INTERFACE 9
DATAI APPL2
8
APPL3

VOLUME/MUTE/DE-EMPHASIS
UDA1320A
3
6 INTERPOLATION FILTER
SYSCLK

NOISE SHAPER

VO(L) 14 DAC DAC 16

VO(R)

13 15 12
MGM816

VDDA VSSA VREF(DAC)

UDA1328T VDDD VSSD

21 20
9
UDA1328T STATIC
23
MUTE
10 24
BCK DEEM1
11 CONTROL 25
WS DEEM0
12 INTERFACE 18
DIGITAL
DATAI12 L3CLOCK
13 INTERFACE 19
DATAI34 L3DATA
14 17
DATAI56 L3MODE

26
VOLUME/MUTE/DE-EMPHASIS DS

INTERPOLATION FILTER
27 8
TEST1 TEST3
16 22
SYSCLK 6-CHANNEL NOISE SHAPER TEST2

DAC DAC
28 32
VOUT1P VOUT2P
29 31
VOUT1N VOUT2N

DAC DAC

1 2
VOUT3 VOUT4

DAC DAC

4 5
VOUT5 VOUT6

6 7, 15 3 30
MGR979
VDDA n.c. VSSA Vref

LCD Displays 3-11

 RELATED SYSTEMS AUDIO D-TO-A CONVERSION

Audio Digital-to-Analog Converters

Type number UDA1330ATS UDA1334TS UDA1350AH(ATS) UDA1351H(TS)

Digital filter ✔ ✔ ✔ ✔
Volume Logarithmic – ✔ ✔
Soft mute ✔ ✔ ✔ ✔
Noise shaping ✔ ✔ ✔ ✔
No zero crossing distortion – – – –
Digital de-emphasis filter sampling rates 32, 44.1 and 48 kHz 44.1 kHz 32, 44.1 and 48 kHz 32, 44.1, 48 and 96 kHz
Input formats I2S I2S (24 bits) I2S I2S
3 LSB + MSB justified LSB-justified (16, LSB justified LSB-justified
20 and 24 bits) (16, 20 and 24 bits)
Oversampling rate – – – –
Selectable system clock 256 fs Automatic 256 fs out 256 fs out
384 fs
512 fs
No analog post-filtering required ✔ ✔ ✔ ✔
Selectable IEC 956 line inputs – – ✔ ✔
On-chip amplifier – – ✔ ✔
Interpolating filter ✔ ✔ ✔ ✔
Master-mode DATA output/
input interface – – ✔ ✔
Power supply 2.7 to 5.5 V 1.8 to 3.6 V 2.7 to 3.6 V 2.7 to 3.6 V
I2C-bus controlled No No No No
Digital supply current 5.5 mA 1.2 mA t.b.f t.b.f
DAC supply current t.b.f t.b.f t.b.f t.b.f
Audio input sample frequency range 16 to 48 kHz 8 to 100 kHz 8 to 48 kHz 28 to 100 kHz
Typical THD at 0 dB –90 dB –80 dB –90 dB –90 dB
Typical SNR 100 dB 97 dB 100 dB 100 dB
Output 1.45 V 0.5 V 0.9 V 0.9 V
Power dissipation 75 mV 7 mW 72.5 mW 72.5 mW
Package SSOP16 SSOP16 UDA1350AH QFP44 UDA1351H QFP44
UDA1350ATS SSOP28 UDA1351TS SSOP28

VDDD VSSD
UDA1330ATS
4 5

7
APPSEL
1 11
BCK APPL0
2 CONTROL 10
WS DIGITAL INTERFACE APPL1
3 INTERFACE 9
DATAI APPL2
8
APPL3

UDA1330ATS VOLUME/MUTE/DE-EMPHASIS

6 INTERPOLATION FILTER
SYSCLK

NOISE SHAPER

14 DAC DAC 16
VOUTL VOUTR

13 15 12 MGL401

VDDA VSSA Vref(DAC)

3-12 LCD Displays

RELATED SYSTEMS AUDIO D-TO-A CONVERSION

UDA1350AH VDDA(DAC) Vref

UDA1351H CLKOUT TC TEST2 RTCB VSSA VDDA VOUTL VSSA(DAC) VOUTR

32 29 23 39 44 26 27 18 17 25 24 22
VDDA(PLL)
31
VSSA(PLL)
CLOCK DAC DAC
34
TEST1 AND
TIMING CIRCUIT
UDA1350AH
2 NOISE SHAPER
VDDD(C)
VSSD(C)
4
INTERPOLATOR
3
10
L3MODE
6 L3 12
L3CLOCK AUDIO FEATURE PROCESSOR MUTE
5 INTERFACE
L3DATA
35
SELSTATIC
SLICER
15
SPDIF0 DATA DATA
IEC 958 1
16 OUTPUT INPUT RESET
SPDIF1 DECODER
INTERFACE INTERFACE
13
SELCHAN
43
VDDD
3 11, 14,
VSSD
28, 38,
40, 41 21 30 42 33 37 36 7 8 9 19 20
MGS750

n.c. PREEM1 BCKO WSO DATAO BCKI SELCLK

LOCK PREEM0 DATAI WSI SELSPDIF

UDA1350ATS TEST1 TEST3 VSSA VDDA(DAC) Vref

UDA1351TS TEST2 TEST4 VDDA VOUTL VSSA(DAC) VOUTR

4 18 28 25 21 22 15 14 20 19 17
24
VDDA(PLL)
23
VSSA(PLL)
CLOCK DAC DAC
AND
TIMING CIRCUIT

NOISE SHAPER
6
VDDD(C) UDA1351TS
INTERPOLATOR
10
L3MODE
9 L3 11
L3CLOCK AUDIO FEATURE PROCESSOR MUTE
INTERFACE
8
L3DATA
26
SELSTATIC
SLICER

13 IEC 958 5
SPDIF RESET
DECODER
3
VDDD
7
VSSD
12
VSSD(C)
1, 2, 27 16
MGU032
n.c. LOCK

LCD Displays 3-13

 RELATED SYSTEMS AUDIO D-TO-A CONVERSION

VDDD VSSD
UDA1334TS
UDA1334BTS 4 5

1
BCK
2
WS DIGITAL INTERFACE
3
DATAI

DE-EMPHASIS
UDA1334BTS
6 7
3 SYSCLK
MUTE
8
INTERPOLATION FILTER
11
SFOR1
SFOR0
9
DEEM
10
PCS
NOISE SHAPER

14 DAC DAC 16
VOUTL VOUTR

13 15 12
MGL964

VDDA VSSA Vref(DAC)

3-14 LCD Displays

RELATED SYSTEMS AUDIO D-TO-A CONVERSION

Low Power Stereo Audio CODECs

Type number UDA1341TS UDA1345TS

Fully USB support compliant – –
Bitstream ADC ✔ ✔
Bitstream/CC DAC ✔ ✔
Separate power down modes for
ADC and DAC ✔ ✔
Integrated high-pass filter ✔ ✔
Analog loop through function – –
3
Fully integrated analog front-end ✔ ✔
Stereo single ended input configuration ✔ ✔
L3 microcontroller interface ✔ ✔
System clock 256 fs, 384 fs 256 fs, 384 fs
and 512 fs and 512 fs
Digital de-emphasis filter sampling rates 32, 44.1 and 48 kHz 32, 44.1, 48 and 96 kHz
Can operate in Bus and
Self-powered modes – –
Digital de-emphasis (DAC) ✔ ✔
I/O formats I2S, MSB, LSB, 1 fs I2S, MSB, LSB, 1 fs
Overload detector ✔ ✔
Digital sound processing features ✔ ✔
No analog post-filtering required ✔ ✔
Microphone input with on-board PGA ✔
Power supply (5 V tolerant I/O) 2.4 to 3.6 V 2.4 to 3.6 V
I2C-bus controlled No No
ADC Analog supply current – 10 mA
Digital supply current 7.0 mV 5 mA
Typical THD + N at 0 dB –90 dB –83 dB
SNR 100 dB 95 dB
DAC Analog supply current – 4 mA
Digital supply current – 5 mA
Typical THD + N at 0 dB –91 dB –85 dB
SNR 100 dB 100 dB
Audio input sample frequency range 8 to 48 kHz 8 to 100 kHz
Power dissipation (typ.) 80 mW 65 mW
Package SSOP28 SSOP28

LCD Displays 3-15

 RELATED SYSTEMS AUDIO D-TO-A CONVERSION

VDDA(ADC) VSSA(ADC) VDDD VSSD VADCP VADCN

UDA1341TS
3 1 10 11 7 5

6 8
VINL2 VINR2

PGA PGA
ADC2 ADC2
2 0 dB/6 dB 0 dB/6 dB 4
VINL1 VINR1
SWITCH SWITCH

ADC1 ADC1

22
UDA1341TS AGCSTAT
DIGITAL AGC

3 DIGITAL MIXER

9
DECIMATION
DECIMATIONFILTER
FILTER OVERFL

18 13
DATAO L3MODE
16
BCK L3-BUS 14
17 DIGITAL INTERFACE L3CLOCK
WS INTERFACE
19 15
DATAI L3DATA

DSP FEATURES 12
SYSCLK

23 PEAK
QMUTE INTERPOLATION FILTER
DETECTOR

20
NOISE SHAPER TEST1
28
Vref 21
TEST2

DAC DAC

26 24
VOUTL VOUTR

25 27

VDDA(DAC) VSSA(DAC)
MGR427

UDA1345TS VDDA(ADC) VSSA(ADC) VADCP VADCN Vref(A)

2 1 7 6 4

3 0 dB/6 dB 0 dB/6 dB 5
VINL VINR
SWITCH SWITCH

ADC ADC
8
MC1
10 DECIMATION FILTER 21
VDDD MC2

11 20
MP5
VSSD DC-CANCELLATION FILTER

18 13
DATAO MP2
16
BCK L3-BUS 14
17 DIGITAL INTERFACE MP3
WS INTERFACE
19 15
DATAI MP4
12
SYSCLK
9 INTERPOLATION FILTER
MP1

UDA1345TS
NOISE SHAPER

DAC DAC

26 24
VOUTL VOUTR

25 27 23 22 28
MGS875

VDDO VSSO VDDA(DAC) VSSA(DAC) Vref(D)

3-16 LCD Displays

RELATED SYSTEMS USB INTERFACE

USB Interface
All Philips USB interface-ICs conform to their respective USB "hotline" costs. SoftConnect provides an extra level of peripheral
specification and are fully compliant with most device specifica- control via the host connection.
tions. Many also include the GoodLink™ and SoftConnect™
features. GoodLink allows a quick visual check of whether Such feature enhancements make a significant contribution to
peripherals connected to the hub's downstream ports are work- cost-savings in a total system implementation and at the same
ing properly, delivering significant cost-savings in user support time ease the implementation of advanced USB functionality
into PC peripherals.

Type number ISP1123 ISP1122A PDIUSBH11A PDIUSBD11

Hub yes yes yes no
3
USB specification compliance 1.1 1.1 1.0 1.1
Upstream ports 1 1 1 1
Downstream ports 2 to 5 2 to 5 4 0
Embedded function 0 0 3 1
Embedded USB port Port 1 0 0 0
Integrated FIFOs yes yes yes yes
Automatic USB protocol handling yes yes yes yes
SoftConnect yes yes yes yes
GoodLink yes yes yes no
I2C-bus yes yes yes yes
Bundled Monitor Control software no no yes yes
Clock frequency (MHz) 6 6 12 12
Supply voltage (V) 5.0 5.0 3.0 to 3.6 3.0 to 3.6
Package LQFP32 SDIP32, SO32, LQFP32 SDIP32, SO32 DIP16, SO16

upstream
ISP1123 VCC Vreg(3.3) D+
port
D− LED
6 MHz

5V PACKET I2C-BUS SDA

PLL GENERATOR INTERFACE SCL
SUPPLY ANALOG HUB
REGULATOR Tx / Rx GoodLink BIT CLOCK
ISP1123
3.3 V RECOVERY
full INDV
speed PHILIPS HUB
SIE CONTROLLER OPTION

END OF
HUB
FRAME
REPEATER
TIMERS

GENERAL
PORT
CONTROLLER

ANALOG GoodLink/ ANALOG GoodLink/ ANALOG GoodLink/ ANALOG GoodLink/ ANALOG GoodLink/ self/bus
Tx /Rx POWER SWITCH/ Tx / Rx POWER SWITCH/ Tx / Rx POWER SWITCH/ Tx / Rx POWER SWITCH/ Tx / Rx POWER SWITCH/ powered
OC DETECT OC DETECT OC DETECT OC DETECT OC DETECT

D+ D− overcurrent LED/ D+ D− overcurrent LED/ D+ D− overcurrent LED/ D+ D− overcurrent LED/ D+ D− overcurrent LED/
detection power switch detection power switch detection power switch detection power switch detection power switch

downstream port 1: downstream port 2 downstream port 3 downstream port 4 downstream port 5
embedded or non-removable (removable) (removable) (removable) (removable) MBL083
function

LCD Displays 3-17

 RELATED SYSTEMS USB INTERFACE

ISP1122A upstream
port 6 MHz
VCC Vreg(3.3) D+ D− LED

5V PACKET I2C-BUS SDA

PLL GENERATOR INTERFACE SCL
SUPPLY ANALOG HUB
REGULATOR Tx / Rx GoodLink BIT CLOCK
ISP1122A
3.3 V RECOVERY
full INDV
speed PHILIPS HUB
SIE CONTROLLER OPTION

3 HUB
REPEATER
END OF
FRAME
TIMERS

GENERAL
PORT
CONTROLLER

ANALOG GoodLink/ ANALOG GoodLink/ ANALOG GoodLink/ ANALOG GoodLink/ ANALOG GoodLink/ self/bus
Tx / Rx POWER SWITCH/ Tx / Rx POWER SWITCH/ Tx / Rx POWER SWITCH/ Tx / Rx POWER SWITCH/ Tx / Rx POWER SWITCH/ powered
OC DETECT OC DETECT OC DETECT OC DETECT OC DETECT

D+ D− overcurrent LED/ D+ D− overcurrent LED/ D+ D− overcurrent LED/ D+ D− overcurrent LED/ D+ D− overcurrent LED/
detection power switch detection power switch detection power switch detection power switch detection power switch

downstream downstream downstream downstream downstream

port 1 port 2 port 3 port 4 port 5 MBL169

PDIUSBH11A UPSTREAM
PORT 12 MHz
D+ D−

3.3 V

1.5 kΩ PLL
INTEGRATED
RAM
D+ ANALOG BIT CLOCK
RECOVERY
SoftConnectTM TX/RX

MEMORY I2C
FULL SPEED PHILIPS MANAGEMENT SLAVE
SIE UNIT INTERFACE

END OF
HUB
FRAME
REPEATER
TIMERS

GENERAL
PORT
CONTROLLER

GOODLINKTM TM TM TM
ANALOG ANALOG GOODLINK ANALOG GOODLINK ANALOG GOODLINK
Tx/Rx CONTROL Tx/Rx CONTROL Tx/Rx CONTROL Tx/Rx CONTROL

D+ D− LED D+ D− LED D+ D− LED D+ D− LED INTERRUPT SDA SCL

DOWNSTREAM DOWNSTREAM DOWNSTREAM DOWNSTREAM

PORT 2 PORT 3 PORT 4 PORT 5 NO LIGHT LIT BLINKING

NO CONNECTED DATA
CONNECTION TRANSFER
GOODLINKTM
MSC666

3-18 LCD Displays

RELATED SYSTEMS USB INTERFACE

PDIUSBD11 UPSTREAM
PORT 12 MHz
D+ D−

3.3 V

1.5 kΩ PLL
INTEGRATED
RAM
D+ ANALOG BIT CLOCK
FULL SPEED RECOVERY
SoftConnectTM TX/RX

MEMORY I2C INTERRUPT

PHILIPS
SIE
MANAGEMENT
UNIT
SLAVE
INTERFACE
SDA
SCL 3
MSC668

LCD Displays 3-19

 RELATED SYSTEMS SMPS

Low standby power SMPS systems

The Switched Mode Power Supply (SMPS) is the most com- source and integrated on/off circuitry that replaces an expensive
pact and efficient electrical power supply for LCD monitors. main switch. GreenChips have a built-in standby mode that uses
Although many SMPS systems provide a standby mode, during burst-mode operation. In this mode, standby power level
which they consume just 5 to 10 Watts, this "standby" accounts as low as 1 W can be reached without the need for a dedicated
for up to 10% of domestic and office electricity bills. Philips standby SMPS. The newest addition to the GreenChip family
Semiconductors now offers a new SMPS controller family that is the TEA1507 GreenChip SMPS controller. Besides standby
drastically reduces the overall cost and power consumption of power, this product offers optimal efficiency at all power levels.
SMPS designs. In addition to the GreenChip™ TEA1504 SMPS GreenChip uses valley switching to reduce switch-on losses and
controller and TEA1501 standby controllers, Philips offers the EMI radiation. The GreenChip operates in Quasi Resonant
new TEA1507 GreenChip and STARplug™ families of ICs that (QR) mode at high power levels, and fixed frequency operation
3 save energy in all modes of operation. at medium power levels. At low power level, the switching fre-
quency is reduced to limit switching losses.
GreenChip circuits
GreenChip designs, based on around the TEA15xx family, bring STARplug circuits
typical standby power consumption down to 1 to 2 W, or less The TEA152x STARplug family of SMPS controller ICs are
than 200 mW when used in combination with the dedicated designed for compact and efficient power supplies supplying up
standby controller TEA1501 (ideal for use together with the to 50 W. They operate directly from the rectified mains and all
TEA1504) or STARplug ICs. ICs (except the TEA152AJM) incorporate dedicated circuitry
for valley-switching, resulting in minimal switch-on-loss. They
GreenChips are optimized for both primary and secondary also feature frequency reduction at low power output, which
sensing configurations and operate directly from a 90 V to 276 brings their standby power down to 100 mW or less. The ICs
V AC supply. They also contain an on-chip startup current are available in 8-pin DIP, 14-pin SO and 9-pin DBS packages.

GreenChip Circuits for LCD Monitor SMPS

Type number MOSFET Power* (W) Package

TEA1501 internal, 650 V @ 40 Ω 0.1 - 3 DIP8
TEA1504 – <2 DIP14
TEA1507 – <3 DIP8
* Universal mains 100-240 V (AC)

STARplug Circuits for LCD Monitor SMPS

Type Rds,on Global mains 180 - 276V 150V max

number DIP/SO DBS DIP/SO DBS DIP/SO DBS
TEA1524 3.5 Ω 15 W 30 W 30 W 50 W 15 W 30 W
TEA1523 7Ω 10 W 20 W 15 W 35 W 10 W 20 W
TEA1522 12 Ω 7W 10 W 8W 20 W 7W 10 W
TEA1521 24 Ω 3W - 4.5 W - 3W -
TEA1520 50 Ω 2W - 3W - 2W -

3-20 LCD Displays

RELATED SYSTEMS SMPS

TEA1501
Vaux Rref Drn

start-up current
source
SUPPLY CURRENT V aux MANAGEMENT
TRACKING REFERENCE BLOCK
TEMPERATURE
GND PROTECTION

Cbt MODULATOR

LOGIC
SWITCH
OSCILLATOR 3
BURST OSCILLATOR

on/off level power

switch
COUNTER GATE DRIVER
LEADING EDGE
OOD BLANKING

data on data off Src

Vdetect
TEA1501

MSC680

TEA1504
REF Vaux Vi

8 6 1

Vaux START-UP
MANAGEMENT CURRENT SOURCE
on/off

TEA1504
14 1 kΩ
OOB

5.5 V
burst mode
stand-by
6Ω 7
R DS
OVER 6Ω
Q 4
TEMPERATURE DRIVER
PROTECTION S
driver
stage
9
CTRL PULSE WIDTH
MODULATOR
SAMPLE SAMPLE
OVER CURRENT
AND AND
PROTECTION
HOLD1 HOLD2
inverting
error comparator 5
amplifier LEADING EDGE I sense
BLANKING
13
DEM
DEMAGNETIZATION
OSCILLATOR
MANAGEMENT FREQUENCY
CONTROL
duty cycle limiting
NEGATIVE signal
CLAMP
11 2 3 10 12
MGS569
GND HVS n.c. n.c. n.c.

LCD Displays 3-21

 RELATED SYSTEMS SMPS

TEA1507
1 SUPPLY START-UP 8
VCC Drain
MANAGEMENT CURRENT SOURCE

internal uvlo start clamp 7

supply HVS
VALLEY
S1 Mlevel
VOLTAGE 4
Demag
2 CONTROLLED LOGIC
GND OSCILLATOR

3 100 mV
OVER
VOLTAGE
TEA1507 PROTECTION

FREQUENCY
LOGIC 6
CONTROL Driver

DRIVER
ISS
OVER LEB
TEMPERATURE soft 0.5
S Q
PROTECTION blank start V
3 S2
Ctrl −1
POWER-ON UVLO R Q
RESET 5
OCP Sense
2.5 V

short 0.75
burst MAXIMUM winding
detect ON-TIME V
PROTECTION
OVER
POWER
PROTECTION

MSD547

TM
GREEN CHIP

TEA15xx
µP
S MAIN
on/off SUPPLY
Src Drn
TM
OOD GREEN CHIP n.c. on/off
S open: main supply off main
Cbt S closed: main supply on supply
GND
TM
Rref TEA1501 VCC GREEN CHIP
µP
TEA1501 S

STANDBY
SUPPLY
MSC682

(a) (b)

The TDA1501 standby supply (a) stand-alone application diagram, (b) used with mains-supply GreenChip (< 1 W standby option)

3-22 LCD Displays

RELATED SYSTEMS SMPS

TEA152x

1 8
VCC SUPPLY DRAIN

VALLEY
TEA152x

GND
2 LOGIC 7
n.c. 3
100 mV

PWM

stop
3 6
RC OSCILLATOR THERMAL SOURCE
low freq SHUTDOWN

PROTECTION
LOGIC
F POWER-UP blank
RESET
1.8 U
overcurrent

2.5 V 0.5 V
4 5
REG 10x AUX

short circuit winding

0.75 V

MGT419

TEA1523
LF
D5

CF1 CF2 Z1

C5 Vout
D1

Vmains
R1
R2 D2

CVCC
VCC
1 8 DRAIN

GND n.c.
2 7
RRC
TEA1523 RI
RC SOURCE
3 6
R4
CRC RAUX
REG AUX
4 5
C6 - Ycap
R3

MGU245

Typical STARplug Application

LCD Displays 3-23

 RELATED SYSTEMS LCD MODULES AND DISCRETES

Flat-panel LCD modules

Our sister company, Philips Flat Display System (FDS), offers a
wide range of state-of-the-art flat-panel displays, including pas-
sive and active matrix LCD and Polymer LED products. A full
line of display panels, up to 22 inches, is available for desktop
monitor, notebook, telecommunications, industrial, automotive,
handheld and medical system applications. Through their own
manufacturing and joint ventures, FDS is a leading supplier of
technically advanced flat displays.

For the latest product availability and specifications, visit

3 www.components.philips.com or contact [email protected].

Small-signal discretes for LCD monitors

■ Leading-edge technology used in power-saving ■ Schottky diodes set the standard with the lowest
bipolar small-signal transistors, Schottky diodes V F and I R available
and Zener diodes ■ Compact surface-mount packages reduce board
■ Breakthroughs in Small-Signal transistors offer space, for smaller and lighter products
extremely low power dissipation for switching
low-voltage loads at high currents Philips Semiconductors offers a wide range of high-performance,
■ Transistors offer outstanding DC current gain small-signal switching transistors, Zener diodes and Schottky
at high-current operation diodes. These devices fulfill many general application require-
■ Zener diodes offer noise-free breakdown-knees ments within the LCD monitor and, because of their low power
at very low currents consumption, are particularly well suited to battery-powered
equipment containing the latest IC technologies.

3-24 LCD Displays

 Diodes for LCD Monitor Designs

SOT23 SC-70/ SC-76/ SC-59/ Description VR IF IFRM IFSM VF @ IF Cd trr Cd @ VR Ptot @ Ttp/ Vz Vz

LCD Displays
SOT323 SOD323 SOT346 max. max. max. max. max. (mA) max. max. max. (V) max. Tamb min max.
(V) (mA) (mA) (A) (mV) (pF) (ns) (pF) (mW) (ºC) (V) (V)
1PS181 High speed, double diode 80 125 - 215 500 4 1200 100 2 4 250 25
1PS226 High speed, double diode 80 125 - 215 500 4 1200 100 1.5 4 250 25
RELATED SYSTEMS

PZM-N Voltage regulator diode 250 1100 100 300 25 2.4 36

BAS316 High speed diode 75 150 - 250 450 - 500 4 1000 50 1..2 4
BAS321 General purpose diode 200 200 - 300 625 - 1000 9 - 20 1000 100 2..5 50
PDZ-series Voltage regulator diode 200 1100 100 400 25
1PS300 High speed double diode 80 200 - 250 500 4 1000 50 2 4 300 25
1PS301 High speed double diode 80 160 - 250 500 4 1200 100 1.5 4 300 25
1PS302 High speed double diode 80 170 - 200 500 4 1200 100 1.5 4 300 25
1PS70SB10 Schottky diodes 30 200 300 600 320 1 10 1
1PS70SB15 Schottky diodes 30 200 300 600 320 1 10 1
1PS76SB10 Schottky diodes 30 200 320 1 10 1
1PS76SB40 Schottky diodes 40 120 380 1 5 0
1PS59SB10 Schottky diodes 30 200 300 600 320 1 10 1
1PS59SB15 Schottky diodes 30 200 300 600 320 1 10 1
BAT854W low Vf Schottky diode * 600 100
BAT754 low Vf Schottky diode 600 100
BZX99-C low power consumption
Zener diode 2.4 15
BZX399 low power consumption
Zener diode 1.8 43

* VR = 25 V @ IR = 0.5 mA
LCD MODULES AND DISCRETES

3-25
3
 3

3-26
Transistors for LCD Monitor Designs (For Resistor Equipped Transistors see page 3-27)

SOT23 SC-70/ SC-89/ SC-59/ SC-75/ SC-88/ Description ICmax. VCEOmax. hFE min. hFE max. fTmin.
SOT323 SOT490 SOT346 SOT416 SOT363 (mA) (V) (MHz)

PMMT491A BISS transistor PNP 1000 40 300 800 150

PMMT591A BISS transistor PNP 1000 40 300 900 150
RELATED SYSTEMS

2PA1576 general purpose transistors (2) PNP 100 40 - 50 120 - 270 270 - 560 100
2PC4082 general purpose transistors (2) NPN 100 40 - 50 120 - 270 270 - 560 100
2PB1219A general purpose transistors PNP 500 50 85 - 170 170 - 340 100 - 140
2PD1820A general purpose transistors NPN 500 50 85 - 170 170 - 340 140 - 150
BC847W family general purpose transistors NPN 100 45 110 800 100
BC857W family general purpose transistors PNP 100 45 125 800 100
2PB709A general purpose transistors PNP 100 45 - 50 160 - 290 260 - 460 60
2PD601A general purpose transistors NPN 100 45 - 50 160 - 290 260 - 460 100
2PB710A general purpose transistors PNP 500 50 85 - 170 170 - 340 100 - 140
2PD602A general purpose transistors NPN 500 50 85 - 170 170 - 340 140 - 150
2PA1774 general purpose transistors (2) PNP 100 40 - 50 120 - 270 270 - 560 100
2PC4617 general purpose transistors (2) NPN 100 40 - 50 120 - 270 270 - 560 100
BC847BS general purpose transistors (2) NPN 100 45 200 450 100
BC857BS general purpose transistors (2) PNP 100 45 200 - 220 475 - 500 100
BC847BPN general purpose transistors NPN/PNP 100 45 200 450 100
PUMX1 general purpose double transistor (2) NPN 100 40 - 50 120 - 270 270 - 560 100
PUMT1 general purpose double transistor (2) PNP 100 40 - 50 120 - 270 270 - 560 100
PUMZ1 general purpose transistors NPN/PNP 100 40..50 120 - 270 270 - 560 100
BC847F family general purpose transistors NPN 100 45 110 - 420 220 - 800 100
BC857F family general purpose transistors PNP 100 45 125 - 420 250 - 800 100
2PA1774J general purpose transistors (2) PNP 100 40..50 120 - 270 270 - 560 100
2PC4617J general purpose transistors (2) NPN 100 40..50 120 - 270 270 - 560 100

LCD Displays
LCD MODULES AND DISCRETES
RELATED SYSTEMS LCD MODULES AND DISCRETES

Resistor Equipped Transistors

VCE0 (V) 50
ICmax (mA) 100
Ptot (mW) 500 250 200 250 150 250 300
R1 (kΩ) R2 (kΩ) Pol. SOT54 SOT23 SOT323 SC-59 SOT416 SOT490 SOT363
TO92 SC-70 SC-75 SC89 SC-88
PNP PDTA123ET
2.2 2.2 NPN/PNP
NPN PDTC123ET
PNP PDTA143ES PDTA143ET PDTA143EU PDTA143EK PDTA143EE 3
4.7 4.7 NPN/PNP
NPN PDTC143ES PDTC143ET PDTC143EU PDTC143EK PDTC143EE
PNP PDTA114ES PDTA114ET PDTA114EU PDTA114EK PDTA114EE PDTA114EEF PUMB11
10 10 NPN/PNP PUMD3
NPN PDTC114ES PDTC114ET PDTC114EU PDTC114EK PDTC114EE PDTC114EEF PUMH11
PNP PDTA124ES PDTA124ET PDTA124EU PDTA124EK PDTC124EE
22 22 NPN/PNP PUMD2
NPN PDTC124ES PDTC124ET PDTC124EU PDTC124EK PDTC124EE PUMH1
PNP PDTA144ES PDTA144ET PDTA144EU PDTA144EK PDTA144EE PDTA144EEF PUMB2
47 47 NPN/PNP PUMD12
NPN PDTC144ES PDTC144ET PDTC144EU PDTC144EK PDTC144EE PDTC144EEF PUMH2
PNP
100 100 NPN/PNP
NPN PDTC115EE
PNP PDTA123JT PDTA123JE PDTA123JEF
2.2 47 NPN/PNP PUMD10
NPN PDTC123JT PDTC123JE PDTC123JEF PUMD10
PNP
4.7 Open NPN/PNP PUMD6
NPN PDTC143TT PUMH7
PNP PDTA143XT PDTA143XE
4.7 10 NPN/PNP
NPN PDTC143XT PDTC143XE
PNP PDTA143ZT PDTA143ZK
4.7 47 NPN/PNP PUMD13*
NPN PDTC143ZT PDTC143ZK
10 Open PNP PDTA114TS PDTA114TT PDTA114TU PDTA114TK PUMB4
NPN/PNP
NPN PDTC114TS PDTC114TT PDTC114TU PDTC114TK PDTC114TE PUMH4
PNP PDTA114YT
10 47 NPN/PNP PUMD9
NPN PDTC114YT PDTC114YU PDTC114YE PUMH9
PNP PDTA124XE PDTA124XEF
22 47 NPN/PNP
NPN PDTC124XE PDTC124XEF
PNP PDTA144WU
47 22 NPN/PNP
NPN PDTC144WT PDTC144WU

Other Configurations: Double transistor with 2 different resistor combinations

NPN: 47 47
NPN/PNP PUMD48
PNP: 2.2 47

LCD Displays 3-27

 3

3-28
BISS Transistors for LCD Monitor Designs

Devices Package VCEsat(mV) – max @ Ic max VCEO hFE hFE fT Polarity

IC=200 mA IC=500mA IC=1A IC=2A IC=5A (mA) max (V) min max min (MHz)
IB=10 mA IB=50mA IB=50mA IB=200 mA IB = 500 mA
PBSS2515F SC89/SOT490 200 250 500 15 200 100 NPN
PBSS3515F SC89/SOT490 200 250 500 15 200 100 PNP
RELATED SYSTEMS

PBSS414OU SC70/SOT323 250 1000 40 300 900 150 NPN

PBSS514OU SC70/SOT323 250 1000 40 300 800 150 PNP
PMMT591A SOT23 300 1000 40 300 900 150 NPN
PMMT491A SOT23 350 1000 40 300 800 150 PNP
PBSS4140T SOT23 250 1000 40 300 900 150 NPN
PBSS5140T SOT23 250 1000 40 300 800 150 PNP
PBSS435OD SC74/SOT457 90 170 290 3000 50 200 100 NPN
PBSS535OD SC74/SOT457 100 180 300 3000 50 200 100 PNP
PBSS4350X SOT89/SC62 90 170 290 3000 50 200 100 NPN
PBSS5350X SOT89/SC62 100 180 300 3000 50 200 100 PNP
PBSS4540Z SOT223 150 355 5000 40 250 70 NPN
PBSS5540Z SOT223 160 375 5000 40 150 60 PNP
PBSS8112T SOT23 150 250 1000 125 300 100 NPN

LCD Displays
LCD MODULES AND DISCRETES
 A

APPENDIX

LCD Displays A-1

 APPENDIX INDEX

INDEX OF TYPE NUMBERS

Type number Description Page

ISP1122A/23 USB interface 3-17
OM6211/12/13 LCD graphic driver (black/white) 2-23
PCF2113/19 LCD graphic driver (black/white) 2-23
PCF85116-3 16 kbits CMOS EEPROM with I2C bus-interface 2-18
PCF8531/35 LCD graphic driver (black/white) 2-23
PCF8548/49/58 LCD graphic driver (black/white) 2-23
PCF8598C-2 8 kbits CMOS EEPROM with I2C bus-interface 2-18
PCF8811/12/13/20 LCD graphic driver (black/white) 2-23
PCA8840 TFT-LCD gate driver for VGA and XGA 2-21
PCA8848/49/50 TFT-LCD source driver 2-20
A PCA8851 TFT-LCD gate driver for XGA and SXGA 2-22
PDIUSBD11 USB interface 3-17
PDIUSBH11A USB interface 3-17
SAA6712 XGA RGB-to-TFT display controller 2-3
SAA6712A XGA RGB/YUV-to-TFT display controller 2-4
SAA6713 XGA dual-input TFT display controller 2-6
SAA6714 SXGA triple-input TFT display controller 2-8
SAA6721 SXGA RGB/YUV-to-TFT display controller 2-4
SAA7113 Video input processor 2-13
SAA7114 Video decoder with comb filter and high-performance scaler 2-14
SAA7118 Multi-standard video decoder with adaptive comb filter and component video input 2-16
TDA1517P 2x4 S amplifier 3-2
TDA8541(T) 1 W BTL amplifier 3-2
TDA8542AT 2x1.5 W BTL amplifier 3-2
TDA8542TS 2x0.7 WBTL amplifier 3-2
TDA8543(T) 2 W BTL amplifier 3-2
TDA8551T 1.4 W BTL amplifier 3-2
TDA8552T(TS) 2x1.4 W amplifier with digital volume control 3-2
TDA8559(T) Low-voltage BTL stereo amplifier 3-2
TDA8752 Triple high-speed analog-to-digital converter 2-11
TDA8757 Triple 8-bit ADC 170 Msps 2-12
TDA8941 1.5 W audio amplifier 3-2
TDA8942 2x1.5 W audio amplifier 3-2
TDA8943 6 W audio amplifier 3-2
TDA8944 2x7 W audio amplifier 3-2
TEA1501/04/07 GreenChip circuit for SMPS 3-20
TEA1520 to 24 STARplug circuits for SMPS 3-20
UDA1320 Audio digital-to-analog converter 3-10
UDA1321 USB-DAC 3-6
UDA1325 Audio CODEC 3-7
UDA1328T Audio digital-to-analog converter 3-10
UDA1330ATS Audio digital-to-analog converter 3-12
UDA1334TS(BTS) Audio digital-to-analog converter 3-12

A-2 LCD Displays

APPENDIX INDEX

Type number Description Page

UDA1339TS USB stereo microphone ADC 3-8
UDA1341TS/45TS Low-power stereo-audio CODEC 3-15
UDA1350AH(ATS) Audio digital-to-analog converter 3-12
UDA1351H(TS) Audio digital-to-analog converter 3-12
UDA1360TS/61TS Low-voltage low-power stereo-audio ADC 3-9

LCD Displays A-3

 APPENDIX NOTES

A-4 LCD Displays

Philips Semiconductors
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list of our sales offices and distributor partners, please visit our website http://www.semiconductors.philips.com or contact
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