Introduction to Sequential

Circuits

By

Dr. Irshad Ahmad Ansari

 Combinational Logic
• Combinational Logic:
– Output depends only on current input
– Has no memory
 Sequential Logic
• Sequential Logic:
– Output depends not only on current input but also
on past input values, e.g., design a counter
– Need some type of memory to remember the past
input values
– Elevator, Traffic light
 Sequential Circuits
Circuits that we Information Storing
have learned Circuits
so far

Timed “States”
 Sequential Logic: Concept
• Sequential Logic circuits remember past
inputs and past circuit state.
• Outputs from the system are
“fed back” as new inputs
– With gate delay and wire delay
• The storage elements are circuits that are
capable of storing binary information: memory.
 Synchronous vs. Asynchronous

There are two types of sequential circuits:

• Synchronous sequential circuit: circuit output
changes only at some discrete instants of time. This
type of circuits achieves synchronization by using a
timing signal called the clock.
• Asynchronous sequential circuit: circuit output can
change at any time (clockless).
 Synchronous Sequential Circuits:
Flip flops as state memory

 The flip-flops receive their inputs from the

combinational circuit and also from a clock signal
with pulses that occur at fixed intervals of time,
as shown in the timing diagram.
 Clock Period

FF Combinational FF
Circuit

FF

Smallest clock period = largest combinational

circuit delay between any two directly connected FF,
subjected to impact of FF setup time.
 SR Latch (NAND version)

0 S’ S’ R’ Q Q’
Q 1
0 0
0 1 1 0 Set
1 0
Q’ 0
1 R’ 1 1

X Y NAND
00 1
01 1
10 1
11 0
 SR Latch (NAND version)

1 S’ S’ R’ Q Q’
Q 1
0 0
0 1 1 0 Set
1 0
Q’ 0
1 R’ 1 1 1 0 Hold

X Y NAND
00 1
01 1
10 1
11 0
 SR Latch (NAND version)

1 S’ S’ R’ Q Q’
Q 0
0 0
0 1 1 0 Set
1 0 0 1 Reset
Q’ 1
0 R’ 1 1 1 0 Hold

X Y NAND
00 1
01 1
10 1
11 0
 SR Latch (NAND version)

1 S’ S’ R’ Q Q’
Q 0
0 0
0 1 1 0 Set
1 0 0 1 Reset
Q’ 1
1 R’ 1 1 1 0 Hold
0 1 Hold
X Y NAND
00 1
01 1
10 1
11 0
 SR Latch (NAND version)

0 S’ S’ R’ Q Q’
Q 1
0 0 1 1 Disallowed
0 1 1 0 Set
1 0 0 1 Reset
Q’ 1
0 R’ 1 1 1 0 Hold
0 1 Hold
X Y NAND
00 1
01 1
10 1
11 0
 SR Latch with Clock signal
(SR FLIP FLOP)

Latch is sensitive to input changes ONLY when C=1

 FLIP FLOPS

• SR flip flop

• D flip flop

• JK flip flop

• T flip flop
 (D FLIP FLOP)
• One way to eliminate the undesirable indeterminate
state in the SR flip flop is to ensure that inputs S and
R are never 1 simultaneously. This is done in the D
latch:
 Flip-Flops
• Latches are “transparent” (= any change on
the inputs is seen at the outputs immediately
when C=1).
• This causes synchronization problems.
• Solution: use latches to create flip-flops that
can respond (update) only on specific times
(instead of any time).
• Types: SR flip-flop and D flip-flop
 Characteristic Tables
• Defines the logical properties of a flip-flop (such
as a truth table does for a logic gate).
• Q(t) – present state at time t
• Q(t+1) – next state at time t+1
Characteristic Tables (cont.)
SR Flip-Flop
S R Q(t+1) Operation
0 0 Q(t) No change/Hold
0 1 0 Reset
1 0 1 Set
1 1 ? Undefined/Invalid
Characteristic Tables (cont.)

D Flip-Flop
D Q(t+1) Operation
0 0 Set
1 1 Reset

Characteristic Equation: Q(t+1) = D(t)

(JK FLIP FLOP)
Characteristic Table of JK flip flop

J K Q(t+1) Q’(t+1) Mode

0 0 Q(t) Q’(t) Hold

1 0 1 0 Sets

0 1 0 1 Resets
1 1 Q’(t) Q(t) Toggle
(Race Around)
(JK FF Master-Slave)
(T Flip Flop)
(Level and Edge Trigger)
Complete FF Representation
Counter
D C B A
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 1
1 0 0 0
1 0 0 1
1 0 1 0
1 0 1 1
1 1 0 0
1 1 0 1
1 1 1 0
1 1 1 1
• Modulo-16 Counter

• Up Counter (BCD Counter)

• Down Counter

• Three bit Counter (2-6 Counter)

• Modulo-4 (Up Counter)

PST CLR Q
0 1 1
1 0 0
1 1 Normal
0 0 Not Permitted
BCD Counter
• Ripple Counter (Delay issue):
Asynchronous Counter

• Synchronous Counter: Clock to all

Synchronous Counter
Synchronous Counter

Determine, What type of counter is shown above ?

It is Modulo-8, Down Counter

 Example -1

Here, J=Q’

D is the correct option

 Example -2

The above sequential circuit is built using JK flip-flops is initialized with Q2Q1Q0 =
000. The state sequence for this circuit for the next 3 clock cycle is
(A) 001, 010, 011
(B) 111, 110, 101
(C) 100, 110, 111
(D) 100, 011, 001

C is the correct option

D Flip Flop: Counter

Determine, What type of counter is shown above ?

It is a Modulo-16, UP Counter
 Basic shift register

A basic shift register is simply a chain of D flip-flops with a common clock.

serial D Q D Q D Q D Q
serial
input output

A B C D
clock

Each flip-flop transfers its D input to its Q output at a clock transition.

• The effect is to transfer data along the register, one flip-flop per clock
cycle.

This type of register is called a serial input-serial output (SISO).

• SISO
• SIPO
• PISO
• PIPO
 Basic shift register

Basic applications
Delay
Ring counters
Johnson counters

Conversion of data from serial to parallel and vice versa

A basic shift register is simply a chain of D flip-flops with a common clock.

serial input D Q D Q D Q D Q
serial
01001110 output

A B C D
clock

The table shows the contents of the

register after successive clock transitions. input QA QB QC QD
The assumption is that the register is 0 0 0 0 0
initially clear.

clock pulses
1 1 0 0 0
• The number of clock pulses needed to
1 1 1 0 0
fill the register is equal to the number of
flip-flops used to make the register. 1 1 1 1 0
• This is a 4 bit register. 0 0 1 1 1
0 0 0 1 1
1 1 0 0 1
0 0 1 0 0
 Timing for a shift register

clock

input

QA

QB

QC

QD tpd

The pattern in successive flip-flops moves to the right with each clock
cycle to shift the pattern into and out of the register.
 Timing for a shift register

clock

input

QA

QB

QC input QA QB QC QD
0 0 0 0 0
QD tpd
1 1 0 0 0
1 1 1 0 0
1 1 1 1 0
0 0 1 1 1
 Applications of a basic shift register
1. Delay line — N stages delay the signal by N clock cycles
2. Multiplication and division by powers of 2-

5 = 101 (binary)
5 * 2 = 10 = 1010 (binary) - just shifted all bits 1 position to the left
5 * 4 = 20 = 10100 (binary) - just shifted all bits 2 positions to the left
 Ring counter

A shift register with its output fed back to its input forms a ring counter.

D Q D Q D Q D Q output

A B C D
clock

This can be used to generate an arbitrary binary pattern of length N, where

N is the number of stages in the ring counter. It must be preloaded with the
sequence desired, which then rotates around the counter indefinitely.

One application is to divide down the clock frequency for a slower part of a
digital system, while keeping everything synchronous. Modern computers
have several ‘buses’ running at different speeds, where a ring counter is
used to create the clocks for the various buses.
 Johnson counter (Twisted Ring)
A ring counter with the complement of its output fed back is a Johnson
counter.

D Q D Q D Q D Q output

A B C D
clock

This generates longer sequences than a simple ring counter.

 Johnson counter
A ring counter with the complement of its output fed back is a Johnson
counter.
D Q D Q D Q output

A B C D
clock
QA QB QC

0 0 0
1 0 0
1 1 0
1 1 1
0 1 1
0 0 1
1 0 1
0 1 0
 Pseudo-random number generator
A ring counter with feedback through an exclusive-or gate makes a simple
pseudo-random number generator.

D Q D Q D Q D Q output

• Pseudo-random sequences of 1s and 0s have many applications,

notably in encryption. They appear to be random over ‘short’ times but
the sequence eventually repeats, hence the more accurate term
‘pseudo-random’.
• Also, they can be reproduced perfectly if you know both:
• the method used to generate the sequence
• the state in the sequence at which to start
• This is an important feature!
• The circuit above has a period of 24 – 1 = 15
• (the missing state is 0000 —why?).
1 0 0 0
0 1 0 0
0 0 1 0
1 0 0 1
1 1 0 0
0 1 1 0
1 0 1 1
0 1 0 1
1 0 1 0
1 1 0 1
1 1 1 0
1 1 1 1
0 1 1 1
0 0 1 1
0 0 0 1
1 0 0 0
 Pseudo-random binary sequences and encryption
your data (plain text) pseudo-random binary sequence

sender exclusive or

looks like binary

transmit data over
‘noise’ —
insecure link
apparently random

receiver
?
 Pseudo-random binary sequences and encryption
your data (plain text) pseudo-random binary sequence

sender exclusive or

looks like binary

transmit data over
‘noise’ —
insecure link
apparently random

same pseudo-random binary sequence

receiver if you exclusive-or a bit

? exclusive or
with the same value (0 or
1) twice, you get the
your data in plain text again initial value back again.
 Pseudo-random binary sequences and encryption
your data (plain text) pseudo-random binary sequence

sender exclusive or How do we ensure

that both sender
and receiver use
looks like binary the same pseudo-
transmit data over
‘noise’ — random binary
insecure link
apparently random sequence?

same pseudo-random binary sequence

receiver if you exclusive-or a bit

? exclusive or
with the same value (0 or
1) twice, you get the
your data in plain text again initial value back again.

This is the basis of the method used to encrypt data sent over the internet
(https) or with a digital mobile phone.
 Transmission of data — serial format
Data often has to be transmitted from one computer to another, or from a
computer to peripheral equipment (printer, modem, …). This can be done in:
• serial format, one bit at a time
• parallel format, several bits at a time (e.g. byte at a time, 8 bits)
Serial format is most commonly used because it is simpler. Only a few wires
are needed:
• traditional serial ‘COM’ ports (RS-232) need only 3 wires (transmitted
data, received data and ground — but more may be used for control)
• universal serial bus (USB, common on modern computers) uses 4
wires (two for differential data plus power and ground)

Traditional serial transmission was slow but modern systems use much
faster rates (USB version 1 up to 12 Mbits per second, FireWire 1 up to
400 Mbits per second), version 2 of both even faster.

simple serial
1 0 0 1 1 0 1 1 0 1 0 1
bit stream
 Parallel data
Where higher speed is required, several bits (usually a small number of
bytes, each of 8 bits) may be moved at once. More complicated connections
are needed — more wires. Common applications include:
• inside the processor itself, e.g. our microcontroller handles bytes
• inside a computer system on the bus (e.g. PCI) and interfaces to disk
drives (e.g. e.g. SCSI or IDE)— but these are now mainly serial

Interfaces have changed to serial because it is hard to ensure that all bits on
a parallel bus arrive at the same time at the high speed of modern systems.

How do you interface a serial device to a computer?

How do we interface an external device that transmits serially with the bus of
a computer that transfers one byte (8 bits) at a time?
• Use a shift register.
In practice this would almost certainly be buried inside a larger circuit called
a UART (universal asynchronous receiver transmitter) or something similar.
 Use of shift register to serialize data
parallel data in

parallel load
D Q D Q D Q D Q
serial
output

A B C D

Extra logic is added to the basic shift register so that all the flip-flops can be loaded
in parallel (simultaneously), controlled by a shift/load input.

Once the data have been loaded, the clock is enabled and the values are shifted
once per clock cycle. This causes the input data to be transferred to the output, one
bit at a time — serial output (PISO).

The opposite process is used to read in serial data, fill up the shift register, and
transfer it in parallel to a bus when the register is full (SIPO).

The register can also be parallel input – parallel output (PIPO).

 Review exercises
A shift register has 16 stages and is clocked at 1 MHz. How long does data
take to pass through it?

We wish to multiply a binary number by 8. How can this be done with a

shift register? In which direction should it operate?

A 4-bit ring counter is started with the pattern ABCD = 1100. What are its
subsequent states after the clock is turned on?

Prove that a bit returns to its original value, either 0 or 1, after two
exclusive-or operations with the same value, whether this is 0 or 1
Try to work out the sequence produced by the 4-stage pseudo-random
number generator described in the lecture. Start at ABCD = 1000.
(What would happen if you started with 0000?)
Example -1
D CLK Q0 Q1 Q2 Q3
1 - 1 0 0 0
1 1 1 1 0 0
0 2 1 1 1 0
0 3 0 1 1 1
0 4 0 0 1 1
1 5 0 0 0 1
1 6 1 0 0 0

D = XOR(Q0, Q2, Q3)

D CLK Q0 Q1 Q2 Q3
1 - 0 0 1 ?
1 1 0 0 1
Example -2
STATE MACHINES