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MAC Unit Using Carry Lookahead Adder and Wallace Tree Multiplier

The document summarizes a MAC (multiply-accumulate) unit that uses carry lookahead adders and Wallace tree multipliers. It contains block diagrams of the MAC unit and descriptions of its components. The MAC unit uses two multipliers and two adders to process four inputs in parallel, providing higher speed than a single-multiplier single-adder design while modestly increasing costs. It multiplies two pairs of four-bit numbers simultaneously, adds the results, and accumulates the sums in the accumulator register with each clock cycle.

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93 views11 pages

MAC Unit Using Carry Lookahead Adder and Wallace Tree Multiplier

The document summarizes a MAC (multiply-accumulate) unit that uses carry lookahead adders and Wallace tree multipliers. It contains block diagrams of the MAC unit and descriptions of its components. The MAC unit uses two multipliers and two adders to process four inputs in parallel, providing higher speed than a single-multiplier single-adder design while modestly increasing costs. It multiplies two pairs of four-bit numbers simultaneously, adds the results, and accumulates the sums in the accumulator register with each clock cycle.

Uploaded by

Anand
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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MAC unit using

Carry lookahead adder and


Wallace tree multiplier
Done by
M.K.Sanju Vikasini-EVD16I007
Monika Shree K-EVD16I012
Carry look ahead adder
A carry look-ahead adder reduces the propagation delay by introducing more complex hardware. A carry-look ahead adder
improves speed by reducing the amount of time required to determine carry bits.

RCA- each stage must wait until the previous carry bit.

CLA- calculates one or more carry bits before the sum.


ALGORITHM
carry generate Gi and ‘carry propagate Pi

The sum output and carry output can be expressed as


Wallace tree multiplier- Algorithm
Wallace tree multiplication algorithm is divided into three major steps-
1. Generation of partial products
2. Addition of partial products
3. Generation of final results from the partial products
Wallace tree multiplier- Architecture

Advantage of the Wallace tree is small delay. Logic levels required to perform the summation can be
reduced.But it requires lot of hardware.
ALGORITHM
Various stages in Wallace tree Multiplier
● The multipliers and multiplicands are denoted by ‘ai’ and ‘bi’ respectively, where i =0,1,..3 for 4 bit
multiplier.

● At first, the partial products are generated by multiplying multiplicands and multipliers that is they are
the result of simple AND gates.All partial products are obtained simultaneously.

● Partial products present in first three successive rows are added using half adders and full adders to
generate ri and ci, where i =0,1,2..,5. ri are the sum bits and ci are the carry out bits of the adders of
the previous stage.

● ci, ri, and the partial products present in fourth row are further added to generate the sum pi and
carryout bits c_i where i=0,1,2..6.

● Carry c_i, and Pi are added in the final step to generate sum and carry which are denoted by si and
C6, where i= 0,1,..,6 which forms 8-bit output.
MAC UNIT -BLOCK DIAGRAM
Description of MAC unit
● This is a semi-parallel configuration optimised for medium speed and cost by using two multipliers
and two adders for getting higher speed by processing four inputs at a time instead of two inputs.
And at the same time, the overall cost of the system slightly increases due to the increase in number
of resources as compared to the case of single multiplier and single adder mac unit.
● Two four bit numbers I1 and I2 are given to the first multiplier. At the same time another pair of four
bit numbers I3 and I4 are given to second multiplier. Both multiplication happens parallely.
● Output from both the multipliers are given as input to the first adder and sum is sent to the main
adder.
● The main adder adds the sum output of the first adder with the value stored in the
accumulator.Finally,accumulator is updated with the sum output of the main adder.
● Now another set of four inputs are fed to the multipliers.
● The sum output of the first adder for the new set of inputs is added with the value present in the
accumulator using the main adder and the accumulator is updated accordingly.
● The above steps are repeated for every set of four inputs.
Thank You

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