Analog &digital VLSI DESIGN: Instructor: Dr. Darshak K Bhatt

Analog &Digital VLSI DESIGN
Instructor: Dr. Darshak K Bhatt
BITS Pilani,Goa Campus

Lec:2

Inverter Design
 Design of NMOS inverter given a set of performance
metrics
 Compare different design options of inverters.

Inverter Design
 Design of NMOS inverter given a set of performance
metrics
 Compare different design options of inverter.
Exercise: Determine the W/L ration of the NMOST and

value of load resistor RL required to design a resistive
load inverter circuit with VOL = 0.4V, for a given process
dependent parameters of NMOST.
A B = A’
Vout
Vth
1 0
0 VDD/2 VDD Vin

Definition of Noise Margins
"1"
V
OH
NMH
V
Noise Margin High IH
Undefined
Region
Noise Margin Low
NML VIL
V
OL
"0"
Gate Output Gate Input
 Example: VIL(max)= 0.7 V, VIH(min)=1.4 V,

VOH(min)=1.7 V, VOL(max)=0.2 V

Noise Margin
NM L  VIL  VOL
NM H  VOH  VIH
Fan-in and Fan-out
(a) Fan-out N
M
(b) Fan-in M
N

Resistive Load Inverter
Driver transistor
ID( Vin, Vout) = IL( VL)

Voltage transfer characteristics found by solving the equation analytically
For nMOST
ID = 0 for VGS < VT
ID(lin) = n (Cox/2 )(W/L) [ 2(VGS- V TO) VDS – VDS2]
for VGS > = VT

VDS < VGS – VT
ID( sat) = n (Cox/2 )(W/L) [ (VGS- V TO)2] (1+ VDS)

for VGS >= VT
and VDS >= VGS - VT

For very low input voltage output
Vout voltage Vout is equal to high value of VOH.
dVout/dVin = -1
VOH
Driver nMOS is cut-off – no current thro
it.
As the input voltage Vin increases, the

driver transistor starts conducting a
certain current, and the output voltage
starts to decrease.
dVout/dVin = -1
VOL
Vin
VILVTH VIH

The drop in the output voltage is gradual.
Two critical points in the graph.
dVout/dVin = -1
VIL: Maximum input voltage which can be interpreted as logic ‘0’
VIH: Minimum input voltage which can be interpreted as logic ‘1’
As the input voltage is further increased , output voltage continue to drop

and reaches a value of VOL when input voltage is equal to VOH
Inverter threshold voltage Vth, is the transition voltage is at the point where
Vin = Vout
VOL ( min) , VOH (max)

Mapping between analog
and digital signals
V V(y)
"1" OH
Slope = -1
V V
IH OH
Undefined
Region
Slope = -1
V
IL VOL
"0"
V
OL V V
IL IH V(x)

Resistive load inverter
- nMOS transistor is the driver device.
-Load is a resistor RL.
Drain current ID = Load current IR
Taking VSB = 0
Threshold voltage of the driver transistor is VTO

Input voltage range Operating Mode
Vin < VTO cut-off
VTO<= Vin < Vout + VTO saturation
Vin >= Vout + VTO linear

VOH :
Vout = VDD – IR. RL.
when input voltage is low, i.e., less than the threshold

voltage of the MOST, driver transistor will be in cutoff.
ID = IR = 0
VOH = VDD

VOL:
VOL:
To calculate VOL , assume that the input voltage is VOH. i.e., Vin
= VOH = VDD
Since Vout >VIN – VTO, driver transistor operates in linear
region.
IR = ( VDD – Vout)/ RL
( I R = I D)
( VDD – Vout)/ RL = kn/2 [ 2(VDD- V TO) VOL – VOL2]
Solving for VOL
VOL = VDD- VTO +1/knRL – ((VDD-VTO + I/knRL)2 –2VDD/knRL))1/2

VIL:
VIL:
VIL is the smaller of the two input voltage values at which the
slope of the VTC becomes equal to ( -1). By inspection when input
is VIL , output is only slightly smaller than VOH.
Vout > Vin – VTO driver transistor operates in saturation.

( VDD – Vout)/ RL = kn/2 [ (Vin- V TO)2]
Differentiating both the sides with respect to Vin
(-1/RL) dVout/dVin = kn ( Vin – VTO) , substituting dVout/dVin = -1
VIL = VTO + 1/knRL.

Vout ( Vin = VIL) = VDD - (1/2knRL)
VIH:
VIH:
VIH is the larger of the two points on the VTC in which slope is
equal to ( -1).
By inspection when Vin = VIH, Vout is only slightly larger than VOL.
Hence, VOUT < VIN – VTO , driver transistor operates in linear
region.
( VDD – Vout)/ RL = kn/2 [ 2(Vin- V TO) Vout – V out2]
Differentiating Vout with respect to Vin
substituting dVout/dVin = -1 and also Vin = VIH

VIH = VTO + 2VOUT - 1/knRL.
Using the two equations with two unknowns Vout and VIH
Solving gives
Vout ( Vin = VIH) = ( 2.VDD/3.kn.RL)1/2.
and
VIH = VTO + (8.VDD/3.kn.RL)1/2 - 1/knRL.
The four critical points

VIH, VIL, VOH, VOL help calculate noise margin.
Vth can be found by solving Vin = Vout = Vth.

Vout VDD = 5V
VTO = 1V
knRL = 2 V-1
knRL =4 V-1
knRL = 8 V-1
Vin
knRL is the design parameter.

Power Consumption:
The average power consumption of a resistive load inverter circuit is

found by considering
Vin= VOL(low) and Vin = VOH ( high)
When Vin = VOL driver transistor cut-off ( ID = IR = 0) and the DC

power dissipation is zero.
When Vin = VOH driver and load conduct a non zero current. Vout
= VOL
ID = IR = (VDD- VOL) /RL
PDC(average) = VDD/2.( VDD- VOL) RL.

Chip area occupied by Inverter depends on
-W/L ratio of driver to transistor

-RL
Choosing a particular L we can find W/L
Resistor area depends on the technology used to fabricate resistor on the chip.
Diffused resistor and polysilicon resistor.
In diffused resistor resistance determined by doping density of diffusion region

and the dimensions. ( practical values of sheet resistance 100/square)- large
length to width ratio needed to get in order of k .
Undoped polysilicon with high sheet resistivity 10 M/square. Controlling

resistor values difficult.

Example 5.2 - Inverter Design
 Resistive-load inverter circuit

 VDD=1.2V, kn’=102μA/V2
 VT0=0.48V, RL=20kΩ, W/L=4
 Calculate (VOL, VOH, VIL, VIH)
 Find the noise margins
VOH  VDD  1.2V kn = kn' (W/L) = 408 μA/V2, (kn∙RL) = 8.16 V-1.
2
1  1  2 VDD 1 1
VOL  VDD  VT 0    VDD  VT 0    VIL  VT 0   0.48   0.603V
kn RL  kn RL  kn RL kn RL 8.16
 1  2 1.2
2 8 VDD 1 8 1.2 1
 1.2  0.48 
1
 1.2  0.48  VIH  VT 0     0.48     0.984V
  3 kn RL kn RL 3 8.16 8.16
8.16  8.16  8.16
NM L  VIL  VOL  0.603  0.198  0.405V Poor noise immunity

 0.198V
NM H VOH  VIH  1.2  0.984  0.216V < 0.3V = 25% of VDD

Design a Resistive load nMOS inverter with R = 1k such that
VOL = 0.6V.
NMOS transistor parameters of K’ n = 22 μA/v2, γ = 0.2 V1/2
VDD = 5V; VT0 = 1V
(i) Determine W/L
(ii) Determine VIL and VIH
(iii) Determine noise margin NML and NMH
BITS Pilani, Pilani Campus

CMOS Inverter
VDD It consists of an enhancement-

type nMOS transistor and an
enhancement type pMOS
transistor.
Push-pull arrangement
Vin
Vout -for high input, nMOS pulls
down the output node while
CL pMOS acts as load
-for low input pMOS pulls up

the output node while the nMOS
acts as the load.
BITS Pilani, Pilani Campus

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Analog &Digital VLSI DESIGN

Instructor: Dr. Darshak K Bhatt

BITS Pilani,Goa Campus

BITS Pilani,Goa Campus

 Compare different design options of inverters.

BITS Pilani,Goa Campus

 Compare different design options of inverter.

Exercise: Determine the W/L ration of the NMOST and

0 VDD/2 VDD Vin

BITS Pilani,Goa Campus

Gate Output Gate Input

 Example: VIL(max)= 0.7 V, VIH(min)=1.4 V,

BITS Pilani,Goa Campus

BITS Pilani,Goa Campus

ID( Vin, Vout) = IL( VL)

ID(lin) = n (Cox/2 )(W/L) [ 2(VGS- V TO) VDS – VDS2]

for VGS > = VT

ID( sat) = n (Cox/2 )(W/L) [ (VGS- V TO)2] (1+ VDS)

BITS Pilani,Goa Campus

As the input voltage Vin increases, the

BITS Pilani,Goa Campus

Two critical points in the graph.

VIL: Maximum input voltage which can be interpreted as logic ‘0’

VIH: Minimum input voltage which can be interpreted as logic ‘1’

As the input voltage is further increased , output voltage continue to drop

VOL ( min) , VOH (max)

BITS Pilani,Goa Campus

- nMOS transistor is the driver device.

-Load is a resistor RL.

Drain current ID = Load current IR

Threshold voltage of the driver transistor is VTO

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Vin < VTO cut-off

VTO<= Vin < Vout + VTO saturation

Vin >= Vout + VTO linear

BITS Pilani,Goa Campus

Vout = VDD – IR. RL.

when input voltage is low, i.e., less than the threshold

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Solving for VOL

VOL = VDD- VTO +1/knRL – ((VDD-VTO + I/knRL)2 –2VDD/knRL))1/2

Vout > Vin – VTO driver transistor operates in saturation.

Differentiating both the sides with respect to Vin

(-1/RL) dVout/dVin = kn ( Vin – VTO) , substituting dVout/dVin = -1

VIL = VTO + 1/knRL.

Differentiating Vout with respect to Vin

substituting dVout/dVin = -1 and also Vin = VIH

Vout ( Vin = VIH) = ( 2.VDD/3.kn.RL)1/2.

VIH = VTO + (8.VDD/3.kn.RL)1/2 - 1/knRL.

The four critical points

Vth can be found by solving Vin = Vout = Vth.

knRL is the design parameter.

The average power consumption of a resistive load inverter circuit is

When Vin = VOL driver transistor cut-off ( ID = IR = 0) and the DC

ID = IR = (VDD- VOL) /RL

PDC(average) = VDD/2.( VDD- VOL) RL.

-W/L ratio of driver to transistor

Diffused resistor and polysilicon resistor.