EMBEDDED SYSTEMS DESIGN

UCS614

ASSIGNMENT 1-4

Submitted to

Mr. Mainak Adhikari

Submitted by

Pankaj Gupta
101603215
COE-15

DEPARTMENT OF COMPUTER SCIENCE & ENGINEERING

PATIALA-147004, PUNJAB
INDIA
JAN-MAY 2019
 ASSIGNMENT – 01
Implementation of basic logic gates
1. AND gate

module and1(S,a,b);
output S;
input a,b;
assign S = a&b;
endmodule

module and_test;
reg a,b;
wire S;
and1 an1(S,a,b);
initial begin
a=0; b=1; #10;
a=1; b=0; #10;
a=0; b=0; #10;
a=1; b=1; #10;
$finish;
end
initial begin
$monitor("a=%d and b=%d s=%d",a,b,S);
end
endmodule

2. OR gate
module or1(S,a,b);
output S;
input a,b;
assign S = a|b;
endmodule

module or_test;
reg a,b;
wire S;
or1 an1(S,a,b);
initial begin
a=0; b=1; #10;
a=1; b=0; #10;
a=0; b=0; #10;
 a=1; b=1; #10;
$finish;
end
initial begin
$monitor("a=%d and b=%d s=%d",a,b,S);
end
endmodule

3. NAND gate

module nand1(S,a,b);
output S;
input a,b;
assign S = ~(a&b);
endmodule

module nand_test;
reg a,b;
wire S;
nand1 an1(S,a,b);
initial begin
a=0; b=1; #10;
a=1; b=0; #10;
a=0; b=0; #10;
a=1; b=1; #10;
$finish;
end
initial begin
$monitor("a=%d and b=%d s=%d",a,b,S);
end
endmodule
4. NOR gate

module nor1(S,a,b);
output S;
input a,b;
assign S = ~(a^b);
endmodule
module nor_test;
reg a,b;
wire S;
nor1 an1(S,a,b);
initial begin
a=0; b=1; #10;
a=1; b=0; #10;
a=0; b=0; #10;
a=1; b=1; #10;
$finish;
end
initial begin
$monitor("a=%d and b=%d s=%d",a,b,S);
end
endmodule

5. Inverter gate

module inv1(S,a);
output S;
input a;
assign S = ~a;
endmodule

module inv_test;
reg a;
wire S;
inv1 an1(S,a);
initial begin
a=0; #10;
a=1; #10;

$finish;
 end
initial begin
$monitor("a=%d s=%d",a,S);
end
endmodule
 ASSIGNMENT – 02
Application of Basic Gates

1. NAND gate using basic gates.

module nand11(S,a,b);
output S;
input a,b;
wire d;
and1 u1 (d,a,b);
inv1 u2 (S,d);
endmodule

module nand_test1;
reg a,b;
wire S;
nand11 an1(S,a,b);
initial begin
a=0; b=1; #10;
a=1; b=0; #10;
a=0; b=0; #10;
a=1; b=1; #10;
$finish;
end
initial begin
$monitor("a=%d and b=%d s=%d",a,b,S);
end
endmodule

2. NOR gate using basic gates.

module nor11(S,a,b);
output S;
input a,b;
wire d;
or1 u1 (d,a,b);
inv1 u2 (S,d);
endmodule
 module nor_test1;
reg a,b;
wire S;
nor11 an1(S,a,b);
initial begin
a=0; b=1; #10;
a=1; b=0; #10;
a=0; b=0; #10;
a=1; b=1; #10;
$finish;
end
initial begin
$monitor("a=%d and b=%d s=%d",a,b,S);
end
endmodule

3. XOR gate using basic gates.

module xor1(S,a,b);
output S;
input a,b;
wire d,e,f,g;
inv1 u1 (d,a);
inv1 u2 (e,b);
and1 u3 (f,a,e);
and1 u4 (g,d,b);
or1 u5 (S,f,g);
endmodule

module xor_test1;
reg a,b;
wire S;
xor1 an1(S,a,b);
initial begin
a=0; b=1; #10;
a=1; b=0; #10;
a=0; b=0; #10;
a=1; b=1; #10;
$finish;
end
initial begin
 $monitor("a=%d and b=%d s=%d",a,b,S);
end
endmodule

4. XNOR gate using basic gates.

module xnor1(S,a,b);
output S;
input a,b;
wire d,e,f,g;
inv1 u1 (d,a);
inv1 u2 (e,b);
and1 u3 (f,a,b);
and1 u4 (g,d,e);
or1 u5 (S,f,g);
endmodule

module xnor_test1;
reg a,b;
wire S;
xnor1 an1(S,a,b);
initial begin
a=0; b=1; #10;
a=1; b=0; #10;
a=0; b=0; #10;
a=1; b=1; #10;
$finish;
end
initial begin
$monitor("a=%d and b=%d s=%d",a,b,S);
end
endmodule
 ASSIGNMENT – 03
Adders
1. Half Adder

module ha1(S,C,a,b);
output S,C;
input a,b;
xor1 u1 (S,a,b);
and1 u2 (C,a,b);
endmodule

module ha_test1;
reg a,b;
wire S,C;
ha1 an1(S,C,a,b);
initial begin
a=0; b=1; #10;
a=1; b=0; #10;
a=0; b=0; #10;
a=1; b=1; #10;
$finish;
end
initial begin
$monitor("a=%d and b=%d s=%d c=%d",a,b,S,C);
end
endmodule

2. Full Adder

module fa1(S,C0,a,b,c);
output S,C0;
input a,b,c;
wire p,q,r,s;
xor1 u1 (p,a,b);
xor1 u2 (S,p,c);
and1 u3 (q,a,b);
and1 u4 (r,c,p);
or1 u5 (C0,q,r);
endmodule

module fa_test1;
reg a,b,c;
 wire S,C0;
fa1 an1(S,C0,a,b,c);
initial begin
a=0; b=1; c=0; #10;
a=1; b=0; c=0; #10;
a=0; b=0; c=0; #10;
a=1; b=1; c=0; #10;
a=0; b=1; c=1; #10;
a=1; b=0; c=1; #10;
a=0; b=0; c=1; #10;
a=1; b=1; c=1; #10;
$finish;
end
initial begin
$monitor("a=%d and b=%d and c=%d s=%d c=%d",a,b,c,S,C0);
end
endmodule
 ASSIGNMENT – 04
Subtractors
1. Half Subtractor

module hs1(D,B0,a,b);
output D,B0;
input a,b;
wire x;
xor1 u1 (D,a,b);
inv1 u2 (x,a);
and1 u3 (B0,x,b);
endmodule

module hs_test1;
reg a,b;
wire D,B0;
hs1 an1(D,B0,a,b);
initial begin
a=0; b=1; #10;
a=1; b=0; #10;
a=0; b=0; #10;
a=1; b=1; #10;
$finish;
end
initial begin
$monitor("a=%d and b=%d D=%d B0=%d",a,b,D,B0);
end
endmodule

2. Full Subtractor

module fs1(D,B0,a,b,c);
output D,B0;
input a,b,c;
wire p,q,r,s,t;
xor1 u1 (p,a,b);
xor1 u2 (D,p,c);
inv1 u3 (q,a);
and1 u4 (r,q,b);
inv1 u5 (s,p);
and1 u6 (t,s,c);
 and1 u7 (B0,r,t);

endmodule

module fs_test1;
reg a,b,c;
wire S,C0;
fs1 an1(S,C0,a,b,c);
initial begin
a=0; b=1; c=0; #10;
a=1; b=0; c=0; #10;
a=0; b=0; c=0; #10;
a=1; b=1; c=0; #10;
a=0; b=1; c=1; #10;
a=1; b=0; c=1; #10;
a=0; b=0; c=1; #10;
a=1; b=1; c=1; #10;
$finish;
end
initial begin
$monitor("a=%d and b=%d and c=%d s=%d c=%d",a,b,c,S,C0);
end
endmodule