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3 Vlsi Design (Elective III)

This document is an exam for the course VLSI Design (Elective-III) for students of Electronics and Communication Engineering. It contains 8 questions covering topics related to IC production processes, MOSFET transistor characteristics, basic logic gates, switch logic arrangements, structured design approaches for circuits like parity generators and carry bypass adders, programmable logic design approaches, VHDL synthesis, CMOS testing and layout design for testability. Students are required to answer any 5 questions out of the 8 questions provided.

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Rohith Sai Rohi
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122 views1 page

3 Vlsi Design (Elective III)

This document is an exam for the course VLSI Design (Elective-III) for students of Electronics and Communication Engineering. It contains 8 questions covering topics related to IC production processes, MOSFET transistor characteristics, basic logic gates, switch logic arrangements, structured design approaches for circuits like parity generators and carry bypass adders, programmable logic design approaches, VHDL synthesis, CMOS testing and layout design for testability. Students are required to answer any 5 questions out of the 8 questions provided.

Uploaded by

Rohith Sai Rohi
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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CODE No.

:10BT60405

SREE VIDYANIKETHAN ENGINEERING COLLEGE


(An Autonomous Institution, Affiliated to JNTUA, Anantapur)
III B.Tech II Semester (SVEC10) Regular/Supplementary Examinations June - 2014
VLSI DESIGN (ELECTIVE-III)
[ Electronics and Communication Engineering ]

Time: 3 hours Max Marks: 70


Answer any FIVE questions
All questions carry equal marks

1. a) Explain step-by-step procedure for a typical n-well process with neat diagrams.
b) Explain the concepts of 'Lithography' and 'Probe testing' related to IC production Process.

2. a) Derive an equation for Transconductance of an n channel enhancement MOS- FET


operating in active region.
b) A PMOS transistor is operated in triode region with the following parameters.
VGS=- 4.5V, Vtp= -1V, VDS=-2.2 V, (W/L) =95, μnCox =95μA/V 2. Find its drain
current and drain source resistance.

3. a) Draw the stick diagram for NAND gate and give its procedural steps.
b) Discuss the limitations of scaling of MOS circuits.

4. a) What is meant by Switch Logic? Explain some switch logic arrangements.


b) What are the basic MOS circuit concepts? Explain the concept of sheet resistance
applied to MOS Transistors and Inverters.

5. a) Draw and explain the structured design approach of a parity generator.


b) Present the design approach for a Carry Bypass Adder with neat diagram.

6. a) Explain semiconductor integrated circuit design approach using programmable


logic arrays.
b) Compare the performance parameters of Complex Programmable Logic Devices
and Field Programmable Gate Arrays.

7. a) Draw the block diagram of synthesis process and illustrate with an example.
b) Describe VHDL synthesis approach with an example.

8. a) What is meant by CMOS testing? Explain the need for testing.


b) Discuss about layout design for improved testability. Consider a suitable example.



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