EMBEDDED

LAB ASSIGNMENT

Project : Car Parking System

Submitted by:

Purnima Tayal (101783034)

Pranav Partaap (101610068)
Sanchit Nayyar (101603302)
Shagun Verma (101601153)

COE-21

Submitted to:

Asst. Prof. Jasleen

THAPAR INSTITUTE OF
ENGINEERING & TECHNOLOGY

1|P a g e
Q1) Write a program in verilog to print Hello World?

Sol:-
module hello;
initial begin
$display ("Hello world");
#10
$finish;
end
endmodule

2|P a g e
Q2) Write a program in verilog to show the outputs of AND, OR, NOR,
NAND, XOR, XNOR and NOT gates using gate level modeling. Verify
logic using truth table.

Sol:-
module gates(a,b,c,d,e,f,g,h);
input a,b;
output c,d,e,f,g,h;
and a2(c,a,b);
or o2(d,a,b);
nand na2(e,a,b);
nor no2(f,a,b);
xor xo2(g,a,b);
xnor xno2(h,a,b);
endmodule

module test;
reg x,y;
wire x1,y1,x2,y2,x3,y3;
gates g1(x,y,x1,y1,x2,y2,x3,y3);

initial begin
$display("A\tB\tAND\tOR\tNAND\tNOR\tXOR\tXNOR");
$monitor("%b\t%b\t%b\t%b\t%b\t%b\t%b\t%b",x,y,x1,y1,x2,y2,x3,y3);
x=0;y=0;
#10
x=0;y=1;
#10
x=1;y=0;
#10
x=1;y=1;
#10
$finish;
end
endmodule

3|P a g e
Q3) Write a verilog program to verify AND, OR, NOR, NAND, XOR, XNOR
and NOT gates using timing diagram?

Sol: -
module gates(a,b,c,d,e,f,g,h);
input a,b;
output c,d,e,f,g,h;
and a2(c,a,b);
or o2(d,a,b);
nand na2(e,a,b);
nor no2(f,a,b);
xor xo2(g,a,b);
xnor xno2(h,a,b);
endmodule

module test;
reg x,y;
wire x1,y1,x2,y2,x3,y3;
gates g1(x,y,x1,y1,x2,y2,x3,y3);

initial begin
$dumpfile("first.vcd");
$dumpvars(0,test);
$display("A\tB\tAND\tOR\tNAND\tNOR\tXOR\tXNOR");
$monitor("%b\t%b\t%b\t%b\t%b\t%b\t%b\t%b",x,y,x1,y1,x2,y2,x3,y3);
x=0;y=0;
#10
x=0;y=1;
#10
x=1;y=0;
#10
x=1;y=1;
#10
$finish;
end
endmodule

4|P a g e
5|P a g e
Q4) Write a program in verilog to show the outputs of AND, OR, NOR,
NAND, XOR, XNOR and NOT gates using data flow modeling. Verify logic
using truth table.

Sol: -
module gates(a,b,c,d,e,f,g,h);
input a,b;
output c,d,e,f,g,h;
assign c = a&b;
assign d = a|b;
assign e = ~(a&b);
assign f = ~(a|b);
assign g = a^b;
assign h = ~(a^b);
endmodule

module test;
reg x,y;
wire x1,y1,x2,y2,x3,y3;
gates g1(x,y,x1,y1,x2,y2,x3,y3);
initial begin
$display("A\tB\tAND\tOR\tNAND\tNOR\tXOR\tXNOR");
$monitor("%b\t%b\t%b\t%b\t%b\t%b\t%b\t%b",x,y,x1,y1,x2,y2,x3,y3);
x=0;y=0;
#10
x=0;y=1;
#10
x=1;y=0;
#10
x=1;y=1;
#10
$finish;
end
endmodule

6|P a g e
Q5) Write a program in verilog to show the Half Adder using AND, XOR
gate using gate level modeling. Verify logic using truth table.

Sol: -
module adderhalf(a,b,s,c);
input a,b;
output s,c;
xor xo2(s,a,b);
and a2(c,a,b);
endmodule

module test;
reg x,y;
wire x1,y1;
adderhalf a1(x,y,x1,y1);

initial begin
$dumpfile("adderhalf.vcd");
$dumpvars(0,test);
$display("A\tB\tSUM\tCarry");
$monitor("%b\t%b\t%b\t%b",x,y,x1,y1);
x=0;y=0;
#10
x=0;y=1;
#10
x=1;y=0;
#10
x=1;y=1;
#10
$finish;
end
endmodule

7|P a g e
8|P a g e
Q6) Write a program in verilog to show the Full Adder using AND, XOR
gate using gate level modeling. Verify logic using truth table.

Sol: -
module adderfull(a,b,c,s,cr);
input a,b,c;
output s,cr,d,e,f;
xor xo1(s,a,b,c);
and a1(d,a,b);
and a2(e,b,c);
and a3(f,c,a);
or o1(cr,d,e,f);
endmodule

module test;
reg x,y,z;
wire x1,y1;
adderfull a1(x,y,z,x1,y1);

initial begin
$dumpfile("adderfull.vcd");
$dumpvars(0,test);
$display("A\tB\tC\tSUM\tCarry");
$monitor("%b\t%b\t%b\t%b\t%b",x,y,z,x1,y1);
x=0;y=0;z=0;
#10
x=0;y=0;z=1;
#10
x=0;y=1;z=0;
#10
x=0;y=1;z=1;
#10
x=1;y=0;z=0;
#10
x=1;y=0;z=1;
#10
x=1;y=1;z=0;
#10
x=1;y=1;z=1;
#10
$finish;
end
endmodule

9|P a g e
10 | P a g e
Q7) Write a program in verilog to show the Half Subtractor using AND,
XOR gate using gate level modeling. Verify logic using truth table.

Sol: -
module subhalf(a,b,d,br);
input a,b;
output d,br;
xor xo1(d,a,b);
and a1(br,~a,b);
endmodule

module test;
reg x,y;
wire x1,y1;
subhalf a1(x,y,x1,y1);

initial begin
$dumpfile("subhalf.vcd");
$dumpvars(0,test);
$display("A\tB\tDiff\tBorrow");
$monitor("%b\t%b\t%b\t%b",x,y,x1,y1);
x=0;y=0;
#10
x=0;y=1;
#10
x=1;y=0;
#10
x=1;y=1;
#10
$finish;
end
endmodule

11 | P a g e
12 | P a g e
Q8) Write a program in verilog to show the Full Subtractor using AND,
XOR gate using gate level modeling. Verify logic using truth table.

Sol: -
module subfull(a,b,c,d,br);
input a,b,c;
output d,br,e,f,g;
xor xo1(d,a,b,c);
and a1(e,~a,c);
and a2(f,~a,b);
and a3(g,b,c);
or o1(br,e,f,g);
endmodule

module test;
reg x,y,z;
wire x1,y1;
subfull a1(x,y,z,x1,y1);

initial begin
$dumpfile("subfull.vcd");
$dumpvars(0,test);
$display("A\tB\tC\tDiff\tBorrow");
$monitor("%b\t%b\t%b\t%b\t%b",x,y,z,x1,y1);
x=0;y=0;z=0;
#10
x=0;y=0;z=1;
#10
x=0;y=1;z=0;
#10
x=0;y=1;z=1;
#10
x=1;y=0;z=0;
#10
x=1;y=0;z=1;
#10
x=1;y=1;z=0;
#10
x=1;y=1;z=1;
#10
$finish;
end
endmodule

13 | P a g e
14 | P a g e
Q9) Write a program in verilog to show the encoder using case statement.
Verify logic using truth table and timing diagram.

Sol: -
module encoder(in, out);
input [3:0]in;
output [1:0]out;
reg out;
always @(*)
begin
case(in)
4'b0001:out=2'b00;
4'b0010:out=2'b01;
4'b0100:out=2'b10;
4'b1000:out=2'b11;
endcase
end
endmodule

module test;
reg [3:0]in;
wire [1:0]out;
encoder e1(in, out);

initial begin
$dumpfile("encoder.vcd");
$dumpvars(0,test);
$display("IN3 \t IN2 \t IN1 \t IN0 \t OUT1 \t OUT0");
$monitor("%b \t %b \t %b \t %b \t %b \t %b", in[3], in[2], in[1], in[0], out[1], out[0]);
in=4'b0001;
#10
in=4'b0010;
#10
in=4'b0100;
#10
in=4'b1000;
#10
$finish;
end
endmodule

15 | P a g e
16 | P a g e
Q10) Write a program in verilog to show the adder using case statement.
Verify logic using truth table and timing diagram.

Sol: -
module adder(a,b,s,cr);
input a,b;
output s,cr;
reg s, cr;
always @(a or b)
begin
s = a^b;
cr = a&b;
end
endmodule

module test;
reg x,y;
wire x1,y1;
adder a1(x,y,x1,y1);

initial begin
$dumpfile("adder.vcd");
$dumpvars(0,test);
$display("A\tB\tSUM\tCarry");
$monitor("%b\t%b\t%b\t%b",x,y, x1,y1);
x=0;y=0;
#10
x=0;y=1;
#10
x=1;y=0;
#10
x=1;y=1;
#10
$finish;
end
endmodule

17 | P a g e
18 | P a g e
Q11) Write a program in verilog to show the decoder using case
statement. Verify logic using truth table and timing diagram.

Sol: -
module decoder(in, out);
input [1:0]in;
output [3:0]out;
reg out;
always @(*)
begin
case(in)
2'b00:out=4'b0001;
2'b01:out=4'b0010;
2'b10:out=4'b0100;
2'b11:out=4'b1000;
endcase
end
endmodule

module test;
reg [1:0]in;
wire [3:0]out;
decoder e1(in, out);

initial begin
$dumpfile("decoder.vcd");
$dumpvars(0,test);
$display("IN1 \t IN0 \t OUT3 \t OUT2 \t OUT1 \t OUT0");
$monitor("%b \t %b \t %b \t %b \t %b \t %b", in[1], in[0], out[3], out[2], out[1], out[0]);
in=2'b00;
#10
in=2'b01;
#10
in=2'b10;
#10
in=2'b11;
#10
$finish;
end
endmodule

19 | P a g e
20 | P a g e
Q12) Write a program in verilog to show the MUX using case statement.
Verify logic using truth table and timing diagram.

Sol: -
module mux(in0, in1, sel, muxout);
input in0, in1, sel ;
output muxout;
wire muxout;
assign muxout = (sel) ? in0 : in1;
endmodule

module test;
reg in0;
reg in1;
reg sel;
wire muxout;
mux m1(in0, in1, sel, muxout);

initial begin
$dumpfile("mux.vcd");
$dumpvars(0,test);
$display("SEL \t IN1 \t IN0 \t MUXOUT");
$monitor("%b \t %b \t %b \t %b ", sel, in1, in0, muxout);
in1=1'b0;
in0=1'b0;
sel=1'b0;
#10
in1=1'b1;
in0=1'b0;
sel=1'b0;
#10
in1=1'b0;
in0=1'b1;
sel=1'b0;
#10
in1=1'b1;
in0=1'b1;
sel=1'b0;
#10
in1=1'b0;
in0=1'b0;
sel=1'b1;
#10
in1=1'b1;
in0=1'b0;
sel=1'b1;

21 | P a g e
#10
in1=1'b0;
in0=1'b1;
sel=1'b1;
#10
in1=1'b1;
in0=1'b1;
sel=1'b1;
#10
$finish;
end
endmodule

22 | P a g e
Q13) Write a program in verilog to show SR Flip-flop using case
statement. Verify logic using truth table and timing diagram.

Sol: -
module flipflop(sr,clk,q,qb);
input [1:0] sr;
input clk;
output q,qb;
reg q,qb;
initial q=0;
always @(posedge clk)
begin
case(sr)
2'b00:q=q;
2'b01:q=0;
2'b10:q=1;
2'b11:q=1'bz;
endcase
qb=~q;
end
endmodule

module test;
reg [1:0]sr;
reg clk,i;
wire q,qb;
flipflop fp(sr,clk,q,qb);

initial begin
$dumpfile("abc.vcd");
$dumpvars(0,test);
$display("sr\t clk \t q \t qb");
$monitor("%b\t %b\t %b\t %b\t",sr,clk,q,qb);
sr=2'b00;
#10 sr=2'b01;
#10 sr=2'b10;
#10 sr=2'b11;
#10
$finish;
end

initial begin
clk=0;
for(i=0;i<=100;i++)
#5 clk=~clk;
$finish;
end
endmodule

23 | P a g e
24 | P a g e
Q14) Write a program in verilog to show JK Flip-flop using case
statement. Verify logic using truth table and timing diagram.

Sol: -
module flipflop(jk,clk,q,qb);
input [1:0] jk;
input clk;
output q,qb;
reg q,qb;
initial q=0;
always @(posedge clk)
begin
case(jk)
2'b00:q=q;
2'b01:q=0;
2'b10:q=1;
2'b11:q=~q;
endcase
qb=~q;
end
endmodule

module test;
reg [1:0]jk;
reg clk,i;
wire q,qb;
flipflop fp(jk,clk,q,qb);

initial begin
$dumpfile("abc.vcd");
$dumpvars(0,test);
$display("clk\t jk \t q \t qb");
$monitor("%b\t %b\t %b\t %b\t",clk,jk,q,qb);
jk=2'b00;
#10
jk=2'b01;
#10
jk=2'b10;
#10
jk=2'b11;
#10
$finish;
end

initial begin
clk=0;

25 | P a g e
for(i=0;i<=100;i++)
#5 clk=~clk;
$finish;

end
endmodule

26 | P a g e
27 | P a g e
Q15) Write a program in verilog to show D Flip-flop using case statement.
Verify logic using truth table and timing diagram.
Sol: -
module dflipflop(d,clk,q,qb);
input d;
input clk;
output q,qb;
reg q,qb;
initial q=0;
always @(posedge clk)
begin
assign q=d;
qb=~q;
end
endmodule

module test;
reg d;
reg clk,i;
wire q,qb;
dflipflop fp(d,clk,q,qb);

initial begin
$dumpfile("abc.vcd");
$dumpvars(0,test);
$display("CLK\t D \t Q \t~Q");
$monitor("%b\t %b\t %b\t",clk,d,q,qb);
d=0;
#10 d=1;
#10
$finish;
end

initial begin
clk=0;
for(i=0;i<=100;i++)
#5 clk=~clk;
$finish;
end
endmodule

28 | P a g e
29 | P a g e
Q16) Write a program in verilog to implement counters.

Sol:-
module counter(clk, rst, enable, count);
input clk, rst, enable;
output [3:0]count;
reg [3:0]count;
always@(posedge clk)begin

if(rst == 1)
count = 4'b0000;
else if(enable == 1)
count = count + 4'b0001;
end
endmodule

module test;
reg clk, rst, enable,i;
wire [3:0]count;
counter c(clk, rst, enable, count);

initial begin
$dumpfile("counter.vcd");
$dumpvars(0, test);
$display("Clock\tReset\tEnable\tCount");
$monitor("%b\t%b\t%b\t%b", clk, rst, enable,
count); rst=1;
#3 enable = 1;
rst = 0;
#10 enable = 0;
rst = 0;
#10 enable = 1;
rst = 0;
#100 enable = 1;
rst = 1;
#10
$finish;
end

initial begin
clk = 0;
for(i=0;i<100;i++)
#2 clk =~clk;
end
endmodule

30 | P a g e
31 | P a g e
Q17) Implement left and right shift in hexadecimal numbers.
Sol:-
module left(in,out);
input [3:0]in;
output [4:0]out;
assign out = in<<1;
endmodule

module right(in,out);
input [3:0]in;
output [4:0]out;
assign out = in>>1;
endmodule

module test;
reg [3:0]in;
wire [4:0]out;
wire [4:0]out1;
left l1(in,out);
right r1(in,out1);
initial
begin
$dumpfile("shift.vcd");
$dumpvars(0,test);
$display("Decimal\tleft_shift\tright_shift");
$monitor("%h \t %b \t\t %b",in,out,out1);
in = 4'b0000;
#10
in = 4'b0001;
#10
in = 4'b0010;
#10
in = 4'b0011;
#10
in = 4'b0100;
#10
in = 4'b0101;
#10
in = 4'b0110;
#10
in = 4'b0111;
#10
in = 4'b1000;
#10
in = 4'b1001;
#10
in = 4'b1010;
#10
in = 4'b1011;
#10

32 | P a g e
 in = 4'b1100;
#10
in = 4'b1101;
#10
in = 4'b1110;
#10
in = 4'b1111;
#10
$finish;
end
endmodule

33 | P a g e
Q18) Write a program in verilog to implement seven segment display.
Sol:-
module segment(input [3:0]a, output [6:0]b);
reg [6:0]b;
always @(*)
begin
case (a)
4'b0000:b=7'b0111111;
4'b0001:b=7'b0000110;
4'b0010:b=7'b1011011;
4'b0011:b=7'b1001111;
4'b0100:b=7'b1100110;
4'b0101:b=7'b1101101;
4'b0110:b=7'b1111101;
4'b0111:b=7'b0000111;
4'b1000:b=7'b1111111;
4'b1001:b=7'b1101111;
4'b1010:b=7'b1110111;
4'b1011:b=7'b1111111;
4'b1100:b=7'b0111001;
4'b1101:b=7'b0111111;
4'b1110:b=7'b1111001;
4'b1111:b=7'b1110001;
endcase
end
endmodule

module test;
reg [3:0]a;
wire [6:0]b;
segment s(a,b);
initial begin
$dumpfile("segment.vcd");
$dumpvars(0, test);
$display("a3 a2 a1 a0\tb6 b5 b4 b3 b2 b1 b0");
$monitor("%b%b%b%b\t\t\t%b%b%b%b%b%b%b", a[3], a[2], a[1], a[0], b[6], b[5],
b[4], b[3], b[2], b[1], b[0]);
a = 4'b0000;
#10;
a = 4'b0001;
#10;
a = 4'b0010;
#10;
a = 4'b0011;
#10;
a = 4'b0100;
#10;
a = 4'b0101;
#10;
a = 4'b0110;

34 | P a g e
 #10;
a = 4'b0111;
#10;
a = 4'b1000;
#10;
a = 4'b1001;
#10;
a = 4'b1010;
#10;
a = 4'b1011;
#10;
a = 4'b1100;
#10;
a = 4'b1101;
#10;
a = 4'b1110;
#10;
a = 4'b1111;
#10;
$finish;
end
endmodule

35 | P a g e
Q19) Write a program in verilog to design a BCD to Excess 3 code convertor.

Sol:-
module segment(input [3:0]a, output [3:0]b);
reg [3:0]b;
always @(*)
begin
case (a)
4'b0000:b=4'b0011;
4'b0001:b=4'b0100;
4'b0010:b=4'b0101;
4'b0011:b=4'b0110;
4'b0100:b=4'b0111;
4'b0101:b=4'b1000;
4'b0110:b=4'b1001;
4'b0111:b=4'b1010;
4'b1000:b=4'b1011;
4'b1001:b=4'b1100;
4'b1010:b=4'bXXXX;
4'b1011:b=4'bXXXX;
4'b1100:b=4'bXXXX;
4'b1101:b=4'bXXXX;
4'b1110:b=4'bXXXX;
4'b1111:b=4'bXXXX;
endcase
end
endmodule

module test;
reg [3:0]a;
wire [3:0]b;
segment s(a,b);
initial begin
$dumpfile("excess.vcd");
$dumpvars(0, test);
$display("BCD\tExcess3");
$monitor("%h\t%h", a,b);
a = 4'b0000;
#10;
a = 4'b0001;
#10;
a = 4'b0010;
#10;
a = 4'b0011;
#10;
a = 4'b0100;
#10;
a = 4'b0101;
#10;
a = 4'b0110;
#10;

36 | P a g e
 a = 4'b0111;
#10;
a = 4'b1000;
#10;
a = 4'b1001;
#10;
a = 4'b1010;
#10;
a = 4'b1011;
#10;
a = 4'b1100;
#10;
a = 4'b1101;
#10;
a = 4'b1110;
#10;
a = 4'b1111;
#10;
$finish;
end
endmodule

37 | P a g e
 Project : CAR PARKING SYSTEM

In the entrance of the parking system, there is a sensor which is activated

to detect a vehicle coming. Once the sensor is triggered, a password is
requested to open the gate. If the entered password is correct, the gate
would open to let the vehicle get in. Otherwise, the gate is still locked. If
the current car is getting in the car park being detected by the exit sensor
and another the car comes, the door will be locked and requires the
coming car to enter passwords.

38 | P a g e
`timescale 1ns / 1ps
module parking_system(
input clk,reset_n,
input sensor_entrance, sensor_exit,
input [1:0] password_1, password_2,
output wire GREEN_LED,RED_LED,
output reg [6:0] HEX_1, HEX_2
);
parameter IDLE = 3'b000, WAIT_PASSWORD = 3'b001, WRONG_PASS = 3'b010,
RIGHT_PASS = 3'b011,STOP = 3'b100;
// Moore FSM : output just depends on the current state
reg[2:0] current_state, next_state;
reg[31:0] counter_wait;
reg red_tmp,green_tmp;
// Next state
always @(posedge clk or negedge reset_n)
begin
if(~reset_n)
current_state = IDLE;
else
current_state = next_state;
end
// counter_wait
always @(posedge clk or negedge reset_n)
begin
if(~reset_n)
counter_wait <= 0;
else if(current_state==WAIT_PASSWORD)
counter_wait <= counter_wait + 1;
else
counter_wait <= 0;
end
//change state
always @(*)
begin
case(current_state)
IDLE: begin

39 | P a g e
 if(sensor_entrance == 1)
next_state = WAIT_PASSWORD;
else
next_state = IDLE;
end
WAIT_PASSWORD: begin
if(counter_wait <= 3)
next_state = WAIT_PASSWORD;
else
begin
if((password_1==2'b01)&&(password_2==2'b10))
next_state = RIGHT_PASS;
else
next_state = WRONG_PASS;
end
end
WRONG_PASS: begin
if((password_1==2'b01)&&(password_2==2'b10))
next_state = RIGHT_PASS;
else
next_state = WRONG_PASS;
end
RIGHT_PASS: begin
if(sensor_entrance==1 && sensor_exit == 1)
next_state = STOP;
else if(sensor_exit == 1)
next_state = IDLE;
else
next_state = RIGHT_PASS;
end
STOP: begin
if((password_1==2'b01)&&(password_2==2'b10))
next_state = RIGHT_PASS;
else
next_state = STOP;
end
default: next_state = IDLE;

40 | P a g e
 endcase
end
// LEDs and output, change the period of blinking LEDs here
always @(posedge clk) begin
case(current_state)
IDLE: begin
green_tmp = 1'b0;
red_tmp = 1'b0;
HEX_1 = 7'b1111111; // off
HEX_2 = 7'b1111111; // off
end
WAIT_PASSWORD: begin
green_tmp = 1'b0;
red_tmp = 1'b1;
HEX_1 = 7'b000_0110; // E
HEX_2 = 7'b010_1011; // n
end
WRONG_PASS: begin
green_tmp = 1'b0;
red_tmp = ~red_tmp;
HEX_1 = 7'b000_0110; // E
HEX_2 = 7'b000_0110; // E
end
RIGHT_PASS: begin
green_tmp = ~green_tmp;
red_tmp = 1'b0;
HEX_1 = 7'b000_0010; // 6
HEX_2 = 7'b100_0000; // 0
end
STOP: begin
green_tmp = 1'b0;
red_tmp = ~red_tmp;
HEX_1 = 7'b001_0010; // 5
HEX_2 = 7'b000_1100; // P
end
endcase
end

41 | P a g e
 assign RED_LED = red_tmp ;
assign GREEN_LED = green_tmp;

endmodule

Testbench Verilog code for car parking system:

`timescale 1ns / 1ps
module tb_parking_system;

// Inputs
reg clk;
reg reset_n;
reg sensor_entrance;
reg sensor_exit;
reg [1:0] password_1;
reg [1:0] password_2;

// Outputs
wire GREEN_LED;
wire RED_LED;
wire [6:0] HEX_1;
wire [6:0] HEX_2;
parking_system uut (
.clk(clk),
.reset_n(reset_n),
.sensor_entrance(sensor_entrance),
.sensor_exit(sensor_exit),
.password_1(password_1),
.password_2(password_2),
.GREEN_LED(GREEN_LED),
.RED_LED(RED_LED),
.HEX_1(HEX_1),
.HEX_2(HEX_2)
);
initial begin

42 | P a g e
 clk = 0;
forever #10 clk = ~clk;
end
initial begin
// Initialize Inputs
reset_n = 0;
sensor_entrance = 0;
sensor_exit = 0;
password_1 = 0;
password_2 = 0;
// Wait 100 ns for global reset to finish
#100;
reset_n = 1;
#20;
sensor_entrance = 1;
#1000;
sensor_entrance = 0;
password_1 = 1;
password_2 = 2;
#2000;
sensor_exit =1;
end

endmodule

Simulation waveform for the car parking system

43 | P a g e