2016 3rd International Conference on Signal Processing and Integrated Networks (SPIN)

Design of Fast FIR Filter Using Compressor and

Carry Select Adder
Deepak Kumar Patel Raksha Chouksey Dr. Minal Saxena
Department of ECE Department of ECE Department of ECE
SIRT TITR SIRT
BHOPAL, INDIA BHOPAL, INDIA BHOPAL, INDIA

ABSTRACT: - Speed and area are now a day’s one of the paper is to design a FIR filter [4], so for efficient and fast
fundamental design issues in digital era. To increase speed, while design here we used compressor technique for improved
doing the multiplication or addition operations, has always been multiplication and proposed adder structure for fast addition.
a basic requirement of designing of advanced system and For Delay purpose D flip-flop is used.
application. Carry Select Adder (CSA) is a fastest adder used in
many processors to accomplish fast arithmetic function. Many
Section II explains structure of Binary to Excess-1 converter.
different adder architecture designs have been developed to Section III and IV presents the function of conventional CSA
increase the efficiency of the adder. It is very commonly known and proposed modified CSA respectively. Section V describes
that per second any processors performed millions of work the URDHWA multiplier compressor (UMC) for high speed
functions in semiconductor industry. So when we do designing of multiplication. Section VI deals with the novel technique of
multipliers, one of the main standards is performing speed that combining UMC and CSA for designing of filter. Simulation
should be taken in the mind. In this paper, we propose a results and conclusion are analyzed in Section VII and VIII.
technique for designing of FIR filter using multiplier based on
compressor and carry select adder. Performance of all adder
designs is implemented for 16, 32 and 64 bit circuits. These II. EXCESS-1 CONVERTER IN BINARY
structures are synthesized on Xilinx device family. FORMAT (BEC)

Keywords: - Ripple Carry Adder (RCA), Carry Select Adder

(CSA), Excess-1 converter, Compressor, FIR Filter.
Excess-1 converter in binary format is used in Carry Select
Adder for reduction of requirement of area and power. Excess
to 1 converter (BEC) is a circuit that produces output for
I. INTRODUCTION binary numbers by incremented value 1.The Mathematical
expressions of the 4-bit BEC is as
Area of Digital Signal Processing (DSP) is of extreme X0 = NOT (B0) (1)
importance as it performs the processing of digital signal. A X1= B1 ⊕ B0 (2)
complex DSP system involves several adders and multipliers
[1]. An efficient design of adders and multipliers improves the X2 = B2 ⊕ (B0 AND B1) (3)
performance of complex signal processing system. One of the X3 = B3 ⊕ (B0 AND B1 AND B2) (4)
fundamental components is adders which are very frequently Basic structure in figure 1 shown is for 4-bit Excess to 1
found in the many different networks that are in different converter.
blocks of many systems like controllers and processing chips.
A system’s performance is basically estimated by the ability of
the working of adder and multiplier [8].
In digital adders, addition speed is restricted by the
requirement of necessary time for a carry to propagate through
the adder. The sum for each bit position in conventional ripple
adder is created in sequence manner after the previous bit
position has been added and carry transferred into the next
position [2]. By making the required necessary time to smaller
Figure 1: 4-bit Binary to Excess-1 converter (BEC) [1].
to determine carry bits, there is a chance of enhancing the
speed in adders, it makes possible by Carry Select adder. CSA
is used to eliminate the problem of carry propagation delay by III. 16-BIT CONVENTIONAL CARRY
separately producing multiple carries and then carry is selected
SELECT ADDER
to generate the final sum. However, CSA consumes more area
because it uses many pairs of ripple carry adders(RCA) to 16 bit conventional carry select adder is explained with the
produce the partial sum and carry by considering Cin = ‘0’ and help of detailed block diagram which is shown in figure 2. We
Cin =‘1’ respectively, then the final sum and carry are selected have separated our structure in different sizes like 2bit, 3 bit, 4
by the use of multiplexers [3]. The basic approach used in this
bit and into 5 bit blocks of Ripple Carry Adder.

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 2016 3rd International Conference on Signal Processing and Integrated Networks (SPIN)

X[15:11] Y[15:11] X[10:7] Y[10:7] X[6:4] Y[6:4] X[3:2] Y[3:2] X[1:0] Y[1:0]

15:11 RCA 0 10:7 RCA 0 6:4 RCA 0 3:2 RCA 0 1:0 RCA

15:11 RCA 1 10:7 RCA

1 6:4 RCA 1 3:2 RCA 1

CY MUX C3 CY MUX C2 CY MUX C1 CY MUX

Cout
5 4 3 2

Sum [15:11] Sum [10:7] Sum [6:4] Sum [3:2] Sum [1:0]

Figure 2: 16-Bit Carry Select Adder using Ripple Carry Adder [2]

The RCA is simplest adder but their working performance is Basic architecture of conventional adders clears that clearly
restricted due to the method of carry generation [5]. In this there is a chance that we can minimize the requirement of area
method carry is rippled from least bit to significant bit. From and power consumption of the conventional CSA. For this
the figure it is clear that the first block i.e. group 1 is purpose here used Binary to Excess-1 Converter that
combination of only single RCA block which has order of 2 effectively replaces the ripple carry adder with carry input
bit. Cin=1 and for improving the working operations we have not
This block has simply two inputs in form of X & Y and it will used multiplexer.
give sum and out carry. Out carry of first block will be used in We can clearly understand that from the block diagram of
the next block. Combination of two RCA blocks is used from proposed structure which is of the order of 16- bit is divided
the upcoming group. All these groups also have different bit into five blocks of RCA and BEC with different order of bit
size order. The concept is that if the carry-in is 0, the output of size. The first group in this structure i.e. group 1 contains
the upper RCA is chosen and if the input carry is 1, the output only single RCA block of 2- bit size, which gives there
of the lower RCA is chosen [7]. Finally the whole circuit gives output sum and carry out.
us summation of two numbers.
One is RCA block and another is BEC block is used from the
next coming groups that means it consist combination of 2
IV. 16-B PROPOSED CARRY SELECT ADDER blocks. In the designed circuit therefore there are two outputs
USING BEC AND WITHOUT one comes from the RCA block and other output from the
MULTIPLEXER BEC.

A[15:11] B[15:11] A[10:7] B[10:7] A[6:4] B[6:4] A[3:2] B[3:2] A[1:0] B[1:0]

5-bit RCA 0 4-bit RCA 0 3-bit RCA 0 2-bit RCA 0 2-bit RCA

5-bit BEC 1 4-bit BEC 1 3-bit BEC 1 2-bit BEC 1

CY Without C3 CY Without C2 CY Without C1 CY Without

MUX MUX MUX MUX

Cout
5 4 3 2

Sum [15:11] Sum [10:7] Sum [6:4] Sum [3:2] Sum [1:0]

Figure 3: Proposed Modified 16-Bit Carry Select Adder using BEC

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Sout and Cout is chosen from the upper RCA block if Cin=0
and if Cin=1 then the output is chosen from BEC block. Final Y1 Y2 Y3 Y4
output is selected without the help of multiplexer. Using this
concept and with the help of Xilinx calling function command
we can design higher order bit like 32-bit and 64-bit adder.
EX-OR EX-OR
Cin
V. URDHWA MULTIPLIER COMPRESSOR

MUX EX-OR
Multiplication in most of the signal processing algorithms is a
very basic operation. Multipliers generally occupy large area,
latency is long and consumes considerable amount of power.
Therefore designing of low power multiplier has been an EX-OR MUX
essential part in any system design.
In this paper we used modified compressor technique to boost
up the speed of operation. So for the purpose of speed Cout Carry Sum
multiplication we use innovative technique known as
URDHWA multiplier compressor (UMC). Here in this paper
Figure 6: Modified Design of 4:2 Compressors
we used modified 4:2 compressor and 7:2 compressor for
addition purpose in multiplication [9].
The another way on figure 5 is implementation of 4:2
A1 A2 A3 A4 compressor shown in figure 4. Figure 5 is nothing but the
basic design of 4:2 compressor which we can design with the
help of full adder. From the structure of figure 5 it is clear that
we can again design it with the help of other suitable
architecture that can enhance the speed of operation. So Figure
Cout 4:2 Cin 6 represent our proposed modified design structure for 4:2
compressor using multiplexer and EX-OR gate.

These are the following output equation for 4:2 compressor :

Carry Sum
ܵ‫ ݉ݑ‬ൌ ܺଵ ۩ܺଶ ۩ܺଷ ۩ܺସ ۩‫ܥ‬௜௡
Figure 4: Block Diagram of 4:2 Compressors [9]
തതതതതതതതതതത
‫ܥ‬௢௨௧ ൌ ሺܺଵ ْ ܺଶ ሻǤ ܺଷ ൅ ൫ܺ ଵ ْ ܺଶ ൯ ή ܺଵ
To understand the working of 4:2 compressor, we made the ‫ ݕݎݎܽܥ‬ൌ ሺܺଵ ۩ܺଶ ۩ܺଷ ۩ܺସ ሻ ή ‫ܥ‬௜௡
basic architecture in figure 4. If we have to add four input &
one carry input bit, then we can done this operation with the തതതതതതതതതതതതതതതതതതതതത
൅ ሺܺ ଵ ۩ܺଶ ۩ܺଷ ۩ܺସ ሻ ή ܺସ
help of 4:2 compressors and gives three outputs.

A1 A2 A3 A4 As we designed 4:2 compressor in the same way figure 7

shows the 7:2 compressor design, which is capable of adding 7
bits of input and 2 carry output from the previous stages, at a
time.
FA X1 X2 X3 X4 X5 X6 X7
Cin

Cout Cout1 Cin1

FA Cout2 7:2 Cin2

Carry Sum Carry Sum

Figure 5: Design of 4:2 Compressors Figure 7: Block diagram of 7:2 Compressors [9]

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 2016 3rd International Conference on Signal Processing and Integrated Networks (SPIN)

In our implementation, we have designed 7: 2 compressor with The FIR, in signal processing, is a filter whose impulse
the help of utilizing two 4:2 compressors. The architecture has response is of finite duration. Since FIR filter settles to zero in
been shown in Figure 8. finite time, it is known as finite impulse response filter [6].
Designs of FIR Filter consist of Delay component, Multiplier
and adder. If we use this architecture, entire area as well as
4:2 4:2 delay will be more. Large number of adder, multiplier and D
Compressors Compressors flip-flop are needed. Thus the entire network is replaced as
C22 C21 S2 C1 C2 S1 shown in figure 9.

So we have used here our proposed modified structure of carry

select adder in place of conventional adder to enhance the
performance of system. In figure 9, the multiplier block have
H. A. replaced by URDHWA multiplier using compressors. Here in
this paper to understand the designing 8 tap FIR filter is used.
8 tap means 8 delay unit in circuit design.
F. A. S3

C3 VII. SIMULATION RESULT

All the developed designs in this paper used tools of Xilinx

F. A. 14.3i software and family of Spartan 6, Virtex 6 and Virtex 7
updated version.
To make the smart systems and develop new technology
Xilinx 14.3i software provide us very good platform. It has
Cout2 Cout1 Carry1 Sum1 available very advanced tools and also have improved version
of properties which makes appropriate advancement in the
Figure 8: Modified Design of 7:2 Compressors
system now.
These are the following output equation for 7:2 compressor : The latest development of Integrated Software Environment
design tool makes available the requirements of low memory.
Sum1 = S1 ⊕ S 2 ISE 14.3i Xilinx tools are also suitable for designing of
Carry1 = S 3 ⊕ C1 ⊕ C 21 embedded system processors. By the help of this software we
can easily find and remove the error in the program. With the
C out1 = C3 ⊕ C 2 ⊕ C 22 help of tools provided we can create designs in the field of
C out 2 = C 3C 2 + C 22 C 2 + C3 C 22 communication also in the field of signal processing and
designing of low power VLSI system.
The 7:2 compressor architecture would improve the efficiency
as compared to adding nine bits in a conventional approach
Table 1 shows the comparison of adders in different device
that is using full adders and half adders only. This causes to a
family and found that the result of our proposed CSA is better
great enhancement in speed of the processor.
than conventional CSA.

VI. PROPOSED FIR FILTER

The block diagram of our proposed FIR filter is shown in

figure 9.
X (n-7)
X (n) X (n-1) X (n-2) X (n-3)
Delay Delay Delay Delay …… Delay

h0 h1 h2 h3 h7
UMC UMC UMC UMC UMC

Yn
A* A* A* A*

Figure 9: Block Diagram of FIR Filter using UMC and A*

UMC: Urdhwa Multiplier using Compressor
A*: 16-bit CSA using proposed modified CSA

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Table 1: Comparison Table of Adders for Different Device Figure 12 shows the comparison of delay for the Carry Select
Families Adder in spartan 6, Virtex 6 and Virtex 7 device family for 64-
bit.
Adder Delay(ns) Delay(ns) Delay(ns)
Word
Spartan 6 Vertex 6 Vertex 7
size 40
Conventional 13.292 5.610 4.478
(Dual RCA) 30
Spartan 6
16-B Proposed 11.257 3.933 3.144
CSA
(With BEC) 20 Vertex 6
Conventional 20.733 9.387 7.474 10 Vertex 7
(Dual RCA)
32-B Proposed 17.130 6.948 5.537 0
CSA
(With BEC) Conventional CSA Proposed CSA
Conventional 36.599 17.820 14.205 Figure 12: comparison of Adder for Delay (Word Size =64)
(Dual RCA)

64-B Proposed 28.876 12.977 10.324 Table 2: Comparison Table of Filter for Spartan 6 Device
CSA
(With BEC) Family

Filter Design Delay Frequency

The comparison graph of RCA i.e. conventional carry select (ns) (MHZ)
adder and proposed modified (CSA) carry select adder in
terms of delays for word size 16 is shown in figure 10. Spartan
6
14 FIR filter using UMC and 170.612 5.861
12
CSA using Dual RCA
10
8 Spartan 6 Proposed FIR filter using 108.652 9.259
6 Vertex 6 UMC and CSA with BEC
4 Vertex 7
2 Table 2 shows the comparison of FIR filter for Spartan 6
0 family in terms of delay and frequency.
Conventional CSA Proposed CSA
Table 3: Comparison Table of Filter for Vertex 6 Device
Figure 10: comparison of Adder for Delay (Word Size =16) Family

Figure 11 shown is the comparison graph for word size 32 for Filter Design Delay Frequency
conventional CSA and proposed CSA.
(ns) (MHZ)
25 Virtex 6
20 FIR filter using UMC 96.843 10.325
15 Spartan 6 and CSA using Dual
10 Vertex 6
RCA
5 Vertex 7
Proposed FIR filter 54.489 18.352
0
using UMC and CSA
Conventional CSA Proposed CSA
with BEC
Figure 11: comparison of Adder for Delay (Word Size =32)

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Table 3 and Table 4 represent the comparison of filter for Select Adder. In this paper we introduce unique compressor
Vertex 6 and Vertex 7 respectively family in terms of delay technique i.e. URDHWA multiplier compressor. By using this
and frequency and proposed design is better than conventional multiplier and modified CSA, a FIR filter is implemented and
design. our proposed FIR filter improves the performance of system.
All the results are synthesized using Xilinx 14.3i software.
The conventional CSA has a disadvantage of consuming larger
Table 4: Comparison Table of Filter for Vertex 7 Device area and delay. The modified CSA with BEC reduces the
Family delay, when compare to conventional CSA. On the device
family of Spartan 6, 16 bit proposed CSA and proposed design
Filter Design Delay Frequency structure of FIR filter with BEC provides approximately
15.30% and 36.31% higher speed than the conventional design
(ns) (MHZ) structure respectively. It would be challenging to test this
pattern design for higher order bit and for higher order filter.
Virtex 7
FIR filter using UMC 86.093 11.615
REFERENCES
and CSA using Dual
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Efficient Carry Select Adder”, IEEE Transsactions on Very
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[2] Ms. S.Manju, Mr. V. Sornagopal “An Efficient SQRT
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[3] Sajesh Kumar U., Mohamed Salih K. K. Sajith K.,“Design and
Figure 13 shows the comparison graph of FIR filter for Implementation of Carry Select Adder without Using
Spartan 6, Vertex 6 and Vertex 7 device families and our Multiplexers”, 2012 1st International Conference on Emerging
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[4] Pramod Kumar Mehar et al.“ Distributed Arithmetic for FIR
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VIII. CONCLUSION

We have suggested and implemented a technique which

effectively minimizes the delay and increase the speed of
operation in great extent. Proposed modified Adder is a simple
technique used in this paper to decrease the delay of Carry

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