Introduction to VLSI

Unit I
 Why VLSI?
• Integration improves the design
– Lower parasitics = higher speed
– Lower power consumption
– Physically smaller
• Integration reduces manufacturing
cost - (almost) no manual assembly
 VLSI Applications
• VLSI is an implementation technology for electronic circuitry
- analogue or digital
• It is concerned with forming a pattern of interconnected
switches and gates on the surface of a crystal of
semiconductor
• Microprocessors
– personal computers
– microcontrollers
• Memory - DRAM / SRAM
• Special Purpose Processors - ASICS (CD players, DSP
applications)
• Optical Switches
• Has made highly sophisticated control systems mass-
producable and therefore cheap
 Integrated circuits
• Levels of Integration:-
• i) Small Scale Integration:- (10-100) transistors =>
Example: Logic gates
• ii) Medium Scale Integration:- (100-1000) =>
Example: counters
• iii) Large Scale Integration:- (1000-10000) =>
Example:8-bit chip
• iv) Very Large Scale Integration:- (10-100 million
devices per chip) => Example:16 & 32 bit up
• v) Ultra Large Scale Integration:- (more than100
millon) => Example: Special processors, virtual
reality machines, smart sensors
 Basic MOS Transistors:

MOS
We should first understand the fact that why the name Metal Oxide
Semiconductor
transistor, because the structure consists of a layer of Metal (gat
e), a layer of oxide (Sio2) and a layer of semiconductor
Metal-oxide-semiconductor (MOS)
and related VLSI technology
• pMOS
• nMOS
• CMOS
• BiCMOS
• GaAs
Different types of transistors
 types of FETs
• In Enhancement mode transistor channel is
going to form after giving a proper positive
gate voltage.
• We have NMOS and PMOS enhancement
transistors.
• In Depletion mode transistor channel will be
present by the implant. It can be removed
by giving a proper negative gate voltage.
• We have NMOS and PMOS depletion mode
transistors
N-MOS enhancement mode
transistor
 N-MOS enhancement mode
transistor
N-MOS enhancement mode
transistor:-
• This transistor is normally off. This
can be made ON by giving a positive
gate voltage.
• By giving a +ve gate voltage a
channel of electrons is formed
between source drain.
P-MOS enhancement mode
transistor
Enhancement mode Transistor
action:-

Since Vgs > Vt and Vds = 0 the channel is formed but no current
flows between drain and source.
This region is called the non-saturation Region or linear region
where the drain current increases linearly with Vds. When Vds is
increased the drain side becomes more reverse biased (hence
more depletion region towards the drain end) and the channel
starts to pinch. This is called as the pinch off point
This region is called Saturation Region where the drain current
remains almost constant. As the drain voltage is increased further
beyond (Vgs-Vt) the pinch off point starts to move from the drain
end to the source end. Even if the Vds is increased more and
more, the increased voltage gets dropped in the depletion region
leading to a constant current. The typical threshold voltage for an
enhancement mode transistor is given by Vt = 0.2 * Vdd.
N-MOS depletion mode transistor
This transistor is normally ON, even with Vgs=0.
The channel will be implanted while fabricating,
hence it is normally ON. To cause the channel to
cease to exist, a – ve voltage must be applied
between gate and source.

NOTE: Mobility of electrons is 2.5 to 3 times faster

than holes. Hence P-MOS devices will have more
resistance compared to NMOS.
NMOS fabrication
Step1:
Processing is carried on single crystal silicon of high
purity on which required P impurities are introduced
as crystal is grown. Such wafers are about 75 to 150
mm in diameter and 0.4 mm thick and they are
doped with say boron to impurity concentration of
10 to power 15/cm3 to 10 to the power 16/cm3.
Step 2 :
A layer of silicon di oxide (SiO2) typically 1 micrometer
thick is grown all over the surface of the wafer to protect
the surface, acts as a barrier to the dopant during
processing, and provides a generally insulating substrate
on to which other layers may be deposited and patterned .
Step 3:
The surface is now covered with the photo
resist which is deposited onto the wafer and spun
to an even distribution of the required thickness.
Step 4:
The photo resist layer is then exposed to ultraviolet
light through masking which  defines those regions
into which diffusion is to take place together with
transistor channels. Assume, for example , that
those areas exposed to uv radiations are
polymerized (hardened), but that the areas
required for diffusion are shielded by the mask and
remain unaffected.
Step 5:
These areas are subsequently readily etched away
together with the underlying silicon di oxide so
that the wafer surface is exposed in the window
defined by the mask.
Step 6:
The remaining photo resist is removed and a thin layer
of SiO2 (0.1 micro m typical) is grown over the entire
chip surface and then poly silicon is deposited on the
top of this to form the gate structure. The polysilicon
layer consists of heavily doped polysilicon deposited by
chemical vapour deposition (CVD). In the fabrication of
fine pattern devices, precise control of thickness,
impurity concentration, and resistivity is necessary.
Step 7:
Further photo resist coating and masking allows
the poly silicon to be patterned and then the thin
oxide is removed to expose areas into which n-type
impurities are to be diffused to form the source
and drain. Diffusion is achieved by heating the
wafer to a high temperature and passing a gas
containing the desired n-type impurity.
Note: The poly silicon with underlying thin oxide
and the thick oxide acts as mask during diffusion
the process is self aligning.
Step 8:
Thick oxide  (SiO2) is grown over all again
and is then masked with photo resist and
etched to expose selected areas of the poly
silicon gate and the drain and source areas
where connections are to be made.
(contacts cut)
Step 9:
The whole chip then has metal (aluminum)
deposited over its surface to a thickness
typically of 1 micro m. This metal layer is
then masked and etched to form the
required interconnection pattern.
 PMOS FABRICATION
• PMOS fabrication steps are similar to
the fabrication steps of NMOS with a
small changes like p-substrate is
replaced by n-substrate and n-
diffusions are replaced by p-
diffusions in NMOS fabrication
process.
 CMOS FABRICATION
• CMOS FABRICATION is done by using
following processing techniques:
• n –WELL PROCESS
• p-well process
• twin tub
 P-well process
• The p-well process starts with a n type
substrate. The n type substrate can be used to
implement the pMOS transistor, but to
implement the nMOS transistor we need to
provide a p- well, hence we have provided the
place for both n and pMOS transistor on the
same n-type substrate.
• This diffusion must be carried out with special
care since the p-well doping concentration and
depth will effect the threshold voltages as well
as breakdown voltages of the n-transistors.
p-well process

Mask 1:
Mask 1 defines the areas in
which the deep p-well
diffusion takes place.

Mask 2: It defines the thin

oxide region (where the
thick oxide is to be removed
or stripped and thin oxide
grown)
Mask 3: It‘s used to pattern
the polysilicon layer which is
deposited after thin oxide.
Mask 4: A p+ mask (anded
with mask 2) to define areas
where p-diffusion is to take
place.
Mask 5: We are using the –
ve form of mask 4 (p+
mask) It defines where n-
diffusion is to take place.
 The cross section below shows the
CMOS pwell inverter
• Mask 6: Contact cuts are defined using this mask.
• Mask 7: The metal layer pattern is defined by this
mask.
• Mask 8: An overall passivation (over glass) is now
applied and it also defines openings for accessing
pads.
 n –WELL PROCESS

Step 1: Si Substrate
Start with p-type substrate
Step 2: Oxidation
Exposing to high-purity oxygen and
hydrogen at approx. 10000C in oxidation
furnace
Step 3: Photoresist Coating
Photoresist is a light-sensitive organic
polymer
Softens when exposed to light
 Step 8: Formation of n-well
n-well is formed with diffusion or ion
implantation

Step 9: Removal of SiO2

Strip off the remaining oxide using
HF
Cont..
Step 12: P-diffusion
Similar set of steps form p+ diffusion regions for
pMOS source and drain and substrate contact

Step 13: Contact cuts

The devices are to be wired together Cover chip with thick field oxide
Etch oxide where contact cuts are needed
 Berkeley n-well process

• There are a number of p-well and n-

well fabrication processed and , in
order to look more closely at typical
fabrication steps, we will use the
Berkeley n-well process an example.
This process is illustrated as follows:
 CMOS twin-tub inverter.
Here we will be using both p-well and n-well approach. The
starting point is a n-type material and then we create both
n-well and p-well region. To create the both well we first go
for the epitaxial process and then we will create both wells
on the same substrate.
 Bicmos

The driving capability of MOS transistors is less because of

limited current sourcing and sinking capabilities of the
transistors. To drive large capacitive loads we can think of Bi-
Cmos technology. This technology combines Bipolar and CMOS
transistors in a single integrated circuit, by retaining benefits of
bipolar and CMOS, BiCMOS is able to achieve VLSI circuits with
speed-power-density performance previously unattainable with
either technology individually.
Bicmos
CMOS vs BiCMOS
cost versus delay graph
 PHOTO LITHOGRAPHY
• The ability to create patterned
material layers to steer(To guide
by means of a device) electrical
signals on the chip is accomplished
using a technique called photo
lithography.
• The resolution of the photo
lithography process determines the
min. feature size i.e The smallest
dimension that can actually  be
The sequence used to create the
pattern
1. Design the pattern on a computer.
2. Create the mask.
3. Print the pattern on to the surface of
the chip.
4. Use the printed region to define the
material pattern.
 The structure of reticle or
mask
• It consists of a high quality piece of glass
with a chromium metal replica of the
pattern on one side.
• The dimension of replicas are larger than
the final value which are transferred to the
chip.
• Reticle should be optically transparent.
• Cr metal regions are non transparent where
the reticle is opaque and any incident light
is reflected by the metal.
 PHOTO RESIST
• Transfer the reticle pattern to the surface of an IC
takes place in the exposure sequence.
• This process starts by coating the surface of the
chip with a light sensitive organic polymer When
illuminated by the UV regions of photoresist absorbs
the light energy which makes the chemical change.
• If the regions are shielded then they are not
affected.
• Develop the photo resist in the special solution
according to that some regions are hardened and
some regions are soft and can be washed.
 TYPES OF PHOTORESIST

• Positive resist-The illuminated

regions are soluble after exposure to
light and unexposed regions develop
in to hardened material.
• Negative resist-The illuminated
regions are hardened after exposure
to light and unexposed regions are
soluble.
Cont..
 SEQUENCE

•Starting point is substrate with oxide coating and metal layer on

the top.
•Transfer a pattern to the metal layer.
•Photo resist is applied by spin coating the surface of the chip with
liquid solution and baking it for few minutes to dehydrate the
layer.
•This leaves the Photoresist coating.
•The reticle is placed between the a UV light source and the chip
so that it casts a shadow onto the surface of the photo resist.
•Optical imaging components are used to sharpen the edges of
the shadow and this is called EXPOSURE STEP.
•After few seconds the process which will complete and the resist
is exposed, developed and rinsed in solvent.
•This leaves the hardened layer of photo resist that has same
pattern as a original screen image.
Photo-Lithographic Process
• Hardned photoresist itself is used as
a masking layer in the final step.
• It acts as an efficient barrier to
chemical or gaseous agents and that
can be used to etch away the metal
regions.
• The process is known as ETCHING
PROCESS.
REACTIVE ION ETCHING
 Cont..
• In which ionized inert gas which are mixed
with etch assisting chemicals and the
mixture is then excited with RF electric
field in a manner that drives the ions or
chemicals in a vertical up-down motion to
etch the surface.
• Unprotected metal surface is removed but
the metal underneath will be protected by
the resist.
• Removing photo resist give the final result.
 PRINTING PROCESS

• Depending upon the diameter of wafer the area

and shape of the die is decided.
• Larger the diameter of wafer more number of ICs
will manufacture.
• When a reticle is used to pattern a layer each die
site is treated separately.
• The optical printing system remains stationary.
• A pattern is printed on each die site by moving the
wafer with highly accurate displacement motors.
• This is called STEP AND REPEAT PROCESS and the
equipment is STEPPER.
                                                                            si
wafer with individual die sites
• MINIMUM FEATURE SIZE:- The
smallest dimension that can
actually  be transferred to a chip.
• SUB MICRON REGION:-modern
processing facilities can
manufacture chip with minimum
feature size less than 1 micron.
• DEEP SUB MICRON REGION:-
manufacturing chip with minimum
feature size less than 0.1 micron.
 Cascading NMOS Inverters

termine pull – up to pull-down ratio for driven inverter

When cascading logic devices care must be taken to

preserve integrity of logic levels

i.e. design circuit so that Vin = Vout = Vinv

 Assume equal margins around inverter; Vinv = 0.5 Vdd
Assume both transistors in saturation, therefore:
Ids = K (W/L) (Vgs – Vt)2/2
Depletion mode transistor has gate connected to source, i.e. V gs = 0

Ids = K (Wpu/Lpu) (-Vtd)2/2

Enhancement mode device Vgs = Vinv, therefore
Ids = K (Wpd/Lpd) (Vinv – Vt)2/2
Assume currents are equal through both channels (no current drawn by load)

(Wpd/Lpd) (Vinv – Vt)2 = (Wpu/Lpu) (-Vtd)2

Convention Z = L/W

Vinv = Vt – Vtd / (Zpu/Zpd)1/2

Substitute in typical values Vt = 0.2 Vdd ; Vtd = -0.6 Vdd ; Vinv = 0.5 Vdd

gives Zpu / Zpd = 4:1 for an nmos inverter directly driven by another inv
 Pull-Up to Pull-Down Ratio for an nMOS inverter driven
through 1 or more pass transistors

Inverter 1 Vdd Vdd Inverter 2

A B C

Vin1 Vout2

It is often the case that two inverters are connected via a

series of switches (Pass Transistors) We are concerned
that connection of transistors in series will degrade the
logic levels into Inverter 2. The driven inverter can be
designed to deal with this. (Zpu/Zpd >= 8/1)
 Various pull ups
1.Load resistance RL
2.NMOS Depletion Mode Transistor Pull
- Up
3.NMOS Enhancement Mode Transistor
Pull - Up
4.Complementary transistor pull ups
•Inverter : basic requirement for
producing a complete range of
Logic circuits
R

1 0 Vo

0 1

Vss
 Vdd
1.Basic Inverter: Transistor with source
connected to ground and a load resistor
R Pull-Up connected from the drain to the positiv
Supply rail
Output is taken from the drain and contr
input connected between gate and grou
Vo
Resistors are not easily formed in silicon
Vin - they occupy too much area
Pull Down

Transistors can be used as the pull-up de

Vss
 2.NMOS Depletion Mode Transistor Pull - Up
Vdd
Pull-Up is always on – Vgs = 0; depletion
D
• Pull-Down turns on when Vin > Vt

With no current drawn from outputs, Ids

for both transistors is equal S
Vo
V0 Vt
Vdd D
Vin

Non-zero output S
Vss

Vi
 Ids
Vgs=0.2VD
Ids D

Vgs=0

Vgs=-0.2 VDD

Vgs=-0.4
VDD
Vgs=-
0.6VDD VDD –Vds
Vds Vin

Vgs=VDD
VDD
Ids
Vgs=0.8VDD

Vgs=0.6 VDD

Vgs=0.4
V
VDD=0.2V
gs DD

Vds
VDD
Vo
VDD
 Decreasing
Vin
Zpu/Zpd
VDD

Increasing
Zpu/Zpd

Vo
VDD
Vinv

• Point where Vo = Vin is called Vinv

Transfer Characteristics and Vinv can be shifted by altering r
of pull-up to Pull down impedances
 NMOS Depletion Mode Inverter
Characteristics
• Dissipation is high since rail to rail current
flows when Vin = Logical 1
• Switching of Output from 1 to 0 begins
when Vin exceeds Vt of pull down device
• When switching the output from 1 to 0, the
pull up device is non-saturated initially and
this presents a lower resistance through
which to charge capacitors (Vds < Vgs –
Vt)
 3.NMOS Enhancement Mode Transistor Pull - Up
• Dissipation is high since current flows when Vin = 1 Vdd
D
• Vout can never reach Vdd (effect of channel)

• Vgg can be derived from a switching source (i.e. one phase

of a clock, so that dissipation can be significantly reduced
Vgg
• If Vgg is higher than Vdd, an extra supply rail is required S
V0 Vo
Vdd D
Vt (pull up)
Vin

S
Non zero output
Vss

Vt (pull down) Vin

 4.Complimentary Transistor Pull – Up (CMOS)

Vdd

Vout Vtn Vtp

P on N on
Vin N off P off
Both On
Vo

Vin
Vss Vdd

Vss
Logic 0 Logic 1
Vout Vtn Vtp

1: Logic 0 : p on ; n off
P on N on
N off P off 5: Logic 1: p off ; n on

Both On 2: Vin > Vtn.

Vdsn large – n in saturation
Vdsp small – p in resistive
Small current from Vdd to Vss
Vin
Vs 4: same as 2 except reversed p and n
s Vdd
3: Both transistors are in saturation
Large instantaneous current flows
1 2 3 4 5

0 vin
 CMOS Inverter
Characteristics
• No current flow for either logical 1 or
logical 0 inputs
• Full logical 1 and 0 levels are
presented at the output
• For devices of similar dimensions the
p – channel is slower than the n –
channel device
OS INVERTER CHARACTERISTICS

rent through n-channel pull-down transistor n

VDD  Vtp  Vtn
 p
I n  n Vin  Vtn  2 Vin 
2 n
1
ent through p-channel pull-up transistor p
If n = p and Vtp = –Vtn
p
Ip 
2
 Vin  VDD   Vtp 2
V
At logic threshold, In = Ip Vin  DD
2

 pW p  W
n 2 p  n n
2 2

Vin  Vtn    Vin  VDD   Vtp 2  Lp Ln
n p
2
Vin  Vtn  
2

 Vin  VDD   Vtp 
Mobilities are unequal : µn = 2.5 µp
n
Vin  Vtn    Vin  VDD  Vtp
p Z = L/W
  n  n

Vin 1   Vtn  VDD  Vtp
  p   p Zpu/Zpd = 2.5:1 for a symmetrical CMOS inv
