TSV-to-TSV Crosstalk Induced Delay Analysis for 3D ICs

Qifan Hu1, Qin Wang1*, Jing Chen2, Jing Xie1, Zhigang Mao1
1
Department of Microelectronics and Nanoscience, Shanghai Jiao Tong University, Shanghai, PR China
2
Shanghai Aerospace Electronics Technology Institute, Shanghai, PR China
* Email: [email protected]

Abstract This paper aims to perform estimation of crosstalk

induced delay in three-dimensional integrated circuits.
TSV (Through-silicon Via) meets the demands of high The key contributions of this work are: 1. proposing a
speed and low power consumption in 3D integrated TSV crosstalk induced delay estimation method using
circuits. However it faces challenge in signal integrity parasitic parameter and input signals with high accuracy
problem such as crosstalk. TSV to TSV coupling is the and low computational complexity; 2. giving numerical
most significant crosstalk problem in TSV based 3D ICs. expressions of circuit signal response and crosstalk
This paper presents a quantitative estimation on the TSV signal response instead of RC delay approximation, our
to TSV crosstalk induced interconnect delay, trying to method is relatively accurate and fast.
find the worst interconnect delay and increase circuit Article is organized as follows: Section 2 presents
crosstalk tolerance. We simplifies the existing TSV to equation of circuit signal voltage response and crosstalk
TSV crosstalk model with TSV parasitic parameters. voltage response, from which we calculates crosstalk
This model is validated by finite element simulation tool. induced interconnect delay. Section 3 gives simulation
Using this model, we calculate output signal voltage result and analysis. Section 4 gives the conclusion and
response and crosstalk signal voltage response. Adding prospect.
these voltage response together, time continuous output
signal voltage equation can be obtained. From this 2. Delay calculation
equation, we can easily calculate the circuit delay. The
simulation result shows that interconnect delay increases 2.1 TSV to TSV circuit simplification and verification
at most 85.73% because of TSV to TSV coupling, which Fig.1(a) presents a pair of TSVs drawn in finite
cannot be negligible in static timing analysis (STA). Our element tool HFSS. TSV parameters are listed in table 1.
simulation result is reliable since it has only 5.3%
deviation compared to Spice simulation result. And our
method is faster than Spice simulation theoretically.

1. Introduction

In three-dimensional integrated circuit (3D IC), TSV Figure 1.(a) Physical structure of a pair of TSVs and (b)
parasitic capacitance is quite larger than wire capacitance. simplified circuit of a pair of TSVs
So TSV induced interconnect delay cannot be neglected.
By employing SPEF file which consists of TSV parasitic Table 1. TSV parameters
parameters, traditional static timing analysis (STA) tool
is still able to calculate interconnect delay [1]. [2] and [3] parameter value/um parameter value/um
uses Elmore delay model to calculate interconnect delay TSV 3.2 TSV pitch 10.0
which consists TSV delay. [4] predicts interconnect diameter
delay with distribution models. Analytic model is
TSV 10.0 Oxide 0.25
proposed for crosstalk excitation and propagation in
height layer
VLSI circuit [5]. A detailed crosstalk induced delay
Pad size 6.0 Pad height 2.0
analysis of the coupled interconnects considering process
is presented in [6]. [7] considers multiple aligned RDL 2.0 Upper 0.50
aggressors coupled to a delay-sensitive victim path. height oxide
Quantitative analysis of the crosstalk voltage impact layer
on the output signal is performed in [8]. They also Substrate 9.0 Lower 0.50
propose a signal transmission noise reduction method. thickness oxide
TSVs pair and multiple TSV crosstalk modeling method layer
are given in [9] [10].

978-1-4673-9719-3/16/$31.00 ©2016 IEEE

 With the parasitic parameter extracted from the U1 D  1  DRC  RB s  RC  RA s 2

physical structure, the simplified circuit is presented as 
U s 1  sRC  D  1  DRC  2 RB s  RC  2 RA s 2  (4)
fig.1(b), which is from [8]. Rin is 50Ω terminal resistance
to eliminate reflection. Rtsv is the TSV resistance. Cox is
the capacitance of isolation layer between silicon U2 RAs 2  RBs

substrate and Cu via. Rsi and Csi are the resistance and 
U s 1  sRC  D  1  DRC  2 RB s  RC  2 RA s 2  (5)
capacitance of silicon substrate between two TSVs. Cp is
the load capacitance of both TSVs. These parasitic 1 (6)
Us 
parameter equation is given in [8]. s(t0 s  1)
To verify the simplified circuit, we compare
frequency domain response and time domain response of 2.3 Influence of input transition time and signal skew
simplified circuit and equivalent circuit which is Our method considers both the input transition time
exported from HFSS tool. and signal skew. Assume the input signal is exponential
Frequency domain response is validated up to as in (6). Input signal transition time is ln9*t0. Using the
20GHz. Fig.2(a) is the simulation result of frequency transfer function (4) and (5), voltage of output signal can
domain response. And Fig.2(b) is the time domain be calculated. Since the transfer function is in frequency
response of simplified circuit and equivalent circuit. domain, the voltage equation can be obtained as in (7) by
Both frequency domain and time domain response of using inverse Laplace transformation. Equation (8) is the
simplified circuit is similar to the one of equivalent crosstalk voltage on the victim TSV. Input signal in both
circuit. TSV nearly reach at the same time. The delay between
two signals is called signal skew. Signal skew considered
in this (8) is td. According to superposition principle,
overall signal voltage response is in (9).
U 1 t   1  b1e pt  b2 e qt  b3e mt  b4 e nt
(7)
U 2 t   a1e p t t d   a2 e q t t d   a3e m t t d   a4 e n t t d 
(8)
Figure 2.(a) Frequency domain response verification and U o t   1  b1e pt  b2 e qt  b3e mt  b4 e nt
(b) time domain response verification  a1e p t t d   a2 e q t t d   a3e m t t d   a4 e n t t d 
(9)
Assume the output voltage of the signal is 0.5vdd.
2.2 Signal voltage equation on aggressor TSV and Using the first order Taylor expansion of equation (9)
victim TSV and Newton iteration method, the approximate
The signal transfer function and crosstalk transfer interconnect delay can be derived. Since voltage
function of the simplified circuit is given in (1) in nodal superposition principle is also suitable for multiple TSVs,
analysis. U1 is output signal voltage response while U2 is this can be extended for multi-aggressors crosstalk
aggressor signal voltage response. Us is the input signal
induced delay.
voltage response. Equation (2) is total resistance R and
total capacitance C. Equation (3) is equivalent coupling 3. Simulation results
impedance between two TSVs. ‘A’, ‘B’ and ‘D’ are
symbols representing complex expressions. The signal
transfer function and crosstalk transfer function of the
simplified circuit is given in (4) and (5).

1 
  sC  Gm  Gm  U   1  (1)
R  1    R U s 
1  
  Gm  sC  Gm U 2   0 
 R 

R  Rin  Rtsv , C  C p (2)

Figure 3. Interconnect delay with different skews
 1  s
 R  s 2C m 
2 sC R As 2  Bs
Gm    si  m
 We simulate a circuit of a pair of TSVs with Spice.
 sC ox 1  2 sD
 R   s  R 2C  C  Assume the output load capacitance is 100fF. Input
 sC si  signal transition time is 30ps. The aggressor signal lags
si ox
(3)
behind at most 15ps or arrives ahead at most 15ps.
 Fig.3 and table 2 describe the experiment result of
circuit interconnect delay, which are obtained from Spice 4. Conclusion
simulation and our calculation. Because of different
aggressor signal transition pattern, interconnect delay In this paper, we propose a TSV to TSV crosstalk
either speed up or slow down. We compare the two induced delay estimation method. We also consider the
results and find that the maximum error is about 5.3%, input signal slew and the skew between signals in our
which proves our estimation is correct. Since our method equations. With these equations we simulate a common
gives delay estimation with several expressions, the most TSV pair circuit and calculate the interconnect delay.
time consuming part of solving them is Newton iteration, Known from the simulation, the maximum error is about
which cost constant time. Using Spice simulation takes 5.3%. Our method is quite accurate and fast. We can also
polynomial time which is slower than our method. find that crosstalk is the main effect on interconnect
delay while the skew has much smaller effect. Our
Table 2. Interconnect delay with different skews estimation method can be used in 3D IC static timing
Reduce delay Increase delay analysis to reduce crosstalk induced timing violation.
Skew Calcu Resul Error Calcu Resul Error
(ps) lation t (%) lation t (%) Acknowledgments
(ps) (ps) (ps) (ps)
-14 5.143 5.105 0.7 8.061 8.446 4.6 This work is supported in part by National Natural
-12 5.158 5.170 2.4 8.053 8.501 5.3 Science Foundation of China (61176037), Shanghai
-10 5.18 5.125 1.1 8.039 8.429 4.6 Aerospace Science and Technology Innovation Fund
-8 5.21 5.273 1.2 8.017 8.392 4.5 (SAST201355) and Specialized Research Fund for the
Doctoral Program of Higher Education (SRFDP:
-6 5.25 5.279 0.5 7.989 8.344 4.3
20130073110034).
-4 5.303 5.280 0.4 7.942 8.237 3.6
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