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Sanity Checks

The document describes various sanity checks that are performed in the physical design flow, including: - check_library validates the libraries by checking consistency between logical and physical libraries and within libraries. - check_timing reports unconstrained paths in the design to identify paths not optimized during physical synthesis. - report_constraints checks for worst negative slack, total negative slack, and design rule violations. - check_design checks the internal design representation for consistency and issues errors or warnings. - check_legality reports violations related to cell placement like overlaps and orientation issues.

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202 views4 pages

Sanity Checks

The document describes various sanity checks that are performed in the physical design flow, including: - check_library validates the libraries by checking consistency between logical and physical libraries and within libraries. - check_timing reports unconstrained paths in the design to identify paths not optimized during physical synthesis. - report_constraints checks for worst negative slack, total negative slack, and design rule violations. - check_design checks the internal design representation for consistency and issues errors or warnings. - check_legality reports violations related to cell placement like overlaps and orientation issues.

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PHYSICAL DESIGN SANITY CHECKS

Sanity Checks in Physical Design Flow

check_library

check_timing

report_constraint

report_timing

report_qor

check_design

check_legality

check_library:

check_library validates the libraries i.e., it performs consistency checks between logical and
physical libraries, across logical libraries, and within physical libraries. This command checks
library qualities in three main areas: Physical library quality Logic versus physical library
consistency Logic versus logic library consistency

check_timing

PNR tool wont optimize the paths which are not constrained. So we have to check any
unconstrained paths are exist in the design. check_timing command reports unconstrained
paths. If there are any unconstrained paths in the design, run the report_timing_requirements
command to verify that the unconstrained paths are false paths.

No clock_relative delay specified for input ports ____________

Unconstrained_endpoints. _________________

End-points are not constrained for maximum delay ___________________

report_constraints
It reports to check the following parameters. Worst Negative Slack (WNS) Total Negative Slack
(TNS) Design Rule Constraint Violations

report_timing

report_timing displays timing information about a design. The report_timing command provides
a report of timing information for the current design. By default, the report_timing command
reports the single worst setup path in each clock group.

report_qor

report_qor displays QoR information and statistics for the current design. This command reports
timing-path group and cell count details, along with current design statistics such as
combinational, noncombinational, and total area. The command also reports static power,
design rule violations, and compile-time details.

check_design

check_design checks the current design for consistency. The check_design command checks the
internal representation of the current design for consistency, and issues error and warning
messages as appropriate.

a. inputs/Outputs 300

b. Undriven outputs (LINT-5) 505

c. Unloaded inputs (LINT-8) 162

d. Feedthrough (LINT-29) 174

e. Shorted outputs (LINT-31) 52


f. Constant outputs (LINT-52) 24

g. Cells 152

h. Cells do not drive (LINT-1) 1

i. Connected to power or ground (LINT-32) 118

j. Nets connected to multiple pins on same cell (LINT-33) 33

k. Nets 1226

l. Unloaded nets (LINT-2) 721

Error messages indicate design problems of such severity that the compile command does not
accept the design Warning messages are informational and do not necessarily indicate design
problems. However, these messages should be investigated.

Warnings

Potential problems detected by this command include Unloaded input ports or undriven output
ports Nets without loads or drivers or with multiple drivers

Cells or designs without inputs or outputs

Mismatched pin counts between an instance and its reference

Tristate buses with non-tristate drivers wire loops across hierarchies


check_legality

reports overlap and cells placement related violation like orientation, overlaps etc.

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