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Sequential 2

Sequential

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0% found this document useful (0 votes)
50 views20 pages

Sequential 2

Sequential

Uploaded by

Tarun Eshwar
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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EECS 141 – S02

Lecture 17

Sequential Logic (2)


Multivibrator Circuits

Digital Integrated Circuits Sequential Logic © Prentice Hall 2000

Last Lecture

l Dynamic Circuits Wrap-up


» Differential Domino
» np-CMOS
» Logic Style Summary
l Introduction to Sequential Logic
» Latch vs. Flip-flop
» RS, Mux-based latch
» Master-slave flip-flop
Digital Integrated Circuits Sequential Logic © Prentice Hall 2000

1
Today’s Lecture
l Sequential Logic (Cont’d)
» Timing Definitions
» Pulse-triggered latches
» C2MOS latch
» TSPC logic
l Multi-vibrator Circuits
» Schmitt Trigger
» Monostable
» Astable (Oscillator)
Digital Integrated Circuits Sequential Logic © Prentice Hall 2000

2-phase dynamic flip-flop

φ1 φ2

In D

Input Sampled

φ1

φ2

Output Enable

Digital Integrated Circuits Sequential Logic © Prentice Hall 2000

2
Flip-Flop: Timing Definitions

t
tsetup thold
In

DATA
STABLE
t

tpFF
Out

DATA
STABLE
t

Digital Integrated Circuits Sequential Logic © Prentice Hall 2000

Delay vs. Setup/Hold Times


350

300
Minimum Data-Output
250
Clk-Output [ps]

200

150
Setup Hold

100

50

0
-200 -150 -100 -50 0 50 100 150 200
Data-Clk [ps]
Digital Integrated Circuits Sequential Logic © Prentice Hall 2000

3
Pulse-Triggered Latches
Flip-flops:

Master-Slave Pulse-Triggered
Latches Latch
L1 L2 L
Data Data
D Q D Q D Q
Clk
Clk Clk Clk
Clk

Digital Integrated Circuits Sequential Logic © Prentice Hall 2000

Propagation Delay Based Edge-Triggered

In

N1
N2
In X X tpLH

φ Out

Out

= Mono-Stable Multi-Vibrator
Digital Integrated Circuits Sequential Logic © Prentice Hall 2000

4
Pulse-Triggered Latches

Hybrid Latch – Flip-flop (HLFF), AMD K-6 and K-7 :


Vdd

Clk

Digital Integrated Circuits Sequential Logic © Prentice Hall 2000

Pulse-Triggered Latches
7474, SR latch as a second stage

S
Q

Clk
Q
R

D
Digital Integrated Circuits Sequential Logic © Prentice Hall 2000

5
Pulse-Triggered Latches
Sense-amplifier-based flip-flop, DEC Alpha 21264, StrongARM 110
l First stage is a sense
amplifier, precharged to
high, when Clk = 0
l After rising edge of the
clock sense amplifier
generates the pulse on
S or R
l The pulse is captured in
S-R latch
l Cross-coupled NAND
has different propagation
delays of rising and
falling edges
Digital Integrated Circuits Sequential Logic © Prentice Hall 2000

Maximum Clock Frequency


φ
FF’s

Also:
tcdreg + t cdlogic > thold

tcd: contamination delay =


LOGIC minimum delay
tp,comb

Digital Integrated Circuits Sequential Logic © Prentice Hall 2000

6
Master-Slave Flip-Flop

φ φ D
A
In
B

φ φ

Overlapping Clocks Can Cause


• Race Conditions
• Undefined Signals

Digital Integrated Circuits Sequential Logic © Prentice Hall 2000

Flip-flop insensitive to clock overlap

VDD VDD

M2 M6

φ M4 φ M8
X
In D
CL1 CL2
φ M3 φ M7

M1 M5

φ−section φ−section

C2 MOS LATCH
Digital Integrated Circuits Sequential Logic © Prentice Hall 2000

7
C2MOS avoids Race Conditions

VDD VDD VDD VDD

M2 M6 M2 M6

0 M4 0 M8
X X
In D In D
1 M3 1 M7

M1 M5 M1 M5

(a) (1-1) overlap (b) (0-0) overlap

Digital Integrated Circuits Sequential Logic © Prentice Hall 2000

Pipelining
REG

REG

a a
REG

REG

REG

. .
REG

φ log Out φ log Out

φ φ φ φ
REG

REG

b b
Non-pipelined version Pipelined version
φ φ

Digital Integrated Circuits Sequential Logic © Prentice Hall 2000

8
Pipelined Logic using C2MOS
VDD VDD VDD

In φ φ φ
F G Out
φ C1 φ C2 φ C3

NORA CMOS

What are the constraints on F and G?


Digital Integrated Circuits Sequential Logic © Prentice Hall 2000

Example

VDD VDD VDD

φ φ
1
φ φ

Number of a static inversions should be even

Digital Integrated Circuits Sequential Logic © Prentice Hall 2000

9
NORA CMOS Modules
VDD VDD VDD
φ φ

In1 φ Out
PUN
In2 PDN
In3 φ
φ φ (a) φ-module

Combinational logic Latch

VDD VDD VDD VDD


φ In 4

In 1 φ Out
In 2 PDN
In 3 φ
φ In4 (b) φ-module

Digital Integrated Circuits Sequential Logic © Prentice Hall 2000

TSPC - True Single Phase Clock Logic

VDD VDD VDD VDD

φ M1 φ M1 M1 M1

Out Out
φ
In M2 φ M2
In M2 M2
Out Out
In In

φ M3 φ M3 M3 M3

Precharged N Precharged P Non-precharged N Non-precharged P

Digital Integrated Circuits Sequential Logic © Prentice Hall 2000

10
TSPC - True Single Phase Clock Logic

VDD VDD VDD VDD

PUN

In
Static
φ φ φ φ
Logic Out

PDN

Including logic into Inserting logic between


the latch latches

Digital Integrated Circuits Sequential Logic © Prentice Hall 2000

Doubled TSPC Latches

VDD VDD VDD VDD

Out
In In
φ φ φ φ Out

Doubled n-TSPC latch Doubled p-TSPC latch

Digital Integrated Circuits Sequential Logic © Prentice Hall 2000

11
TSPC - True Single Phase Clock Logic

VDD VDD VDD VDD

PUN

In
Static
φ φ φ φ
Logic Out

PDN

Including logic into Inserting logic between


the latch latches

Digital Integrated Circuits Sequential Logic © Prentice Hall 2000

Master-Slave TSPC Flip-flops

VDD VDD VDD VDD V DD VDD

φ φ
Y
D D
D X
φ φ φ φ
D
φ φ

(a) Positive edge-triggered D flip-flop (b) Negative edge-triggered D flip-flop

VDD VDD VDD

D D
φ φ

(c) Positive edge-triggered D flip-flop


using split-output latches

Digital Integrated Circuits Sequential Logic © Prentice Hall 2000

12
Latches versus Registers
Latch: level-sensitive circuit passing the input to the output
when the latch is enabled - otherwise it is in hold
Positive Latch Negative Latch

In D Q Out In D Q Out
G G
CLK
CLK

clk clk

In In

Out Out

Out Out Out Out


stable followsIn stable followsIn

Edge-triggered register: samples the input on clock transition

Digital Integrated Circuits Sequential Logic © Prentice Hall 2000

Edge Triggered Flip-Flop

S Q Q

R Q Q

J
Q

Q
K

Digital Integrated Circuits Sequential Logic © Prentice Hall 2000

13
JK Latch

Jn Kn Qn+1
J S Q Q
0 0 Qn
φ 1
0 0
K R Q Q 1 0 1
1 1 Qn

(c)
(a) J Q
φ
K Q

(b)

Digital Integrated Circuits Sequential Logic © Prentice Hall 2000

Other Flip-Flops

T J D J
Q Q
φ φ φ φ
Q Q
K K

T Q D Q

φ Q φ Q

Toggle Flip-Flop Delay Flip-Flop

Digital Integrated Circuits Sequential Logic © Prentice Hall 2000

14
Multivibrator Circuits

Digital Integrated Circuits Sequential Logic © Prentice Hall 2000

Schmitt Trigger

V ou t VOH
In Out

•VTC with hysteresis V OL

•Restores signal slopes


VM – VM + V in

Digital Integrated Circuits Sequential Logic © Prentice Hall 2000

15
Noise Suppression using
Schmitt Trigger

Vin Vout

VM+

VM–

t0 t t0 + tp t

Digital Integrated Circuits Sequential Logic © Prentice Hall 2000

CMOS Schmitt Trigger


VDD

M2 M4

Vin X
Vout

M1 M3

Moves switching threshold


of first inverter

Digital Integrated Circuits Sequential Logic © Prentice Hall 2000

16
Schmitt Trigger
Simulated VTC

5.0 6.0

4.0

4.0
3.0

Vout (V)
V M+
VX (V)

2.0
2.0
V M-
1.0

0.0 0.0
0.0 1.0 2.0 3.0 4.0 5.0 0.0 1.0 2.0 3.0 4.0 5.0
Vin (V) V in (V)

Digital Integrated Circuits Sequential Logic © Prentice Hall 2000

CMOS Schmitt Trigger (2)


VDD

M4

M6

M3
In Out

M2
X
M5 VDD

M1

Digital Integrated Circuits Sequential Logic © Prentice Hall 2000

17
Multivibrator Circuits
R

S
Bistable Multivibrator
flip-flop, Schmitt Trigger

T
Monostable Multivibrator
one-shot

Astable Multivibrator
oscillator

Digital Integrated Circuits Sequential Logic © Prentice Hall 2000

Transition-Triggered Monostable

In
DELAY
Out
td td

Digital Integrated Circuits Sequential Logic © Prentice Hall 2000

18
Monostable Trigger (RC-based)

VD D

In R
A B Out

(a) Trigger circuit.


C

In

B VM
(b) Waveforms.

Out
t
t1 t2

Digital Integrated Circuits Sequential Logic © Prentice Hall 2000

Astable Multivibrators (Oscillators)


0 1 2 N-1

Ring Oscillator

V1 V3 V5
5.0
V (Volt)

3.0

1.0

-1.0
0 1 2 3 4 5
t (nsec)

simulated response of 5-stage oscillator

Digital Integrated Circuits Sequential Logic © Prentice Hall 2000

19
Voltage Controller Oscillator (VCO)

Schmitt Trigger
V DD VDD
restores signal slopes
M6 M4

M2
In
M1
Iref Iref
Vcontr M3
M5 Current starved inverter

6
t pH L (nsec)

propagation delay as a function


0.0
0.5 1.5 2.5 of control voltage
V contr (V)

Digital Integrated Circuits Sequential Logic © Prentice Hall 2000

Relaxation Oscillator

Out1
Out 2
I1 I2

R C

Int

T = 2 (log3) RC

Digital Integrated Circuits Sequential Logic © Prentice Hall 2000

20

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