Sequential 2
Sequential 2
Lecture 17
Last Lecture
1
Today’s Lecture
l Sequential Logic (Cont’d)
» Timing Definitions
» Pulse-triggered latches
» C2MOS latch
» TSPC logic
l Multi-vibrator Circuits
» Schmitt Trigger
» Monostable
» Astable (Oscillator)
Digital Integrated Circuits Sequential Logic © Prentice Hall 2000
φ1 φ2
In D
Input Sampled
φ1
φ2
Output Enable
2
Flip-Flop: Timing Definitions
t
tsetup thold
In
DATA
STABLE
t
tpFF
Out
DATA
STABLE
t
300
Minimum Data-Output
250
Clk-Output [ps]
200
150
Setup Hold
100
50
0
-200 -150 -100 -50 0 50 100 150 200
Data-Clk [ps]
Digital Integrated Circuits Sequential Logic © Prentice Hall 2000
3
Pulse-Triggered Latches
Flip-flops:
Master-Slave Pulse-Triggered
Latches Latch
L1 L2 L
Data Data
D Q D Q D Q
Clk
Clk Clk Clk
Clk
In
N1
N2
In X X tpLH
φ Out
Out
= Mono-Stable Multi-Vibrator
Digital Integrated Circuits Sequential Logic © Prentice Hall 2000
4
Pulse-Triggered Latches
Clk
Pulse-Triggered Latches
7474, SR latch as a second stage
S
Q
Clk
Q
R
D
Digital Integrated Circuits Sequential Logic © Prentice Hall 2000
5
Pulse-Triggered Latches
Sense-amplifier-based flip-flop, DEC Alpha 21264, StrongARM 110
l First stage is a sense
amplifier, precharged to
high, when Clk = 0
l After rising edge of the
clock sense amplifier
generates the pulse on
S or R
l The pulse is captured in
S-R latch
l Cross-coupled NAND
has different propagation
delays of rising and
falling edges
Digital Integrated Circuits Sequential Logic © Prentice Hall 2000
Also:
tcdreg + t cdlogic > thold
6
Master-Slave Flip-Flop
φ φ D
A
In
B
φ φ
VDD VDD
M2 M6
φ M4 φ M8
X
In D
CL1 CL2
φ M3 φ M7
M1 M5
φ−section φ−section
C2 MOS LATCH
Digital Integrated Circuits Sequential Logic © Prentice Hall 2000
7
C2MOS avoids Race Conditions
M2 M6 M2 M6
0 M4 0 M8
X X
In D In D
1 M3 1 M7
M1 M5 M1 M5
Pipelining
REG
REG
a a
REG
REG
REG
. .
REG
φ φ φ φ
REG
REG
b b
Non-pipelined version Pipelined version
φ φ
8
Pipelined Logic using C2MOS
VDD VDD VDD
In φ φ φ
F G Out
φ C1 φ C2 φ C3
NORA CMOS
Example
φ φ
1
φ φ
9
NORA CMOS Modules
VDD VDD VDD
φ φ
In1 φ Out
PUN
In2 PDN
In3 φ
φ φ (a) φ-module
In 1 φ Out
In 2 PDN
In 3 φ
φ In4 (b) φ-module
φ M1 φ M1 M1 M1
Out Out
φ
In M2 φ M2
In M2 M2
Out Out
In In
φ M3 φ M3 M3 M3
10
TSPC - True Single Phase Clock Logic
PUN
In
Static
φ φ φ φ
Logic Out
PDN
Out
In In
φ φ φ φ Out
11
TSPC - True Single Phase Clock Logic
PUN
In
Static
φ φ φ φ
Logic Out
PDN
φ φ
Y
D D
D X
φ φ φ φ
D
φ φ
D D
φ φ
12
Latches versus Registers
Latch: level-sensitive circuit passing the input to the output
when the latch is enabled - otherwise it is in hold
Positive Latch Negative Latch
In D Q Out In D Q Out
G G
CLK
CLK
clk clk
In In
Out Out
S Q Q
R Q Q
J
Q
>φ
Q
K
13
JK Latch
Jn Kn Qn+1
J S Q Q
0 0 Qn
φ 1
0 0
K R Q Q 1 0 1
1 1 Qn
(c)
(a) J Q
φ
K Q
(b)
Other Flip-Flops
T J D J
Q Q
φ φ φ φ
Q Q
K K
T Q D Q
φ Q φ Q
14
Multivibrator Circuits
Schmitt Trigger
V ou t VOH
In Out
15
Noise Suppression using
Schmitt Trigger
Vin Vout
VM+
VM–
t0 t t0 + tp t
M2 M4
Vin X
Vout
M1 M3
16
Schmitt Trigger
Simulated VTC
5.0 6.0
4.0
4.0
3.0
Vout (V)
V M+
VX (V)
2.0
2.0
V M-
1.0
0.0 0.0
0.0 1.0 2.0 3.0 4.0 5.0 0.0 1.0 2.0 3.0 4.0 5.0
Vin (V) V in (V)
M4
M6
M3
In Out
M2
X
M5 VDD
M1
17
Multivibrator Circuits
R
S
Bistable Multivibrator
flip-flop, Schmitt Trigger
T
Monostable Multivibrator
one-shot
Astable Multivibrator
oscillator
Transition-Triggered Monostable
In
DELAY
Out
td td
18
Monostable Trigger (RC-based)
VD D
In R
A B Out
In
B VM
(b) Waveforms.
Out
t
t1 t2
Ring Oscillator
V1 V3 V5
5.0
V (Volt)
3.0
1.0
-1.0
0 1 2 3 4 5
t (nsec)
19
Voltage Controller Oscillator (VCO)
Schmitt Trigger
V DD VDD
restores signal slopes
M6 M4
M2
In
M1
Iref Iref
Vcontr M3
M5 Current starved inverter
6
t pH L (nsec)
Relaxation Oscillator
Out1
Out 2
I1 I2
R C
Int
T = 2 (log3) RC
20