EE3801 Tutorial – 1

Introduction to Xilinx Webpack 6.3

Fall 2005
Written by Ahmad Hatami
Modified by Ted Clancy and Samant Kakarla

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 Please have all individual components created in this
lab available to all parties working together to complete
the lab. Make sure everyone also has the components
available individually from previous labs. It is a good
idea to backup your data on another media apart from
the network space you have available.

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 Objective ......................................................................................................................... 4
Design Flow Overview ....................................................................................................... 4
Project I - Adder.................................................................................................................. 4
Half Adder ...................................................................................................................... 4
Design Entry ............................................................................................................... 6
Generating a Test-bench Waveform for Functional Verification ................................... 9
Functional Simulation for Design Verification........................................................... 9
Xilinx, Spartan-3 Starter Kit Board .............................................................................. 11
Synthesis ........................................................................................................................... 13
Simulation for Synthesis and Timing Verification ....................................................... 14
Implementation and Downloading .................................................................................... 16
Hierarchical Design and Symbols ..................................................................................... 17
Full Adder ..................................................................................................................... 18
Project II – Four bit Multiplier.......................................................................................... 21
Introduction ................................................................................................................... 21
Implementation ............................................................................................................. 22
Summary ........................................................................................................................... 24
References ..................................................................................................................... 24

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Objective
After completion of this tutorial you will be able to use Xilinx Webpack to capture,
simulate, test, and download your design into a Spartan-3 Starter Kit Board. The tutorial
is in two parts. In part one we provide an overview of a design flow in general. In part
two you will complete the following two projects:

1. Adder (Half adder and Full adder)

2. Four bit multiplier

Design Flow Overview

Design flow for gate array devices (CPLD or FPGA) can be divided in three steps, as
depicted in Figure 2.

Design Entry: You enter your design into the system by a schematic editor or through
HDL (Hardware Description Languages such as VHDL, Verilog, ABEL …). Your design
may include different gates, FSM (Finite State Machines …)

Implementation: Design tools translate your design to an optimized format suitable to

your target device. The output of this step is a bit stream file that can be downloaded into
the hardware.

Verification: Simulators are used for functional and timing verification of a design.
Functional simulation verifies the behavior of the system without any knowledge of the
underlying target and does not provide timing parameters. Timing simulation provides
various timing analysis after the design has been compiled for a target.

Figure 3 shows a more detailed design flow diagram for FPGA or CPLD devices. Our
projects are targeted for Xilinx Spartan-3 FPGA. For more information Spartan-3 board
refer to [1].

Project I - Adder
Half Adder

Half adder adds two binary inputs (a and b) and generates two outputs Sum and Cout
Figure 1. In the following sections you will implement a half adder.

a Sum a b Sum Cout

0 0 0 0
b H.A Cout 0 1 1 0
1 0 1 0
1 1 0 1
Figure 1

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 Figure 2

Figure 3

1. Start Xilinx Project Navigator by clicking on

2. Create a new project as shown in Figure 4. Use your “M:” drive as the project
location for your files. Make sure there are no spaces in the folder that you create
for your work.

Figure 4

3. Select the device parameters as shown in Figure 5.

4. Click on Finish to complete the project creation (Figure 6).

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 Figure 5

Figure 6

Design Entry

5. Add a new source to your new project. Select schematic as type of the source file
(Figure 7).
6. Double click on your newly generated source file. This opens the schematic editor
(Figure 8).

Figure 7

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 Figure 8

7. Add a wire to your design by clicking on icon.

8. Click on to add an IO marker at the end of the newly generated wire.
9. Double click (or, right click) on the newly generated IO marker and change the
object properties based on Figure 9.
10. Repeat the same process to add a second wire with an associated IO marker and
name the marker b your schematic should be similar to Figure 10.

Figure 9

Figure 10

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 11. Click on the “Symbols” tab and add an and2 gate (in the logic category) to your
schematic (Figure 11).
12. Connect input a, and b to the inputs of the and2 gate.
13. Add a wire and an output marker to the output of the and2 gate and change its
properties (Figure 12).

Figure 11

Figure 12

14. Add an XOR gate to your design and add three wires two for inputs and one for
its output.
15. Add an output IO marker to the output of the XOR gate and changes its name to
Sum.
16. Click on and enter ‘a’ in the dialogue box.
17. Click on the input pin of the XOR gate (Figure 13)1.
18. Similarly, name the second XOR input pin ‘b’.
19. Your design should be similar to Figure 14.
20. Save your file and click on ‘Check Schematic’ in the “Tools” menu as depicted on
Figure 14. If any errors are detected, they will need to be corrected.

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Each wire is called a net. Two nets with the same name are connected although there is no connecting line
between them

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 Figure 13

Figure 14

Generating a Test-bench Waveform for Functional Verification

Functional Simulation for Design Verification

In this section you will learn how to create and use a test-bench waveform to verify the
functional behavior of your design.

21. On project navigator add a new source file through the project pull down menu
(or toolbar).
22. Complete test-bench waveform generation as depicted in Figure 15. This opens
the test-bench waveform shown in Figure 16.

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23. Note that there are four distinct waveforms corresponding to the four IO markers
in your design. The horizontal axis indicates time. Note that you can toggle the
level of the input signals (a, b) by clicking.
24. Generate all possible input combinations (00,01,10,11) and save the waveform
(Figure 17)

Figure 15

Figure 16

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 25. As shown in Figure 17, switch to the “Process view” and double click on
‘Generate Expected Simulation Results’ on the project navigator.
26. Click ‘Yes’ in response for file reloading. The resulting screen shows the output
signals for Sum and Cout corresponding to the inputs a and b.
27. Are the outputs as you expected then to be?

Figure 17

Figure 18

Xilinx, Spartan-3 Starter Kit Board

Reference [1] provides the detail information about the Spartan-3 Starter board. Figure 19
provides the overall architecture of the board with its major components. Spartan-3 board
provides eight sliding switches (SW0-SW7) and four push buttons (BTN3-BTN0) that
can be used as inputs. Each of these switches are connected to an associated IO pin of the
FPGA Table 1 and Table 2 show these connections for sliding switches and push buttons
respectively. Both Slide switches and push buttons are active high, in other words when
they are in on status they connect VCCO to the FPGA IO pin. Note that there is no
debouncing circuitry for these inputs. There eight surface mounted LED’s on the board

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that can be used as an output for your design (LD7-LD0). Table 3 shows the connections
of the LED’s to the FPGA’s IO pins. The LED’s are all active high, so to turn an LED
ON you need to apply a logic high to the corresponding IO pin of the FPGA.

Figure 19

Table 1

Table 2

Table 3

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Synthesis
You have completed your design entry and functional verification of a HA (Half Adder)
in previous steps without any assumptions about the underlying target. In this section you
will compile your design targeted for Spartan-3 FPGA device by assigning input ports a,
b, to SW1-SW0 and outputs Sum, and Cout to LD6-LD7 on the board respectively. The
following steps show you how you can create a user constraint file that assigns these
mappings.

28. In your project navigator session, make sure that the schematic file for HA is
selected, and on the process view panel, under “User Constraints”, double click
on ‘Create Timing Constraints’ as shown in Figure 20.

Figure 20
29. Click on ‘Yes’ for the dialogue box.
30. Select the “Ports” tab in the upcoming dialogue box. (Figure 21)
31. Each row in that table corresponds to one of the IO pins in your design. Enter the
corresponding locations for each IO port. Note that these connections are based
on Table 1 and Table 2. Your inputs are stored in a text file with the ‘ucf’
extension; the content of such a file is shown at the bottom of the dialogue box.

Figure 21

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 32. Save the user constraints file and close the dialogue box.

Simulation for Synthesis and Timing Verification

33. In the project navigator session make sure that the HA testbench waveform that
you had generated before is selected and double click on ‘Simulate Behavioral
Model’ on the process panel (Figure 22). This will launch the modelsim simulator
and opens several windows.
34. Select the Wave window in your modelsim simulator.
35. Click on (zoom out) button several times until you can see the entire time
span of the simulation Figure 23. This waveform simulates the behavior of the
systems as the inputs a and b change. Note that any change on input ports causes
an immediate effect at the outputs, in other words there is no propagation delay in
this simulation.
36. Close the modelsim simulator.

Figure 22

Figure 23

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37. In the project navigator session make sure that the HA testbench waveform that
you had generated before is selected and double click on ‘Simulate Post-
Translate VHDL Model’ on the process panel. This will launch the modelsim
simulator and opens several windows. This process compiles your design for your
target (Spartan-3) without any consideration of the IO constraints you have
defined.
38. Select the Wave window in your modelsim simulator.
39. Click on (zoom out) button several times until you can see the entire time
span of the simulation (Figure 24). This waveform simulates the behavior of the
systems as inputs a/b change.
40. Select the signal associated to the b input by clicking on that.
41. Click on button. This will take the cursor to the next signal event.
42. Click on button. This creates a fixed cursor indicator on the panel.
43. Select the Sum signal by clicking on that. Note that this signal has changed
because of the change on the b input with a time delay.
44. Create a cursor at the changing location of this signal as you did in previous steps.
45. Make a note of the time difference between the two cursor locations.
46. Close the modelsim simulator.
47. In the project navigator session make sure that the HA testbench waveform that
you had generated before is selected and double click on ‘Simulate Post-Place
and Route VHDL Model’ on the process panel. This will launch the modelsim
simulator and opens several windows. This process compiles your design for your
target (Spartan-3) by applying the IO constraints that you have defined.
48. Follow the steps as before and find the propagation delay for the same set of
signals (Figure 25). Can you see any difference? If so, explain the cause of this
difference.

Figure 24

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 Figure 25

Implementation and Downloading

49. In the project navigator session make sure that the HA schematic file is selected
and double click on ‘Configure Device (iMPACT)’ on the process panel
under ‘Generate Programming File’ subgroup. This generates the downloadable
bitstream file and launchs iMPACT. Follow the upcoming dialogue boxes as
depicted in Figure 26.
50. Select the *.bit file and associate that with the first chip. Click bypass for the
second chip
51. Click OK on the Startup clock warning window.
52. Right click on the first chip and follow the dialogue boxes (Figure 27).
53. Now you can test your design by toggling SW0 and SW1 and see the Sum, and
Cout output on LD6-LD7. Try different combination of inputs and make sure that
your design works properly.
54. Close iMPACT.

Figure 26

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 Figure 27

Hierarchical Design and Symbols

In most projects it is desirable to design components that can be reusable in your future
projects. In this section you will create a symbol for your HA that can be used in the rest
of the project.
55. Open the schematic file that you have designed for your HA circuit.
56. Start the symbol wizard through the ‘Tools’ pull down menu.
57. Follow the dialogue boxes as appear in Figure 28.
58. By completing this process you have created a new symbol for your HA design
that can be reused in future

Figure 28

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Full Adder
In this section you will design a full adder. Figure 29 shows the input-output interface of
a full adder. Three single bit inputs (a, b, Cin) are added together and the result appears as
Sum, and Cout on the output ports. Obviously you can design such a circuit using basic
gates, but here you want to use your previous HA as the main building block

a Sum

b
F.A
Cout
Cin

Figure 29

59. Open the project navigator and add a new source file to your project through the
project pull down menu (Figure 30), and open the new file.
60. Note that on the category subsection of the symbol tab there is file associated to
the symbols that you have generated. Click on that and you should see HA as one
of the symbols. Add a HA symbol to your design.
61. Right click on the HA symbol and select symbol-Push Into Symbol. You will see
your original HA design.
62. Close the HA schematic and complete the FA (Full Adder) circuit as depicted in
Figure 31. Check the schematic and save the file.

Figure 30

(a) (b)
Figure 31

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63. Create a new testbench (myFA_tbwf) waveform and associate it with your FA
schematic (Figure 32).

Figure 32

64. Apply all possible input combinations for inputs (a, b, cin) and click on ‘Generate
Expected Simulation Results’ (Figure 33). Make sure that generated outputs are
correct.
65. Open the user constraint file that you have generated for HA before. Add a user
constraints file.
66. At the same time create a users constraint file for your full adder (Figure 34Figure
33).
67. Copy and paste the content of the HA constraint file to your FA constraint file.
Note that for a FA you need another input (Cin), thus add a new line in your
constraint file and assign SW2 as the Cin input. The resulting constraint file
should be similar to Figure 35.
68. Save the constraint file, select FA schematic file and click on ‘Configure Device’
on the process view.

Figure 33

Figure 34

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 Figure 35

69. You will observe some errors on the console. Scroll through the errors and you
will notice that the compiler is complaining that there is not an IO marker with the
name ‘Sum’ in your FA design. To correct this error you need to either rename
the output port in your schematic or change your constraint file. Here we change
the port name on the schematic (Figure 36).
70. Save your schematic.
71. Generate the bit file and download it to the board and make sure that it works
correctly.
72. Create a new symbol for your FA implementation and add it to your personal
library, as you did for the HA (Figure 36).
73. Congratulation you have completed Project I of this tutorial.

Figure 36

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Project II – Four bit Multiplier
In this project you will implement a four bit multiplier with combinational circuits. You
will learn how two use buses to reduce the amount of wirings in your designs.

Introduction
Figure 37 shows the IO interface of a 4-bit multiplier. Two 4-bit inputs (a3 a2 a1 a0 – b3 b2
b1 b0) are fed into the system the product of the two binary numbers which is an 8-bit
output (S7…S0)
4
a
4-bit 8
4 S
b Mult.

Figure 37
Multiplication of two binary numbers is a sequence of shifting and adding. Table 4 shows
this process for multiplication of two 4-bit numbers.

A3 A2 A1 A0
B3 B2 B1 B0
A3.B0 A2.B0 A1.B0 A0.B0
A3.B1 A2.B1 A1.B1 A0.B1
A3.B2 A2.B2 A1.B2 A0.B2
A3.B3 A2.B3 A1.B3 A0.B3
S7 S6 S5 S4 S3 S2 S1 S0
Table 4

We can implement the above process by generating all partial products (and operation
between two bits) and adding them together using HA or FA to sum each column as
depicted in Figure 38.

A 3 .B 3 A 3 .B 2 A 2.B 3 A 3 .B 1 A 2.B 2 A 1 .B 3 A 3 .B 0 A 2 .B 1 A 1.B 2 A 0 .B 3 A 2.B 0 A 1 .B 1 A 0 .B 2 A 0 .B 1 A 1 .B 0 A 0 .B 0

FA FA FA FA HA

FA FA HA

FA FA HA HA

S7 s6 S5 s4 S3 S2 S1 S0

Figure 38

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Implementation
1. Open your project navigator and create a new schematic file. Name the file
‘my4bitMult’
2. Open your newly created file.
3. Add three wires and connect two of them to an input IO marker and one to an
output IO marker. Name them a(3:0), b(3:0), and S(3:0) respectively. This
indicates that inputs a and b are 4-bit buses and S is an 8-bit bus. Each individual
i’th bit of a bus; for example a; can be accessed by a(i) notation (Figure 39).
4. Complete your design by using Figure 38 and use your own HA and FA symbols.
Check your schematic and save your design.
5. Create a test-bench waveform to verify your design.
6. Note that in your test-bench waveform you can assign patterns to inputs a and b.
7. For input a assign a pattern which goes from 0 until 15, and for input b select a
decrementing pattern starting from 15 until 0 (Figure 40).
8. Double click on ‘Generate Expected Simulation Results’ and make sure that the
results are correct.
9. Create a user constraints file for your design as depicted in Figure 41. You will
use SW7-SW4), (SW3-SW0) and (LD7-LD0) for IO pins a, b and S respectively.
10. Create a symbol for your design so you can use it.

Figure 39

Figure 40

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 Figure 41

11. Run a Post Translate VHDL model simulation and generate the associated
waveform (Figure 42).
12. Run a Post Place and Route VHDL model simulation and generate the associated
waveform and compare this waveform with the one generated in the previous step
(Figure 43).
13. How do you evaluate the performance of this multiplier? Can you identify any
advantage or disadvantage for this design?

Figure 42

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 Figure 43

Summary
 You should be able to describe a Design flow for digital systems
 You learned how to use Xilinx Webpack tools to enter a design, synthesize and
download your implementation to a target board
 You learned how to use Modelsim to create stimulus signals, verify functional
and timing behavior of a digital system.
 You learned how to use a hierarchical strategy in your designs in order to be able
to reuse your work
 You learned how to implement a 4-bit multiplier

References

[1] Xilinx, ‘Spartan-3 Starter Kit Board User Guide’

[2] Logic Design: Randy Katz, Gaetano Borriello, Contemporary Logic Design,
Pearson Education, 2005.

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